GS88236BB-166T_技术文档

GS88218/36BB/D-250/225/200/166/150/133

119- and 165-Bump BGA

Commercial Temp

Industrial Temp 9Mb SCD/DCD Sync Burst SRAMs

250 MHz–133MHz

512K x 18, 256K x 36

2.5 V or 3.3 V V_DD

2.5 V or 3.3 V I/O

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip read parity checking; even or odd selectable

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119- and 165-bump BGA packages

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

Register.

SCD and DCD Pipelined Reads

The GS88218/36B is a SCD (Single Cycle Deselect) and DCD

(Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

t

2.5 2.7 3.0 3.4 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.7 7.5 ns

KQ

tCycle

Curr (x18) 280 255 230 200 185 165 mA

Curr (x32/x36) 330 300 270 230 215 190 mA

3.3 V

2.5 V

Curr (x18) 275 250 230 195 180 165 mA

Curr (x32/x36) 320 295 265 225 210 185 mA

Byte Write and Global Write

Flow

Through

2-1-1-1

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

t

5.5 6.0 6.5 7.0 7.5 8.5 ns

KQ

tCycle

Curr (x18) 175 165 160 150 145 135 mA

Curr (x32/x36) 200 190 180 170 165 150 mA

3.3 V

2.5 V

Curr (x18) 175 165 160 150 145 135 mA

Curr (x32/x36) 200 190 180 170 165 150 mA

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Functional Description

Applications

Sleep Mode

The GS88218/36B is a 9,437,184-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Core and Interface Voltages

The GS88218/36B operates on a 2.5 V or 3.3 V power supply. All

input are 3.3 V and 2.5 V compatible. Separate output power

(V_DDQ) pins are used to decouple output noise from the internal

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

circuits and are 3.3 V and 2.5 V compatible.

Rev: 1.00b 12/2002

1/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).

GS88218/36BB/D-250/225/200/166/150/133

165 Bump BGA—x18 Commom I/O—Top View (Package D)

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

NC

A

E1

BB

NC

E3

BW

ADSC

ADV

A18

A

B

C

D

E

F

NC

A

E2

NC

BA

CK

GW

G

ADSP

A

NC

ZQ

NC

DQA

ZZ

NC

V

DDQ

SS

DD

SS

DD

DDQ

NC

DQB

MCL

NC

V

NC

G

H

J

NC

G

H

J

FT

NC

DQB

NC

V

DQA

NC

A

NC

DDQ

K

L

NC

V

NC

K

L

NC

M

N

P

R

NC

M

N

P

R

SCD

NC

V

NC

TDI

NC

A1

A0

NC

V

NC

DDQ

SS

DDQ

A

TDO

TCK

A

A17

A

LBO

NC

A

TMS

A

11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch

Rev: 1.00b 12/2002

2/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

165 Bump BGA—x36 Common I/O—Top View (Package D)

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

NC

A

E1

BC

BB

E3

BW

ADSC

ADV

NC

A

B

C

D

E

F

NC

A

E2

BD

BA

CK

GW

G

ADSP

A

NC

DQB

ZZ

DQC

FT

NC

V

NC

DDQ

SS

DD

SS

DD

DDQ

DQC

MCL

DQD

SCD

NC

V

DQB

ZQ

G

H

J

G

H

J

NC

DQD

NC

V

DQA

NC

DQA

A17

A

DDQ

K

L

V

K

L

M

N

P

R

M

N

P

R

V

NC

TDI

NC

A1

A0

NC

V

SS

DDQ

SS

DDQ

A

TDO

TCK

A

LBO

NC

A

TMS

A

11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch

Rev: 1.00b 12/2002

3/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

GS88236B Pad Out

119 Bump BGA—Top View

1

2

3

4

ADSP

ADSC

V_DD

ZQ

5

6

7

A

V_DDQ

NC

A6

A7

A8

A9

V_DDQ

NC

B

C

D

E

F

E2

A4

A15

A14

V_SS

BB

A17

NC

A5

A3

A16

NC

DQC4

DQC3

V_DDQ

DQC2

DQC1

V_DDQ

DQD1

DQD2

V_DDQ

DQD3

DQD4

NC

DQC9

DQC8

DQC7

DQ^C6

DQC5

V_DD

DQD5

DQD6

DQD7

DQD8

DQD9

A2

V_SS

BC

DQB9

DQB8

DQB7

DQB6

DQB5

V_DD

DQA5

DQA6

DQA7

DQA8

DQA9

A13

DQB4

DQB3

V_DDQ

DQB2

DQB1

V_DDQ

DQA1

DQA2

V_DDQ

DQA3

DQA4

PE

E1

G

H

J

ADV

GW

V_DD

CK

V_SS

NC

V_SS

BD

V_SS

NC

K

L

V_SS

BA

SCD

BW

A1

V_SS

LBO

A10

TDI

V_SS

FT

M

N

P

R

T

A0

V_DD

A11

NC

A12

TDO

NC

ZZ

V_DDQ

TMS

TCK

NC

V_DDQ

U

Rev: 1.00b 12/2002

4/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

GS88218B Pad Out

119 Bump BGA—Top View

1

2

3

4

ADSP

ADSC

V_DD

ZQ

5

6

7

V_DDQ

NC

A6

A7

A8

A9

V_DDQ

NC

A

E2

A4

A15

A14

V_SS

NC

A17

B

C

D

E

F

NC

A5

A3

A16

NC

DQB1

NC

V_SS

BB

DQA9

NC

DQB2

NC

E1

DQA8

V_DDQ

DQA6

NC

V_DDQ

NC

G

DQA7

NC

DQ^B3

NC

V_DD

DQB5

NC

ADV

GW

V_DD

CK

G

H

J

DQB4

V_DDQ

NC

V_SS

NC

V_SS

NC

V_SS

LBO

A11

TDI

V_SS

NC

DQA5

V_DD

NC

V_DDQ

DQA4

NC

V_SS

BA

K

L

DQB6

V_DDQ

DQB8

NC

SCD

BW

A1

DQA3

NC

DQB7

NC

V_SS

FT

V_DDQ

NC

M

N

P

R

T

DQA2

NC

DQB9

A2

A0

DQA1

PE

NC

V_DD

NC

A13

NC

A10

A12

TDO

A18

ZZ

V_DDQ

TMS

TCK

NC

V_DDQ

U

BPR1999.05.18

Rev: 1.00b 12/2002

5/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

GS88218/36 BGA Pin Description

Symbol

A⁰, A¹

An

Type

Description

I

Address field LSBs and Address Counter Preset Inputs

Address Inputs

A^17,A¹⁸

DQ^A1–DQ^A9

DQ^B1–DQ^B9

DQ^C1–DQ^C9

DQ^D1–DQ^D9

I/O

Data Input and Output pins

B^A, BB, BC, BD

I

—

I

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

No Connect

NC

No Connect

CK

Clock Input Signal; active high

BW

I

Byte Write—Writes all enabled bytes; active low

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

GW

I

E¹

I

E3

I

Chip Enable; active low

E²

I

Chip Enable; active high

G

ADV

I

Output Enable; active low

I

Burst address counter advance enable; active l0w

Address Strobe (Processor, Cache Controller); active low

Sleep mode control; active high

ADSC, ADSP

ZZ

I

FT

I

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

LBO

I

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

ZQ

I

Scan Test Mode Select

Scan Test Data In

TMS

TDI

O

I

Scan Test Data Out

TDO

TCK

MCL

SCD

Scan Test Clock

—

I

Must Connect Low

Single Cycle Deselect/Dual Cyle Deselect Mode Control

Core power supply

V

DD

V

I

I/O and Core Ground

SS

V

I

Output driver power supply

DDQ

Rev: 1.00b 12/2002

6/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

GS88218/36B (PE = 0) Block Diagram

^RegisteQ^r

A0–An

D

A0

A1

A0

A1

D0

D1

Q0

Q1

Counter

A

Load

LBO

ADV

CK

Memory

Array

ADSC

ADSP

Q

D

Register

GW

BW

BA

D

Q

36

Register

D

Q

BB

BC

BD

4

Register

D

Q

Register

D

Q

Register

36

D

Q

36

32

Register

E1

D

Q

4

36

Parity

Register

Encode

4

D

Q

Parity

Compare

FT

G

36

SCD

Power Down

Control

DQx1–DQx9

NC

ZZ

Note: Only x36 version shown for simplicity.

Rev: 1.00b 12/2002

7/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

GS88218/36B (PE = 1) x32 Mode Block Diagram

^RegisteQ^r

A0–An

D

A0

A1

A0

A1

D0

D1

Q0

Q1

Counter

A

Load

LBO

ADV

CK

Memory

Array

ADSC

ADSP

Q

D

Register

GW

BW

BA

D

Q

36

4

Parity

Register

Encode

D

Q

BB

BC

BD

32

4

Register

D

Q

Register

D

Q

Register

32

D

Q

36

Register

36

D

Q

Register

E1

D

Q

4

32

Register

Parity

D

Q

Register

Encode

D

Q

4

Parity

Compare

FT

G

32

SCD

Power Down

Control

DQx1–DQx8

NC

ZZ

Note: Only x36 version shown for simplicity.

Rev: 1.00b 12/2002

8/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

Mode Pin Functions

Mode Name

Name

State

Function

L

Linear Burst

Interleaved Burst

Flow Through

Pipeline

Burst Order Control

Output Register Control

Power Down Control

LBO

H

L

FT

H or NC

L or NC

H

Active

ZZ

Standby, I = I

DD SB

L

Dual Cycle Deselect

Single Cycle Deselect

Single/Dual Cycle Deselect Control

Note:

SCD

H or NC

There are pull-up devices on the SCD and FT pins and a pull-down devices on the ZZ pin, so those input pins can be unconnected and the chip

will operate in the default states as specified in the above tables.

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16, x32, or x64) mode.

Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM.

Burst Counter Sequences

Linear Burst Sequence

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

1st address

2nd address

3rd address

4th address

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Note: The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Rev: 1.00b 12/2002

9/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

Byte Write Truth Table

Function

Read

GW

H

BW

H

L

BA

X

BB

X

BC

X

BD

X

Notes

1

Read

H

L

H

L

H

L

H

L

1

Write byte a

Write byte b

Write byte c

Write byte d

Write all bytes

H

L

2, 3

H

L

H

L

2, 3

H

L

H

L

2, 3, 4

H

L

H

L

H

L

X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x36 version.

Rev: 1.00b 12/2002

10/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

Synchronous Truth Table

Operation

State

3

4

Diagram

Address Used

E1

ADSP ADSC

ADV

W

DQ

5

Key

Deselect Cycle, Power Down

Read Cycle, Begin Burst

None

External

R

H

L

X

L

X

L

X

L

X

F

T

F

T

F

T

High-Z

Q

D

Q

D

Q

D

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

R

L

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

W

L

CR

CW

H

Current

H

Notes:

1. X = Don’t Care, H = High, L = Low

2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding

3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.00b 12/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

Simplified State Diagram

X

Deselect

W

R

W

R

X

R

X

First Write

First Read

CW

CR

W

R

X

Burst Write

X

Burst Read

CR

CW

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and

that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and

assumes ADSP is tied high and ADV is tied low.

Rev: 1.00b 12/2002

12/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

Simplified State Diagram with G

X

Deselect

W

R

W

R

X

W

R

X

First Write

First Read

CR

CW

CR

W

R

W

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.00b 12/2002

13/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

Absolute Maximum Ratings

(All voltages reference to V )

SS

Symbol

Description

Value

Unit

V

Voltage on V Pins

–0.5 to 4.6

DD

V

Voltage in V

Pins

DDQ

–0.5 to 4.6

V

DDQ

V

–0.5 to V

+0.5 (≤ 4.6 V max.)

DDQ

Voltage on I/O Pins

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

V

I/O

V

–0.5 to V +0.5 (≤ 4.6 V max.)

V

IN

DD

I

+/–20

mA

W

IN

I

OUT

P

1.5

D

o

T

–55 to 125

C

STG

o

T

Temperature Under Bias

C

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Rev: 1.00b 12/2002

14/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

Power Supply Voltage Ranges

Parameter

Symbol

Min.

3.0

Typ.

3.3

Max.

3.6

Unit

Notes

V

3.3 V Supply Voltage

2.5 V Supply Voltage

V

DD3

V

2.3

2.5

2.7

DD2

3.3 V V

2.5 V V

I/O Supply Voltage

V

3.0

3.3

3.6

DDQ

DDQ3

V

2.3

2.5

2.7

DDQ2

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

V

Range Logic Levels

Parameter

DDQ3

Symbol

Min.

2.0

Typ.

—

Max.

Unit

Notes

V

Input High Voltage

V

+ 0.3

DD

V

1

DD

IH

V

Input Low Voltage

V

–0.3

2.0

—

0.8

+ 0.3

1

DD

IL

V

I/O Input High Voltage

I/O Input Low Voltage

V

—

1,3

DDQ

IHQ

DDQ

V

–0.3

—

0.8

DDQ

ILQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3. V_IHQ(max) is voltage on V_DDQpins plus 0.3 V.

V

Range Logic Levels

Parameter

DDQ2

Symbol

Min.

Typ.

—

Max.

Unit

Notes

V

Input High Voltage

V

0.6*V

V

+ 0.3

DD

V

1

DD

IH

DD

V

Input Low Voltage

V

0.3*V

DD

–0.3

—

1

DD

IL

V

I/O Input High Voltage

I/O Input Low Voltage

V

0.6*V

V

+ 0.3

DDQ

—

1,3

DDQ

IHQ

DD

V

0.3*V

DD

–0.3

—

DDQ

ILQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3. V_IHQ(max) is voltage on V_DDQpins plus 0.3 V.

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Recommended Operating Temperatures

Parameter

Symbol

Min.

0

Typ.

25

Max.

70

Unit

°C

Notes

T

Ambient Temperature (Commercial Range Versions)

2

A

T

Ambient Temperature (Industrial Range Versions)

Note:

–40

25

85

°C

A

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKC

V

+ 2.0 V

50%

DD

V

SS

50%

V

DD

V

– 2.0 V

SS

20% tKC

V

IL

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 2.5 V)

A

DD

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

pF

C

V

= 0 V

Input Capacitance

4

6

5

7

IN

C

V

OUT

= 0 V

Input/Output Capacitance

pF

I/O

Note: These parameters are sample tested.

Package Thermal Characteristics

Rating

Junction to Ambient (at 200 lfm)

Junction to Case (TOP)

Notes:

Layer Board

Symbol

Max

40

Unit

Notes

1,2

R

single

four

—

°C/W

ΘJA

ΘJC

24

1,2

9

3

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-

ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

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AC Test Conditions

Parameter

Conditions

V

– 0.2 V

Input high level

Input low level

DD

0.2 V

1 V/ns

/2

Input slew rate

V

Input reference level

DD

V

/2

Output reference level

Output load

DDQ

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

Output Load 1

DQ

*

50Ω

30pF

V

DDQ/2

* Distributed Test Jig Capacitance

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I

V = 0 to V

IN DD

–1 uA

1 uA

IL

V

≥ V ≥ V

IN

–1 uA

1 uA

100 uA

DD

IH

I

ZZ and PE Input Current

FT, SCD, ZQ Input Current

IN1

IN2

0 V ≤ V ≤ V

IN

V

≥ V ≥ V

IN

–100 uA

–1 uA

1 uA

DD

IL

0 V ≤ V ≤ V

IN

I

Output Disable, V

= 0 to V

DD

Output Leakage Current

Output High Voltage

Output Low Voltage

–1 uA

1.7 V

2.4 V

—

1 uA

—

OL

OUT

DDQ

V

I

= –8 mA, V

= 2.375 V

= 3.135 V

OH2

OH3

OH

—

V

I

= 8 mA

OL

0.4 V

OL

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AC Electrical Characteristics

-250

-225

-200

-166

-150

-133

Parameter

Symbol

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Clock Cycle Time

Clock to Output Valid

Clock to Output Invalid

Clock to Output in Low-Z

Setup time

tKC

tKQ

4.0

—

2.5

—

5.5

—

4.4

—

2.7

—

6.0

—

5.0

—

3.0

—

6.5

—

6.0

—

3.4

—

7.0

—

6.7

—

3.8

—

7.5

—

7.5

—

1.5

0.5

8.5

—

3.0

1.5

0.5

1.7

2

—

4.0

—

8.5

—

ns

tKQX

1.5

1.2

0.2

5.5

—

3.0

1.5

0.5

1.3

1.5

1.3

0.3

6.0

—

3.0

1.5

0.5

1.3

1.5

1.4

0.4

6.5

—

3.0

1.5

0.5

1.3

1.5

0.5

7.0

—

3.0

1.5

0.5

1.3

1.5

0.5

7.5

—

3.0

1.5

0.5

1.5

1.7

Pipeline

1

tLZ

tS

tH

Hold time

Clock Cycle Time

Clock to Output Valid

Clock to Output Invalid

Clock to Output in Low-Z

Setup time

tKC

tKQ

tKQX

Flow

Through

1

tLZ

tS

tH

Hold time

Clock HIGH Time

Clock LOW Time

tKH

tKL

Clock to Output in

High-Z

1

1.5

2.5

1.5

2.7

1.5

3.0

1.5

3.0 1.5 3.0 1.5 3.0

ns

tHZ

G to Output Valid

G to output in Low-Z

G to output in High-Z

ZZ setup time

tOE

—

0

2.5

—

2.5

—

0

2.7

—

2.7

—

0

3.2

—

3.0

—

0

3.5

—

3.0

—

0

3.8

—

3.0

—

0

4.0

—

3.0

—

ns

1

tOLZ

tOHZ

1

—

5

—

5

—

5

—

5

—

5

—

5

2

tZZS

tZZH

2

ZZ hold time

1

ZZ recovery

tZZR

20

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

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Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of

SB

Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

SB

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

CK

tH

tS

tKC

tKL

tKH

ADSP

ADSC

ZZ

tZZH

tZZS

tZZR

Snooze

Application Tips

Single and Dual Cycle Deselect

SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with

the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually

assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste

bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at

bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output

DD

drivers are powered by V

.

DDQ

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

DD

SS

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JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TCK

Test Clock

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

TMS

TDI

Test Mode Select

Test Data In

In controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in

Out response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

TDO

Test Data Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and

0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising

edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI

and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

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JTAG TAP Block Diagram

0

Bypass Register

2

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1 0

·

· · ·

Boundary Scan Register

n

2 1 0

· · · · · · · · ·

TMS

TCK

Test Access Port (TAP) Controller

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

Die

Revision

Code

GSI Technology

JEDEC Vendor

ID Code

I/O

Not Used

Configuration

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

0

1

x72

x36

x32

x18

x16

X

0

1

0

1

0

1

0

1

0

0 1 1 0 1 1 0 0 1

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

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When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

1

Run Test Idle

Select DR

Select IR

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when

the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices

in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-

tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan

Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the

Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it

is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although

allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be

stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be

paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-

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DR state then places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The

EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST

command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when

the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the

sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in

parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the

Boundary Scan Register location with which each output pin is associated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID

register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any

time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-

ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction

EXTEST

IDCODE

Code

000

001

Description

Notes

1

1, 2

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z

010

011

TDO.

1

Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

GSI private instruction.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

100

101

110

111

1

GSI

RFU

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

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JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

2.0

Max.

Unit Notes

V

+0.3

DD3

3.3 V Test Port Input High Voltage

3.3 V Test Port Input Low Voltage

2.5 V Test Port Input High Voltage

2.5 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

V

1

IHJ3

V

–0.3

0.8

+0.3

ILJ3

V

0.6 * V

V

1

IHJ2

DD2

V

0.3 * V

1

–0.3

–300

–1

V

1

ILJ2

DD2

I

uA

V

2

INHJ

I

100

1

3

INLJ

I

–1

4

OLJ

V

Test Port Output High Voltage

1.7

—

5, 6

5, 7

5, 8

5, 9

OHJ

V

Test Port Output Low Voltage

—

0.4

V

OLJ

V

– 100 mV

DDQ

Test Port Output CMOS High

—

V

OHJC

V

Test Port Output CMOS Low

—

100 mV

V

OLJC

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < V

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

2.

V

≤ V ≤ V

ILJ

IN

DDn

3. 0 V ≤ V ≤ V

IN

ILJn

4. Output Disable, V

= 0 to V

DDn

OUT

5. The TDO output driver is served by the V

supply.

DDQ

6.

7.

8.

9.

I

= –4 mA

OHJ

= + 4 mA

OLJ

= –100 uA

= +100 uA

OHJC

JTAG Port AC Test Conditions

Parameter

Conditions

JTAG Port AC Test Load

V

– 0.2 V

Input high level

Input low level

DQ

DD

0.2 V

1 V/ns

*

50Ω

Input slew rate

30pF

V

/2

Input reference level

DDQ

V

/2

DDQ

/2

Output reference level

DDQ

* Distributed Test Jig Capacitance

Notes:

1. Include scope and jig capacitance.

2. Test conditions as as shown unless otherwise noted.

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JTAG Port Timing Diagram

tTKL

tTS

tTKH

tTKC

TCK

tTH

TMS

TDI

TDO

tTKQ

JTAG Port AC Electrical Characteristics

Parameter

TCK Cycle Time

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

50

—

Max

—

Unit

ns

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

20

—

20

10

—

ns

tTH

—

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications

Engineering Department at: apps@gsitechnology.com.

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Package Dimensions—165-Bump FPBGA (Package D)

A1 CORNER

TOP VIEW

BOTTOM VIEW

A1 CORNER

M

Ø0.10

C

Ø0.25 C A B

Ø0.40~0.50 (165x)

1

2 3 4 5 6 7 8 9 10 11

11 10 9 8

7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

I

A

B

C

D

E

F

G

H

I

J

K

L

K

L

M

N

P

R

M

N

P

R

A

1.0

10.0

13±0.07

1.0

B

0.20(4x)

SEATING PLANE

C

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Package Dimensions—119-Pin PBGA

Pin 1

A

Corner

7 6 5 4 3 2 1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

H

D

B

J

S

K

L

M

N

P

R

T

U

R

Bottom View

Top View

Package Dimensions—119-Pin PBGA

Symbol

Description

Width

Min. Nom. Max

13.9 14.0 14.1

21.9 22.0 22.1

A

B

Length

C

Package Height (including ball) 1.73 1.86 1.99

D

Ball Size

0.60 0.75 0.90

0.50 0.60 0.70

E

Ball Height

F

Package Height (excluding balls) 1.16 1.26 1.36

G

Width between Balls

Package Height above board

Width of package between balls

Length of package between balls

Variance of Ball Height

1.27

K

0.65 0.70 0.75

R

7.62

20.32

0.15

S

T

Unit: mm

Side View

Rev: 1.00b 12/2002

30/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

Ordering Information for GSI Synchronous Burst RAMs

2

Speed

3

1

Org

Type

Package

Status

T

Part Number

A

(MHz/ns)

512K x 18

256K x 36

512K x 18

256K x 36

512K x 18

Notes:

GS88218BB-250

GS88218BB-225

GS88218BB-200

GS88218BB-166

GS88218BB-150

GS88218BB-133

GS88236BB-250

GS88236BB-225

GS88236BB-200

GS88236BB-166

GS88236BB-150

GS88236BB-133

GS88218BB-250I

GS88218BB-225I

GS88218BB-200I

GS88218BB-166I

GS88218BB-150I

GS88218BB-133I

GS88236BB-250I

GS88236BB-225I

GS88236BB-200I

GS88236BB-166I

GS88236BB-150I

GS88236BB-133I

GS88218BD-250

GS88218BD-225

GS88218BD-200

GS88218BD-166

GS88218BD-150

GS88218BD-133

Pipeline/Flow Through

119 BGA

165 BGA

250/5.5

225/6

C

I

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

I

200/6.5

166/7

I

150/7.5

133/8.5

250/5.5

225/6

I

200/6.5

166/7

I

150/7.5

133/8.5

250/5.5

225/6

I

C

200/6.5

166/7

150/7.5

133/8.5

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88236B-100IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

Rev: 1.00b 12/2002

31/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

2

Speed

3

1

Org

Type

Package

Status

T

Part Number

A

(MHz/ns)

256K x 36

512K x 18

256K x 36

Notes:

GS88236BD-250

GS88236BD-225

GS88236BD-200

GS88236BD-166

GS88236BD-150

GS88236BD-133

GS88218BD-250I

GS88218BD-225I

GS88218BD-200I

GS88218BD-166I

GS88218BD-150I

GS88218BD-133I

GS88236BD-250I

GS88236BD-225I

GS88236BD-200I

GS88236BD-166I

GS88236BD-150I

GS88236BD-133I

Pipeline/Flow Through

165 BGA

250/5.5

225/6

C

I

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

I

200/6.5

166/7

I

150/7.5

133/8.5

250/5.5

225/6

I

200/6.5

166/7

I

150/7.5

133/8.5

I

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88236B-100IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

Rev: 1.00b 12/2002

32/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218/36BB/D-250/225/200/166/150/133

9Mb Sync SRAM Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Format or Content

Page;Revisions;Reason

• Creation of new datasheet

88218B_r1

Rev: 1.00b 12/2002

33/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS88236BB-166T
厂家：	GSI TECHNOLOGY
描述：	Cache SRAM, 256KX36, 7ns, CMOS, PBGA119, PLASTIC, BGA-119 静态存储器
文件：	总33页 (文件大小：1082K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS88236BB-166T [GSI]

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