GS882V37BGD-360I [GSI]
SRAM;型号: | GS882V37BGD-360I |
厂家: | GSI TECHNOLOGY |
描述: | SRAM 静态存储器 |
文件: | 总27页 (文件大小:1134K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
GS882V37BB/D-360/333/300
360 MHz–300 MHz
119- & 165-Bump BGA
Commercial Temp
Industrial Temp
256K x 36
9Mb SCD/DCD Sync Burst SRAM
1.8 V V
DD
1.8 V I/O
SCD and DCD Pipelined Reads
The GS882V37BB/D is a SCD (Single Cycle Deselect) and DCD
Features
• Single/Dual Cycle Deselect selectable
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-bump and 165-bump BGA packages
• Pb-Free 119-bump and 165-bump BGA packages available
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Functional Description
Applications
The GS882V37BB/D is a 9,437,184-bit high performance
FLXDrive™
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Controls
Low power (Sleep mode) is attained through the assertion (High)
Addresses, data I/Os, chip enable (E1), address burst control
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Core and Interface Voltages
The GS882V37BB/D operates on a 1.8 V power supply. All inputs
are 1.8 V compatible. Separate output power (VDDQ) pins are used
to decouple output noise from the internal circuits and are 1.8 V
compatible.
Parameter Synopsis
-360
-333
-300
Unit
Pipeline
3-1-1-1
t
1.8
2.8
2.0
3.0
2.2
3.3
ns
ns
KQ
tCycle
1.8 V
Curr (x36)
475
435
395
mA
Rev: 1.03 3/2005
1/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
GS882V37B Pad Out—119-Bump BGA—Top View (Package B)
1
2
A
3
4
ADSP
ADSC
VDD
ZQ
5
6
A
7
VDDQ
NC
A
A
VDDQ
NC
A
B
C
D
E
F
NC
A
A
A
NC
A
A
A
A
NC
DQC
DQC
VDDQ
DQC
DQC
VDDQ
DQD
DQD
VDDQ
DQD3
DQD
NC
DQPC
DQC
DQC
DQC
DQC
VDD
DQD
DQD
DQD
DQD
DQPD
A
VSS
VSS
VSS
BC
VSS
VSS
VSS
BB
DQPB
DQB
DQB
DQB
DQB
VDD
DQA
DQA
DQA
DQA
DQPA
A
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
DQA
PE
E1
G
ADV
GW
VDD
CK
G
H
J
VSS
NC
VSS
BD
VSS
NC
VSS
BA
K
L
SCD
BW
A1
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
M
N
P
R
T
A0
VDDQ
DNU
/
VDD
NC
NC
A
A
NC
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
U
Rev: 1.03 3/2005
2/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
165 Bump BGA—x36 Common I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
A
11
A
B
C
D
E
F
NC
A
E1
BC
BB
E3
BW
ADSC
ADV
NC
A
B
C
D
E
F
NC
A
E2
BD
BA
CK
GW
G
ADSP
A
NC
DQB
DQB
DQB
DQB
DQB
ZZ
DQC
DQC
DQC
DQC
DQC
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
DQC
DQC
DQC
DQC
MCL
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQB
DQB
DQB
DQB
ZQ
G
H
G
H
V
/
NC
NC
DDQ
NC
J
K
L
DQD
DQD
DQD
DQD
DQD
NC
DQD
DQD
DQD
DQD
SCD
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQA
DQA
DQA
DQA
NC
DQA
DQA
DQA
DQA
DQA
A17
A
J
K
L
DDQ
DDQ
DDQ
DDQ
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
M
N
P
R
M
N
P
R
V
NC
TDI
NC
A1
A0
NC
V
SS
DDQ
SS
DDQ
A
A
A
TDO
TCK
A
A
A
A
LBO
NC
A
TMS
A
A
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03 3/2005
3/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
GS882V37 BGA Pin Description
Symbol
A0, A1
A
Type
Description
I
I
Address field LSBs and Address Counter Preset Inputs
Address Inputs
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA, BB, BC, BD
I
—
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
NC
NC
No Connect
CK
Clock Input Signal; active high
BW
I
Byte Write—Writes all enabled bytes; active low
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
GW
I
E1
I
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active l0w
Address Strobe (Processor, Cache Controller); active low
Sleep mode control; active high
ADSC, ADSP
I
ZZ
FT
I
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
9th Bit Enable; active low (119-bump BGA only)
LBO
PE
I
I
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
ZQ
I
I
I
Scan Test Mode Select
Scan Test Data In
TMS
TDI
O
I
Scan Test Data Out
TDO
TCK
MCL
SCD
Scan Test Clock
—
—
I
Must Connect Low
Single Cycle Deselect/Dual Cyle Deselect Mode Control
Core power supply
V
DD
V
I
I/O and Core Ground
SS
V
I
Output driver power supply
DDQ
Rev: 1.03 3/2005
4/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
GS882V37B Block Diagram
Register
A0–An
D
Q
A0
A0
A1
D0
D1
Q0
A1
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
36
36
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E2
E3
D
Q
Register
D
Q
G
Power Down
Control
DQx1–DQx9
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.03 3/2005
5/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
Mode Pin Functions
Mode Name
Pin
Name
State
Function
L
Linear Burst
Interleaved Burst
Active
Burst Order Control
Power Down Control
LBO
H
L or NC
ZZ
Standby, I = I
H
DD SB
L
Dual Cycle Deselect
Single Cycle Deselect
Single/Dual Cycle Deselect Control
FLXDrive Output Impedance Control
SCD
ZQ
H or NC
L
High Drive (Low Impedance)
Low Drive (High Impedance)
H or NC
Activate DQPx I/Os (x18/x36
mode)
L
9th Bit Enable
PE
Deactivate DQPx I/Os (x16/x32
mode)
H or NC
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.03 3/2005
6/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
Byte Write Truth Table
Function
Read
GW
BW
H
L
BA
X
BB
X
BC
X
BD
X
Notes
1
H
H
H
H
H
H
H
L
Read
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
Write all bytes
L
2, 3
2, 3
2, 3
2, 3
2, 3
L
H
H
H
L
L
H
H
L
L
H
L
L
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Rev: 1.03 3/2005
7/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
Synchronous Truth Table
Operation
State
3
4
Diagram
Address Used
E1
ADSP ADSC
ADV
W
DQ
5
Key
Deselect Cycle, Power Down
Read Cycle, Begin Burst
None
External
External
External
Next
X
R
H
L
X
L
L
X
L
X
X
X
X
L
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
Q
Q
D
Q
Q
D
D
Q
Q
D
D
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
R
L
L
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
Notes:
1. X = Don’t Care, H = High, L = Low
2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding
3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.03 3/2005
8/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.03 3/2005
9/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.03 3/2005
10/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
Absolute Maximum Ratings
(All voltages reference to V )
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 3.6
DD
DD
V
Voltage in V
Pins
DDQ
–0.5 to 3.6
V
DDQ
V
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 3.6
V
CK
V
–0.5 to V
+0.5 (≤ 3.6 V max.)
DDQ
V
I/O
V
–0.5 to V +0.5 (≤ 3.6 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Rev: 1.03 3/2005
11/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
Power Supply Voltage Ranges
Parameter
Symbol
Min.
1.6
Typ.
1.8
Max.
2.0
Unit
V
V
1.8 V Supply Voltage
DD
1.8 V V
I/O Supply Voltage
V
1.6
1.8
2.0
V
DDQ
DDQ
Note:
The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
I/O Logic Levels
Parameter
Symbol
Min.
Typ.
—
Max.
Unit
Notes
1, 2
V
Input High Voltage
Input Low Voltage
V
0.6*V
V
+ 0.3
DD
V
V
V
V
DD
IH
DD
V
V
0.3*V
DD
–0.3
—
1, 2
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
0.6*V
V
+ 0.3
DDQ
—
1, 2, 3
1, 2
DDQ
IHQ
DD
V
V
0.3*V
DD
–0.3
—
DDQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V, with a pulse width not to exceed 20% tKC.
DDn
3.
V
(max) is voltage on V
pins plus 0.3 V.
DDQ
IHQ
Recommended Operating Temperatures
Parameter
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
Note:
Symbol
Min.
0
Typ.
25
Max.
70
Unit
°C
T
A
T
–40
25
85
°C
A
The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Rev: 1.03 3/2005
12/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
50%
DD
V
SS
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 1.8 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V = 0 V
Input Capacitance
4
6
5
7
IN
IN
C
V
= 0 V
OUT
Input/Output Capacitance
pF
I/O
Note:
These parameters are sample tested.
AC Test Conditions
Parameter
Conditions
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
/2
Input slew rate
V
Input reference level
DD
V
/2
Output reference level
Output load
DDQ
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
*
50Ω
30pF
V
DDQ/2
* Distributed Test Jig Capacitance
Rev: 1.03 3/2005
13/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
–1 uA
1 uA
IL
IN
DD
V
≥ V ≥ V
IH
–1 uA
–1 uA
1 uA
100 uA
DD
IN
I
ZZ and PE Input Current
SCD and ZQ Input Current
IN1
0 V ≤ V ≤ V
IN
IH
V
≥ V ≥ V
IN
–100 uA
–1 uA
1 uA
1 uA
DD
IL
IL
I
IN2
0 V ≤ V ≤ V
IN
I
Output Disable, V
= 0 to V
= 1.6 V
Output Leakage Current
Output High Voltage
Output Low Voltage
–1 uA
1 uA
—
OL
OUT
DD
V
I
= –4 mA, V
V
– 0.4 V
DDQ
OH
OH
DDQ
V
I
= 4 mA, V = 1.6 V
—
0.4 V
OL
OL
DD
Operating Currents
-360
-333
-300
0
to
–40
to
0
to
–40
to
0
to
–40
to
Parameter
Test Conditions
Mode
Symbol
Unit
70°C
85°C
70°C
85°C
70°C
85°C
Device Selected;
All other inputs
≥V or ≤ V
Operating
Current
I
415
60
425
60
380
55
390
55
345
05
355
50
DD
(x36)
Pipeline
mA
I
IH
IL
DDQ
1.8 V
Output open
Standby
Current
ZZ ≥ V – 0.2 V
I
—
—
Pipeline
Pipeline
40
50
40
50
40
95
50
mA
mA
DD
SB
Device Deselected;
All other inputs
≥ V or ≤ V
Deselect
Current
I
105
115
100
105
100
DD
IH
IL
Notes:
1.
2. All parameters listed are worst case scenario.
I
and I
apply to any combination of V
and V
operation.
DDQ
DD
DDQ
DD3
Rev: 1.03 3/2005
14/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
AC Electrical Characteristics
-360
-333
-300
Parameter
Symbol
Unit
Min
2.8
—
1.0
1.0
1.0
0
Max
—
1.8
—
—
—
—
1.8
1.8
—
—
Min
3.0
—
1.0
1.0
1.0
0
Max
—
2.0
—
—
—
—
2.0
2.0
—
—
Min
3.3
—
Max
—
2.2
—
—
—
—
2.2
2.2
—
—
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKC
tKQ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
1.0
1.0
1.1
0.1
—
1
tLZ
Pipeline
tS
tH
Hold time
G to Output Valid
G to output in High-Z
Clock HIGH Time
Clock LOW Time
tOE
—
—
1.2
1.4
—
—
1.3
1.5
1
—
tOHZ
tKH
tKL
1.3
1.5
Clock to Output in
High-Z
1
1.0
1.8
1.0
2.0
1.0
2.2
ns
tHZ
1
G to output in Low-Z
ZZ setup time
ZZ hold time
0
5
—
—
—
—
0
5
—
—
—
—
0
5
—
—
—
—
ns
ns
ns
ns
tOLZ
2
tZZS
2
1
1
1
tZZH
ZZ recovery
tZZR
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.03 3/2005
15/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
Pipeline Mode Timing (+1)
Begin
Read A Cont
Cont
Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont
Deselect
tKC
tKH tKL
CK
ADSP
tS
tS
ADSC initiated read
tH
ADSC
ADV
tS
tH
tH
A
B
C
A0–An
GW
tS
tS
tH
tH
BW
tS
Ba–Bd
E1
tS
tS
tS
Deselected with E1
tH
E2 and E3 only sampled with ADSC
tH
tH
E2
E3
G
tS
tKQ
tLZ
tKQX
tHZ
tOE
tOHZ
Q(A)
tH
D(B)
Q(C)
Q(C+1)
Q(C+2) Q(C+3)
DQa–DQd
Rev: 1.03 3/2005
16/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
Setup
Hold
ADSP
ADSC
tZZR
tZZS
tZZH
ZZ
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DDQ
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
Rev: 1.03 3/2005
17/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Rev: 1.03 3/2005
18/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
JTAG TAP Block Diagram
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1 0
·
· · ·
Boundary Scan Register
n
2 1 0
· · · · · · · · ·
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
ID Code
I/O
Not Used
Configuration
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
x36 0 1 1 0 1 1 0 0 1
0
1
1
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.03 3/2005
19/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
1
1
Exit2 DR
Exit2 IR
0
0
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
Rev: 1.03 3/2005
20/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all
logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still
determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then
the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on
the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is
selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a
pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s
output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
Notes
1
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
SAMPLE-Z
RFU
010
011
1
1
SAMPLE/PRELOAD
GSI
100
101
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
GSI private instruction.
1
1
Do not use this instruction; Reserved for Future Use.
RFU
110
111
1
1
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.03 3/2005
21/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
V
0.6 * V
V
+0.3
DD
1.8 V Test Port Input High Voltage
1.8 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
V
V
1
1
IHJ
DD
V
0.3 * V
1
–0.3
–300
–1
ILJ
DD
I
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
1.7
—
5, 6
5, 7
5, 8
5, 9
OHJ
V
—
0.4
—
V
OLJ
V
V
– 100 mV
DDQ
Test Port Output CMOS High
V
OHJC
V
Test Port Output CMOS Low
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V
+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
ILJn
3. 0 V ≤ V ≤ V
IN
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V
supply.
DDQ
6.
7.
8.
9.
I
I
I
I
= –4 mA
OHJ
= + 4 mA
OLJ
= –100 uA
= +100 uA
OHJC
OHJC
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
V
– 0.20
Input high level
Input low level
DQ
DD
0.2 V
1 V/ns
*
50Ω
Input slew rate
30pF
V
/2
Input reference level
DDQ
DDQ
V
/2
DDQ
V
/2
Output reference level
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
Rev: 1.03 3/2005
22/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
JTAG Port Timing Diagram
tTKL
tTS
tTKH
tTKC
TCK
tTH
TMS
TDI
TDO
tTKQ
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
Max
—
Unit
ns
TCK Cycle Time
50
—
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
20
—
ns
20
20
10
10
ns
—
ns
—
ns
TDI & TMS Hold Time
tTH
—
ns
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
Rev: 1.03 3/2005
23/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
TOP VIEW
BOTTOM VIEW
A1
A1
S
Ø0.10
C
S
S
S
Ø0.30 C A
B
Ø0.60~0.90 (119x)
1
2
3
4
5
6
7
7
6
5
4 3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
M
N
P
R
T
U
K
L
M
N
P
R
T
U
B
1.27
7.62
14±0.10
A
0.20(4x)
SEATING PLANE
C
Rev: 1.03 3/2005
24/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
Package Dimensions—165-Bump FPBGA (Package D; Variation 1)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.50 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
1.0
13±0.07
B
0.20(4x)
SEATING PLANE
C
Rev: 1.03 3/2005
25/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
(MHz)
3
1
Org
Type
Package
Status
T
Part Number
A
256K x 36
256K x 36
256K x 36
GS882V37BB-360
GS882V37BB-333
GS882V37BB-300
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
119 BGA (var. 2)
119 BGA (var. 2)
360
333
300
360
333
300
360
333
300
360
333
300
360
333
300
360
333
300
360
333
300
360
333
300
C
C
C
I
119 BGA (var. 2)
256K x 36 GS882V37BB-360I
256K x 36 GS882V37BB-333I
256K x 36 GS882V37BB-300I
119 BGA (var. 2)
119 BGA (var. 2)
I
119 BGA (var. 2)
I
GS882V37BD-360
GS882V37BD-333
GS882V37BD-300
165 BGA (var. 1)
C
C
C
I
165 BGA (var. 1)
165 BGA (var. 1)
GS882V37BD-360I
GS882V37BD-333I
GS882V37BD-300I
256K x 36 GS882V37BGB-360
256K x 36 GS882V37BGB-333
256K x 36 GS882V37BGB-300
256K x 36 GS882V37BGB-360I
256K x 36 GS882V37BGB-333I
256K x 36 GS882V37BGB-300I
GS882V37BGD-360
GS882V37BGD-333
GS882V37BGD-300
GS882V37BGD-360I
GS882V37BGD-333I
165 BGA (var. 1)
165 BGA (var. 1)
I
165 BGA (var. 1)
I
Pb-Free 119 BGA (var. 2)
Pb-Free 119 BGA (var. 2)
Pb-Free 119 BGA (var. 2)
Pb-Free 119 BGA (var. 2)
Pb-Free 119 BGA (var. 2)
Pb-Free 119 BGA (var. 2)
Pb-Free 165 BGA (var. 1)
Pb-Free 165 BGA (var. 1)
Pb-Free 165 BGA (var. 1)
Pb-Free 165 BGA (var. 1)
Pb-Free 165 BGA (var. 1)
Pb-Free 165 BGA (var. 1)
C
C
C
I
I
I
C
C
C
I
I
GS882V37BGD-300I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS882V37BB-300IB.
2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
3. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.03 3/2005
26/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882V37BB/D-360/333/300
9Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
• Added 360 MHz
• Removed all speed bins below 300 MHz
• Updated format
882V37B_r1
882V37B_r1;
882V37B_r1_01
Format/Content
• Updated mechanical drawing and added variation number to
ordering information
882V37B_r1_01;
882V37B_r1_02
Content
Content
• Added 165 BGA
• Added Pb-Free information
882V37B_r1_02;
882V37B_r1_03
Rev: 1.03 3/2005
27/27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
相关型号:
©2020 ICPDF网 联系我们和版权申明