GS882Z36B-11IT [GSI]
ZBT SRAM, 256KX36, 11ns, CMOS, PBGA119, PLASTIC, BGA-119;
| 型号： | GS882Z36B-11IT |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | ZBT SRAM, 256KX36, 11ns, CMOS, PBGA119, PLASTIC, BGA-119 静态存储器 内存集成电路 |
| 文件： | 总34页 (文件大小：802K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS882Z18/36B-11/100/80/66
119-Bump BGA
Commercial Temp
Industrial Temp
100 MHz–66 MHz
8Mb Pipelined and Flow Through
3.3 V V
DD
Synchronous NBT SRAMs
2.5 V and 3.3 V V
DDQ
Features
Functional Description
• 512K x 18 and 256K x 36 configurations
• User-configurable Pipelined and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
• Read-Write-Read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• ZQ mode pin for user selectable high/low output drive
strength.
• x16/x32 mode with on-chip parity encoding and error
detection
• Pin-compatible with 2M, 4M and 16M devices
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
The GS882Z818/36B is an 8Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
• 3 chip enable signals for easy depth expansion
• Clock Control, registered, address, data, and control
• ZZ Pin for automatic power-down
The GS882Z818/36B may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
• JEDEC-standard 119-Bump BGA package
-11
-100
-80
-66
tCycle
tKQ
IDD
10 ns
4.5 ns
10 ns
4.5 ns
12.5 ns
4.8 ns
15 ns
5 ns
Pipeline
3-1-1-1
210 mA 210 mA 190 mA 170 mA
tKQ
tCycle
IDD
11 ns
15 ns
12 ns
15 ns
14 ns
15 ns
18 ns
20 ns
Flow Through
2-1-1-1
150 mA 150 mA 130 mA 130 mA
The GS882Z818/36B is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 119-bump BGA package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
A
R
B
C
R
D
E
R
F
Read/Write
W
W
W
Flow Through
Data I/O
QA
DB
QC
DD
QE
Pipelined
Data I/O
QA
DB
QC
DD
QE
Rev: 1.15 6/2001
1/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary.
GS882Z18/36B-11/100/80/66
GS882Z36 Pad Out
119-Bump BGA—Top View
1
2
3
4
5
6
7
A
VDDQ
NC
A6
A7
NC
ADV
VDD
ZQ
E1
A8
A9
VDDQ
NC
B
C
D
E
F
E2
A4
A15
A14
VSS
VSS
VSS
BB
E3
NC
A5
A3
A16
NC
DQC4
DQC3
VDDQ
DQC2
DQC1
VDDQ
DQD1
DQD2
VDDQ
DQD3
DQD4
NC
DQPC9
DQC8
DQC7
DQC6
DQC5
VDD
VSS
VSS
VSS
BC
DQPB9
DQB8
DQB7
DQB6
DQB5
VDD
DQB4
DQB3
VDDQ
DQB2
DQB1
VDDQ
DQA1
DQA2
VDDQ
DQA3
DQA4
PE
G
G
H
J
A17
W
VSS
DP
VSS
QE
VSS
BA
VDD
CK
NC
CKE
A1
K
L
DQD5
DQD6
DQD7
DQD8
DQPD9
A2
VSS
BD
DQA5
DQA6
DQA7
DQA8
DQPA9
A13
M
N
P
R
T
VSS
VSS
VSS
LBO
A10
TDI
VSS
VSS
VSS
FT
A0
VDD
A11
TCK
NC
NC
A12
TDO
NC
ZZ
U
VDDQ
TMS
NC
VDDQ
Rev: 1.15 6/2001
2/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
GS882Z18 Pad Out
119-Bump BGA—Top View
1
2
3
4
NC
ADV
VDD
ZQ
E1
5
6
7
A
VDDQ
NC
A6
A7
A8
A9
VDDQ
NC
B
C
D
E
F
E2
A4
A15
A14
VSS
VSS
VSS
NC
VSS
QE
VSS
BA
E3
NC
A5
A3
A16
NC
DQB1
NC
NC
VSS
VSS
VSS
BB
DQA9
NC
NC
DQB2
NC
DQA8
VDDQ
DQA6
NC
VDDQ
NC
G
DQA7
NC
DQB3
NC
VDD
DQB5
NC
A17
W
G
H
J
DQB4
VDDQ
NC
VSS
DP
DQA5
VDD
NC
VDD
CK
NC
CKE
A1
VDDQ
DQA4
NC
VSS
NC
VSS
VSS
VSS
LBO
A11
K
L
DQB6
VDDQ
DQB8
NC
DQA3
NC
DQB7
NC
VSS
VSS
VSS
FT
VDDQ
NC
M
N
P
R
T
DQA2
NC
DQB9
A2
A0
DQA1
PE
NC
VDD
NC
A13
NC
A10
A12
A18
ZZ
VDDQ
NC
VDDQ
U
Rev: 1.15 6/2001
3/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
GS882Z18/36 BGA Pin Description
Pin Location
Symbol
Type
Description
P4, N4
A0, A1
I
Address field LSBs and Address Counter Preset Inputs
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, G4, R2, R6, T3, T5
An
I
Address Inputs
T4
An
NC
An
I
—
I
Address Inputs (x36 Version)
No Connect (x36 Version)
Address Inputs (x18 Version)
T2, T6
T2, T6
K7, L7, N7, P7, K6, L6, M6, N6, P6 DQA1–DQPA9
H7, G7, E7, D7, H6, G6, F6, E6, D6 DQB1–DQPB9
H1, G1, E1, D1, H2, G2, F2, E2, D2 DQC1–DQPC9
K1, L1, N1, P1, K2, L2, M2, N2, P2 DQD1–DQPD9
I/O
Data Input and Output pins (x36 Version)
L5, G5, G3, L3
BA, BB, BC, BD
I
I/O
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ( x36 Version)
Data Input and Output pins (x18 Version)
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
DQA1–DQA9
DQB1–DQB9
L5, G3
BA, BB
Byte Write Enable for DQA, DQB Data I/Os; active low ( x18 Version)
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,
G5, L3, T4
NC
—
No Connect (x18 Version)
K4
M4
H4
E4
B2
B6
F4
B4
T7
R5
R3
R7
J3
CK
CKE
W
I
I
Clock Input Signal; active high
Clock Input Buffer Enable; active low
Write Enable—Writes all enabled bytes; active low
Chip Enable; active low
I
E1
I
E2
I
Chip Enable; active high
E3
I
Chip Enable; active low
G
I
Output Enable; active low
ADV
ZZ
I
Burst address counter advance enable; active high
Sleep Mode control; active high
I
FT
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
Data Parity Mode Input; 1 = Even, 0 = Odd
Parity Error Out; Open Drain Output
LBO
PE
DP
QE
I
I
I
J5
O
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
D4
ZQ
NC
I
B1, C1, R1, T1, L4, B7, C7, U6
—
No Connect
Rev: 1.15 6/2001
4/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
GS882Z18/36 BGA Pin Description
Pin Location
Symbol
TMS
Type
Description
U2
I
I
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
U3
TDI
U5
U4
TDO
O
I
TCK
VDD
J2, C4, J4, R4, J6
I
Core power supply
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
VSS
I
I
I/O and Core Ground
A1, F1, J1, M1, U1, A7, F7, J7, M7,
U7
VDDQ
Output driver power supply
BPR2000.002.14
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
W
H
L
BA
X
L
BB
X
H
L
BC
X
H
H
L
BD
X
H
H
H
L
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the Write input is sampled low at the rising edge of clock.
Rev: 1.15 6/2001
5/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A Write
Cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.15 6/2001
6/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Synchronous Truth Table
Operation
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Continue
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
Write Abort, Continue Burst
Clock Edge Ignore, Stall
Sleep Mode
Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes
D
D
D
D
R
B
None
None
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
None
X
H
X
H
X
H
X
H
X
X
X
H
L
1
External
Next
L-H
L-H
Q
Q
X
L
X
L
H
L
L
1,10
2
R
B
External
Next
H
H
X
X
X
X
X
X
L-H High-Z
X
L
X
L
H
L
L-H High-Z 1,2,10
W
B
External
Next
L-H
L-H
D
D
3
X
L
X
L
H
L
X
L
L
1,3,10
2,3
W
B
None
H
H
X
X
L-H High-Z
Next
X
X
X
X
X
X
H
X
X
X
X
X
L-H High-Z 1,2,3,10
Current
None
L-H
X
-
4
High-Z
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect
cycle is executed first
2. Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is
sampled low but no Byte Write pins are active, so no Write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write
cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.15 6/2001
7/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Pipeline and Flow Through Read-Write Control State Diagram
D
B
Deselect
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
W
R
Burst Read
Burst Write
B
B
D
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B and D represent input command
codes, as indicated in the Synchronous Truth Table.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram
Rev: 1.15 6/2001
8/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
B
R
W
B
Intermediate
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
Intermediate
D
Intermediate
W
R
High Z
B
D
Intermediate
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+2)
Intermediate State (N+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Intermediate
State
Current State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.15 6/2001
9/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Flow Through Mode Data I/O State Diagram
R
W
B
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
D
W
R
High Z
B
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 1.15 6/2001
10/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
FLXDrive™
The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
L
Burst Order Control
LBO
H or NC
L
Output Register Control
Power Down Control
FT
ZZ
DP
PE
ZQ
H or NC
L or NC
Active
Standby, IDD = ISB
H
L
Check for Odd Parity
Check for Even Parity
ByteSafe Data Parity Control
Parity Enable
H or NC
L or NC
Activate 9th I/Os (x18/36 Mode)
Deactivate 9th I/Os (x16/32 Mode)
High Drive (Low Impedance)
Low Drive (High Impedance)
H
L
FLXDrive Output Impedance Control
H
Note:
There are pull-up devices on the LBO, ZQ, DP and FT pins and a pull down device on the PE and ZZ pins, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above table.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or
x32) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.
Rev: 1.15 6/2001
11/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
00 01 10 11
01 00 11 10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
10
11
11
10
00
01
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
CK
tZZR
ZZ
Sleep
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found
on bump 5R. Not all vendors offer this option, however most mark bump 5R as VDD or VDDQ on pipelined parts and VSS on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
ByteSafe™ Parity Functions
In x32/x16 mode this RAM features a parity encoding and checking function. It is assumed that the RAM is being used in x32/x16
mode because there is no source for parity bits from the system. So, in x32/x16 mode, the device generates parity and stores it
along with written data. It is also assumed that there is no facility for parity checking, so the RAM checks read parity and reports an
error in the cycle following parity check. In x32/x16 mode the device does not drive the 9th data output, even though the internal
ByteSafe parity encoding has been activated. A ByteSafe SRAM, used in x32/x16 mode, allows parity protection of data in
applications where parity encoding or checking are not otherwise available. As in any system that checks read parity, reads of un-
Rev: 1.15 6/2001
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© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
written memory locations may well produce parity errors. Initialization of the memory should be implemented to avoid this issue.
In x18/x36 mode this SRAM includes a write data parity check that checks the validity of data coming into the RAM on write
cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write
data errors are reported one clock cycle later. (See Write Parity Error Output Timing Diagram.) The Data Parity Mode (DP) pin
must be tied high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the
RAM as data. Validity is best established at the data’s destination. The Parity Error Output is an open drain output and drives low
to indicate a parity error. Multiple Parity Error Output pins may share a common pull-up resistor.
x32 Mode (PE = 1) Read Parity Error Output Timing Diagram
CK
Address A
Address B
D Out A
Address C
D Out B
Address D
D Out C
Address E
D Out D
Address F
D Out E
DQ
tKQ
tLZ
tHZ
tKQX
QE
DQ
Err A
Err C
D Out A
D Out B
D Out C
D Out D
tKQ
tLZ
tHZ
tKQX
QE
Err A
Err C
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© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
x18/x36 Mode (PE = 0) Write Parity Error Output Timing Diagram
CK
DQ
D In A
D In B
D In C
D In D
D In E
tKQ
tLZ
tHZ
tKQX
QE
DQ
Err A
Err C
D In A
D In B
D In C
D In D
D In E
tKQ
tLZ
tHZ
tKQX
QE
Err A
Err C
BPR 1999.05.18
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© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Absolute Maximum Ratings
(All voltages reference to VSS
)
Symbol
VDD
Description
Value
Unit
Voltage on VDD Pins
–0.5 to 4.6
–0.5 to VDD
V
V
VDDQ
VCK
Voltage in VDDQ Pins
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 6
V
VI/O
–0.5 to VDDQ +0.5 (£ 4.6 V max.)
–0.5 to VDD +0.5 (£ 4.6 V max.)
V
VIN
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
IIN
+/–20
+/–20
mA
mA
W
IOUT
PD
1.5
oC
oC
TSTG
–55 to 125
–55 to 125
TBIAS
Temperature Under Bias
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended
period of time, may affect reliability of this component.
Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
VDD
VDDQ
VIH
Min.
3.135
2.375
1.7
Typ.
3.3
2.5
—
Max.
3.6
Unit
V
Notes
VDD
I/O Supply Voltage
V
1
2
2
3
3
VDD +0.3
Input High Voltage
V
VIL
Input Low Voltage
–0.3
0
—
0.8
70
85
V
TA
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
25
°C
°C
TA
–40
25
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V £ VDDQ £ 2.375 V
(i.e., 2.5 V I/O) and 3.6 V £ VDDQ £ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC.
Rev: 1.15 6/2001
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© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 2.0 V
50%
VSS
50%
VDD
VSS – 2.0 V
20% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Input Capacitance
Symbol
Test conditions
Typ.
Max.
Unit
pF
CIN
VIN = 0 V
4
6
5
7
CI/O
VOUT = 0 V
Input/Output Capacitance
pF
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
RQJA
Max
40
Unit
Notes
1,2
single
four
—
°C/W
°C/W
°C/W
RQJA
24
1,2
RQJC
9
3
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.15 6/2001
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© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
AC Test Conditions
Parameter
Input high level
Input low level
Conditions
2.3 V
0.2 V
Input slew rate
1 V/ns
Input reference level
Output reference level
Output load
1.25 V
1.25 V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225W
225W
DQ
30pF*
50W
5pF*
VT = 1.25 V
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
VDD ³ VIN ³ VIH
0 V £ VIN £ VIH
–1 uA
–1 uA
1 uA
300 uA
IINZZ
IINM
IOL
ZZ Input Current
VDD ³ VIN ³ VIL
0 V £ VIN £ VIL
–300 uA
–1 uA
1 uA
1 uA
Mode Pin Input Current
Output Leakage Current
Output Disable,
VOUT = 0 to VDD
–1 uA
1 uA
VOH
VOH
VOL
IOH = –8 mA, VDDQ = 2.375 V
IOH = –8 mA, VDDQ = 3.135 V
IOL = 8 mA
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
—
—
—
0.4 V
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© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Operating Currents
-11
-100
-80
-66
Parameter
Test Conditions
Symbol
Unit
0 to -40 to
0 to -40 to
0 to -40 to
0 to -40 to
70°C +85°C 70°C +85°C 70°C +85°C 70°C +85°C
IDD
Pipeline
Device Selected;
All other inputs
³ VIH or £ VIL
210
150
30
220
160
40
210
150
30
220
160
40
190
130
30
200
140
40
170
130
30
180
140
40
mA
mA
mA
mA
mA
mA
Operating
Current
IDD
Output open
Flow-through
ISB
Pipeline
Standby
Current
ZZ ³ VDD – 0.2 V
ISB
30
40
30
40
30
40
30
40
Flow-through
IDD
Pipeline
80
90
80
90
70
80
65
75
Device Deselected;
All other inputs
³ VIH or £ VIL
Deselect
Current
IDD
65
75
65
75
55
65
55
65
Flow-through
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© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
AC Electrical Characteristics
-11
-100
-80
-66
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max
Clock Cycle Time
tKC
tKQ
10
—
—
4.5
—
10
—
—
4.5
—
12.5
—
—
4.8
—
15
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock to Output Valid
Pipeline
Clock to Output Invalid
tKQX
1.5
1.5
15.0
—
1.5
1.5
15.0
—
1.5
1.5
15.0
—
1.5
1.5
20
—
—
—
—
18.0
—
—
—
—
5
tLZ1
tKC
Clock to Output in Low-Z
Clock Cycle Time
—
—
—
—
—
—
Clock to Output Valid
Flow-
tKQ
11.0
—
12.0
—
14.0
—
through
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKQX
3.0
3.0
1.7
2
3.0
3.0
2
3.0
3.0
2
3.0
3.0
2.3
2.5
1.5
—
tLZ1
tKH
tKL
—
—
—
—
—
—
Clock LOW Time
—
2.2
1.5
—
—
2.2
1.5
—
—
tHZ1
tOE
Clock to Output in High-Z
G to Output Valid
1.5
—
4.0
4.0
—
4.5
4.5
—
4.8
4.8
—
5
tOLZ1
G to output in Low-Z
0
0
0
0
—
tOHZ1
tS
G to output in High-Z
Setup time
—
1.5
0.5
5
4.0
—
—
—
—
2.0
0.5
5
4.5
—
—
—
—
—
—
5
4.8
2.0
0.5
—
—
—
—
5
5
ns
ns
ns
ns
2.0
0.5
—
Hold time
tH
tZZS2
ZZ setup time
tZZH2
tZZR
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup
and hold times as specified above.
Rev: 1.15 6/2001
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© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Pipeline Mode Read/Write Cycle Timing
1
2
3
4
5
6
7
8
9
10
CK
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
tKH tKL tKC
CKE
E*
ADV
W
Bn
tH
A1
A2
A3
A4
A5
A6
A7
A0–An
tKQ
tKHQZ
tGLQV
tKQHZ
tKQLZ
D
Q
(A4+1)
DQA–DQD
D(A2)
Q(A3)
Q(A4)
Q(A6)
D(A1)
D(A5)
(A2+1)
tKQX
tH
tS
tOEHZ
tOELZ
G
Write
D(A5)
Write
D(A2) Write
D(A2+1)
BURST Read
Q(A3)
Read
Q(A4) Read
Q(A4+1)
BURST
Read
Q(A6)
DESELECT
Write
D(A1)
Write
D(A7)
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
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© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Pipeline Mode No-Op, Stall and Deselect Timing
2
8
4
3
5
6
10
7
9
1
CK
tH
tH
tH
tS
tS
tS
CKE
E*
ADV
tS
tH
W
Bn
A0–An
DQ
A1
A2
A3
A4
A5
tKHQZ
Q(A2)
D(A1)
Q(A3)
D(A4)
Q(A5)
tKQHZ
NOP
Read
Q(A2)
STALL Read
Q(A3)
Write
D(A4)
STALL
Read
Q(A5)
CONTINUE
DESELECT
Write
D(A1)
DESELECT
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
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© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Flow Through Mode Read/Write Cycle Timing
4
3
5
6
8
10
7
9
1
2
CK
CKE
E*
tH
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
tKH tKL
tKC
ADV
W
Bn
A7
A0–An
A1
A2
A3
A4
A5
A6
tKQ
tKHQZ
tGLQV
tKQHZ
tKQLZ
D
Q
DQ
D(A2)
Q(A3)
Q(A4)
Q(A6)
D(A1)
D(A5)
(A2+1)
(A4+1)
tOELZ
tKQX
tH
tS
tOEHZ
G
Write
D(A5)
Write
D(A2)
BURST Read
Read
Q(A4) Read
Q(A4+1)
BURST
Read
Q(A6)
DESELECT
Write
D(A1)
Write
D(A7)
COMMAND
Write
Q(A3)
D(A2+1)
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 1.15 6/2001
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© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Flow Through Mode No-Op, Stall and Deselect Timing
4
3
5
6
8
10
7
9
1
2
CK
tH
tS
tS
tS
CKE
E*
tH
tH
ADV
W
Bn
A1
A2
A3
A4
A5
A0–An
tKHQZ
Q(A2)
D(A1)
Q(A5)
Q(A3)
D(A4)
NOP
DQ
tKQHZ
Read
Q(A2)
STALL Read
Q(A3)
Write
D(A4)
STALL
Read
Q(A5)
DESELECT
CONTINUE
DESELECT
Write
D(A1)
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
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© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface
standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Some
functions have been modified or eliminated because they can slow the RAM. Nevertheless, the RAM supports 1149.1-1990 TAP
(Test Access Port) Controller architecture, and can be expected to function in a manner that does not conflict with the operation of
Standard 1149.1 compliant devices. The JTAG Port interfaces with conventional TTL / CMOS logic level signaling.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits. To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions
Pin
Pin Name I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the
falling edge of TCK.
TCK
Test Clock
In
Test Mode
Select
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state
machine. An undriven TMS input will produce the same result as a logic one input level.
TMS
TDI
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed
between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP
In Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to
Test Data In
the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input
level.
Output that is active depending on the state of the TAP state machine. Output changes in response to the
falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
TDO Test Data Out Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS
as TCK is strobed. Each of the TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and
push serial data out on the next falling edge of TCK. When a register is selected it is placed between the TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAMs JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 1.15 6/2001
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© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Boundary Scan Register
Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The
flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary
Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins
and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the
control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then
is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. Two TAP instructions can be used to
activate the Boundary Scan Register.
JTAG TAP Block Diagram
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1 0
·
· · ·
Boundary Scan Register
n
2 1 0
· · · · · · · · ·
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
ID Code
I/O
Not Used
Configuration
1
1
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
10 9 8 7 6 5 4 3 2 1
0
x36
x32
x18
x16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
1
1
1
1
Rev: 1.15 6/2001
25/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1-
compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor
all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This
device will not perform EXTEST, INTEST or the SAMPLE/PRELOAD command.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
Rev: 1.15 6/2001
26/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring con-
tents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm
the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data cap-
ture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O
ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the
TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-
DR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This
functionality is not Standard 1149.1-compliant.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in
the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, this device is not 1149.1-compliant. Neverthe-
less, this RAM’s TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the instruction regis-
ter the RAM responds just as it does in response to the BYPASS instruction described above.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-
ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 1.15 6/2001
27/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
This RAM does not implement 1149.1 EXTEST function. *Not 1149.1 Compliant *
1
1, 2
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.
SAMPLE-Z
010
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
011
1
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1 Compliant *
100
101
110
111
1
1
1
1
GSI
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol Min. Max. Unit Notes
VIHT
VDD +0.3
Test Port Input High Voltage
1.7
–0.3
–300
–1
V
V
1, 2
1, 2
3
VILT
Test Port Input Low Voltage
0.8
1
IINTH
IINTL
IOLT
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
uA
uA
uA
V
1
4
–1
1
5
VOHT
VOLT
2.4
—
—
0.4
6, 7
6, 8
V
Notes:
1. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
2. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20%
tTKC.
3. VDD ³ VIN ³ VIL
4. 0 V £ VIN £ VIL
5. Output Disable, VOUT = 0 to VDD
6. The TDO output driver is served by the VDD supply.
7. IOH = –4 mA
8. IOL = +4 mA
Rev: 1.15 6/2001
28/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
JTAG Port AC Test Conditions
Parameter
Input high level
Conditions
2.3 V
JTAG Port AC Test Load
DQ
Input low level
0.2 V
30pF*
Input slew rate
1 V/ns
50W
Input reference level
Output reference level
1.25 V
VT = 1.25 V
1.25 V
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
JTAG Port Timing Diagram
tTKL
tTKH
tTKC
TCK
tTS tTH
TMS
TDI
TDO
tTKQ
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
20
—
10
10
5
Max
Unit
ns
TCK Cycle Time
—
10
—
—
—
—
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
ns
ns
ns
ns
tTH
5
ns
Rev: 1.15 6/2001
29/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
GS882Z18/36B BGA Boundary Scan Register
Bump
Bump
x36 x18
6A
Bump
x36
x18
x36
x18
x36
x18
x36 x18
x36 x18
1
2
3
4
5
6
7
8
9
PE
PH = 0
A10
7R
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
A9
A8
60
61
62
63
64
65
DP
3J
n/a
5A
PH = 1
n/a
3T 2T
4T 3T
5T
A17
4G
DQD1
DQD2
DQD5
DQD6
DQB5
DQB6
DQB7
DQB8
2K
A11
NC = 0
ADV
G
4A
1L
A12
4B
2M
A13
6R
4F
1N
A14
5C
CKE
W
4M
x18 = DQB9
x16 = NA = 0
66
DQD3
1K 2P
A15
5B
4H
67
68
69
DQD4
DQD7
DQD8
NC = 1
NC = 1
NC = 1
2L
2N
1P
A16
6C
CK
4K
x36 = DQA9
x32 = NA = 0
PH = 0
PH = 1
CE3
BA
n/a
10
NC = 1
6P
n/a
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQA8
DQA4
DQA3
DQA7
DQA6
DQA5
DQA2
DQA1
NC = 1
NC = 1
NC = 1
NC = 1
DQA1
7N
6M
7L
x36 = DQD9
x32 = NA = 0
6B
70
NC = 1
2P 1K
5L
71
72
73
74
75
76
77
78
LBO
3R
2C
3B
3C
2R
4N
4P
BB
BC
BD
BB
5G 3G
3G 5G
3L
A5
A4
A3
A2
A1
A0
ZQ
6K
7P
6N
6L
NC = 1
NC = 1
DQA2
CE2
CE1
A7
2B
DQA3
4E
DQA4
7K
7T
5J
3A
ZZ
QE
A6
2A
4D
x36 =DQC9
x32 = NA = 0
BPR 1999.08.11
50
NC = 1
2D
DQB5
DQB1
DQB2
DQB6
DQA5
DQA6
DQA7
DQA8
6H
7G
6F
7E
51
52
53
54
55
56
57
58
59
DQC8
DQC4
DQC3
DQC7
DQC6
DQC5
DQC2
DQC1
NC = 1
NC = 1
NC = 1
NC = 1
DQB1
1E
2F
1G
2H
1D
2E
2G
1H
5R
x18 =DQA9
x16 = NA = 0
7H 6D
25
DQB3
26
27
28
DQB4
DQB7
NC = 1
NC = 1
NC = 1
6G
6E
7D
DQB2
DQB3
DQB8
DQB4
x36 = DQB9
x32 = NA = 0
6D 6T
29
A18
FT
Note:
1. The Boundary Scan Register contains a number of registers that are not connected to any pin. They default to the value shown at reset.
2. Registers are listed in exit order (i.e., Location 1 is the first out of the TDO pin).
3. NC = No Connect, NA = Not Active
Rev: 1.15 6/2001
30/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
FLXDrive Output Driver Characteristics
120.0
100.0
Pull Down Drivers
80.0
60.0
40.0
20.0
0.0
VDD
I Out
VOut
-20.0
-40.0
-60.0
VSS
Pull Up Drivers
-80.0
-100.0
-120.0
-140.0
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD HD
3.1V PU LD
3.3V PD HD
3.3V PU LD
3.1V PD HD
3.6V PU LD
3.6V PD LD
3.1V PU HD
3.3V PD LD
3.3V PU HD
3.1V PD LD
3.6V PU HD
BPR 1999.05.18
Rev: 1.15 6/2001
31/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Package Dimensions—119-Bump PBGA
Pin 1
Corner
A
7 6 5 4 3 2
1
A
B
C
D
E
F
G
H
J
G
D
B
P
S
K
L
M
N
P
R
T
U
R
N
Bottom View
Top View
Package Dimensions—119-Bump PBGA
Symbol
Description
Width
Min Nom Max
13.8 14.0 14.2
21.8 22.0 22.2
A
B
Length
C
Package Height (including ball)
Ball Size
—
—
2.40
D
0.60 0.75 0.90
0.50 0.60 0.70
E
Ball Height
F
Package Height (excluding balls)
Width between Balls
Package Height above board
Cut-out Package Width
Foot Length
—
—
1.46 1.70
1.27
G
—
K
0.80 0.90 1.00
N
—
—
—
—
—
12.00
19.50
7.62
—
—
—
—
—
P
R
Width of package between balls
Length of package between balls
Variance of Ball Height
S
T
20.32
0.15
Side View
Unit: mm
BPR 1999.05.18
Rev: 1.15 6/2001
32/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Ordering Information—GSI NBT Synchronous SRAM
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
512K x 18
512K x 18
512K x 18
512K x 18
256K x 36
256K x 36
256K x 36
256K x 36
512K x 18
512K x 18
512K x 18
512K x 18
256K x 36
256K x 36
256K x 36
256K x 36
Notes:
GS882Z18B-11
GS882Z18B-100
GS882Z18B-80
GS882Z18B-66
GS882Z36B-11
GS882Z36B-100
GS882Z36B-80
GS882Z36B-66
GS882Z18B-11I
GS882Z18B-100I
GS882Z18B-80I
GS882Z18B-66I
GS882Z36B-11I
GS882Z36B-100I
GS882Z36B-80I
GS882Z36B-66I
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
ByteSafe NBT Pipeline/Flow Through
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
100/11
100/12
80/14
C
C
C
C
C
C
C
C
I
66/18
100/11
100/12
80/14
66/18
100/11
100/12
80/14
I
I
66/18
I
100/11
100/12
80/14
I
I
I
66/18
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS882Z36B-100IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some
of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.15 6/2001
33/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary.
GS882Z18/36B-11/100/80/66
Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Page /Revisions/Reason
New
• Last Page/Fixed “GSGS..” in Ordering Information
Note.Document/Changed format of all E’s from EN to EN.
• Timing Diagrams/Changed format. ex. A0 to A0.
• Flow Through Timing Diagrams/Upper case “T” in Flow
Through. thru to Through.
Format/Typos
Content
GS882Z818/36BRev1.04h 5/
1999;
• Pin outs/Block Diagrams -Updated format to small caps.
• Added Rev History.
1.05 9/1999
• Pin Outs/Numbered all data I/O’s.
• Boundary Scan/Ordered Data I/O pins correctly.
• Speed Bins on Page 1/Last column-changed 12ns to 15ns
and 15ns to 12ns.
• Improved Appearance of Timing Diagrams.
• Minor formatting changes.
GS882Z818/36B 1.05 9/
1999K/ 1.06 10/1999
Format
• Changed pin 4J to VDD in x 18 Pinout.
• Took out overbar on NC in PinoutNew GSI Logo.Placed pin
4A in the No Connect list in the pin description.
GS882Z818/36B 1.06 9/
1999K 1.07 1/2000L
Content
• Removed 166 and 150 MHz speed bins
• Used 100 MHz Pipeline numbers for 133 MHz
• Changed all 133 MHz references to 11 ns
• Updated format to comply with Technical Publications
standards
Rev.1.10; 882Z18_r1_11
Content/Format
• Updated Capitance table—removed Input row and changed
Output row to I/O
882Z18_r1_11;
882Z18_r1_12
Content
Content
Content
• Corrected typo on pinouts
882Z18_r1_12;
882Z18_r1_13
• Removed SCD/DCD reference from Mode Pin Functions table
on page 11
882Z18_r1_13;
882Z18_r1_14
• Added parity bit references to x36 pad out
• Updated order of data input and output pins in pin description
table
882Z18_r1_14;
882Z18_r1_15
Content
Rev: 1.15 6/2001
34/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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