GS88418GB-150I [GSI]
Cache SRAM, 512KX18, 9ns, CMOS, PBGA119, BGA-119;
| 型号： | GS88418GB-150I |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Cache SRAM, 512KX18, 9ns, CMOS, PBGA119, BGA-119 静态存储器 内存集成电路 |
| 文件： | 总25页 (文件大小：800K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS88418/36B-200/180/166/150/133
119-Bump BGA
Commercial Temp
Industrial Temp
200 MHz–133 MHz
512K x 18, 256K x 36
8Mb S/DCD Sync Burst SRAMs
3.3 V V
DD
3.3 V and 2.5 V I/O
(LBO) input. The Burst function need not be used. New
addresses can be loaded on every cycle with no degradation of
chip performance.
Features
• FT pin for user-configurable flow through or pipelined
operation
• Single/Dual Cycle Deselect Selectable
• ZQ mode pin for user-selectable high/low output drive strength
• 3.3 V +10%/–5% core power supply
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode bump (Bump 5R). Holding the FT
mode pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
SCD and DCD Pipelined Reads
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• 119-bump BGA package
The GS88436B is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the
SCD mode input on Bump 4L.
-200 -180 -166 -150 -133 Unit
Pipeline tCycle
5.0
3.0
450
5. 5
3.2
410
6.0
3.5
380
6.7
3.8
350
7.5
4.0
340 mA
ns
ns
3-1-1-1
tKQ
IDD
Flow
Through
2-1-1-1
tKQ
tCycle
IDD
7.5
10
270
8
10
270
8.5
10
250
9.0
10
240
9.5
10
220 mA
ns
ns
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Functional Description
Applications
The GS88418/36B is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart for details.
Sleep Mode
Controls
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Addresses, data I/Os, chip enables (E1, in x18 version, E1 and
E2 in x36 version), address burst control inputs (ADSP,
ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered
clock input (CK). Output enable (G) and power-down control
(ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order
Core and Interface Voltages
The GS884B operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- and 2.5 V-compatible. Separate output
power (VDDQ) pins are used to decouple output noise from the
internal circuit.
Rev: 1.05 10/2001
1/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
GS88436 Pad Out
119-Bump BGA—Top View
1
2
3
4
ADSP
ADSC
VDD
ZQ
5
6
7
A
B
C
D
E
F
VDDQ
NC
A6
A7
A8
A9
VDDQ
NC
E2
A4
A15
A14
VSS
VSS
VSS
BB
A17
NC
A5
A3
A16
NC
DQC4
DQC3
VDDQ
DQC2
DQC1
VDDQ
DQD1
DQD2
VDDQ
DQD3
DQD4
NC
DQPC9
DQC8
DQC7
DQC6
DQC5
VDD
VSS
VSS
VSS
BC
DQPB9
DQB8
DQB7
DQB6
DQB5
VDD
DQB4
DQB3
VDDQ
DQB2
DQB1
VDDQ
DQA1
DQA2
VDDQ
DQA3
DQA4
NC
E1
G
ADV
GW
VDD
CK
G
H
J
VSS
NC
VSS
BD
VSS
NC
VSS
BA
DQD5
DQD6
DQD7
DQD8
DQPD9
A2
DQA5
DQA6
DQA7
DQA8
DQPA9
A13
K
L
SCD
BW
A1
VSS
VSS
VSS
LBO
A10
NC
VSS
VSS
VSS
FT
M
N
P
R
T
A0
VDD
A11
NC
NC
NC
A12
NC
NC
ZZ
VDDQ
NC
NC
VDDQ
U
Rev: 1.05 10/2001
2/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
GS88418 Pad Out
119-Bump BGA—Top View
1
2
3
4
ADSP
ADSC
VDD
ZQ
5
6
7
VDDQ
NC
A6
A7
A8
A9
VDDQ
NC
A
B
C
D
E
F
NC
A4
A15
A14
VSS
VSS
VSS
NC
VSS
NC
VSS
BA
A17
NC
A5
A3
A16
NC
DQB1
NC
NC
VSS
VSS
VSS
BB
DQA9
NC
NC
DQB2
NC
E1
DQA8
VDDQ
DQA6
NC
VDDQ
NC
G
DQA7
NC
DQB3
NC
VDD
DQB5
NC
ADV
GW
VDD
CK
G
H
J
DQB4
VDDQ
NC
VSS
NC
VSS
NC
VSS
VSS
VSS
LBO
A11
NC
DQA5
VDD
NC
VDDQ
DQA4
NC
K
L
DQB6
VDDQ
DQB8
NC
SCD
BW
A1
DQA3
NC
M
N
P
R
T
DQB7
NC
VSS
VSS
VSS
FT
VDDQ
NC
DQA2
NC
DQB9
A2
A0
DQA1
NC
NC
VDD
NC
A13
NC
A10
A12
NC
A18
ZZ
U
VDDQ
NC
NC
NC
VDDQ
Rev: 1.05 10/2001
3/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
GS88418/36 BGA Pin Description
Pin Location
Symbol
Type
Description
P4, N4
A0, A1
I
Address field LSBs and Address Counter Preset Inputs
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, G4, R2, R6, T3, T5
An
I
Address Inputs
T4
An
NC
An
I
—
I
Address Inputs (x36 Version)
No Connect (x36 Version)
Address Inputs (x18 Version)
T2, T6
T2, T6
K7, L7, N7, P7, K6, L6, M6, N6, P6 DQA1–DQPA9
H7, G7, E7, D7, H6, G6, F6, E6, D6 DQB1–DQPB9
H1, G1, E1, D1, H2, G2, F2, E2, D2 DQC1–DQPC9
K1, L1, N1, P1, K2, L2, M2, N2, P2 DQD1–DQPD9
I/O
Data Input and Output pins (x36 Version)
L5, G5, G3, L3
BA, BB, BC, BD
I
I/O
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ( x36 Version)
Data Input and Output pins (x18 Version)
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
DQA1–DQA9
DQB1–DQB9
L5, G3
BA, BB
Byte Write Enable for DQA, DQB Data I/Os; active low ( x18 Version)
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,
G5, L3, T4
NC
—
No Connect (x18 Version)
K4
E4
B2
F4
T7
R5
R3
L4
CK
E1
I
I
I
I
I
I
I
I
Clock Input Signal; active high
Chip Enable; active low
E2
Chip Enable; active high
G
Output Enable; active low
ZZ
Sleep Mode control; active high
FT
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control
LBO
SCD
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
D4
ZQ
I
B1, C1, R1, T1, L4, B7, C7, U6, R7,
J3,J5, U2, U3, U4, U5
NC
VDD
VSS
—
No Connect
J2, C4, J4, R4, J6
I
I
Core power supply
I/O and Core Ground
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
A1, F1, J1, M1, U1, A7, F7, J7, M7,
U7
VDDQ
I
Output driver power supply
BPR2000.002.14
Rev: 1.05 10/2001
4/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
GS88418/36 Block Diagram
Register
A0–An
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
18
18
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
D
Q
Register
D
Q
FT
G
DCD=0
SCD=1
Power Down
Control
DQx0–DQx9
ZZ
Note: Only x18 version shown for simplicity.
Rev: 1.05 10/2001
5/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Mode Pin Functions
Mode Name
Pin Name
State
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
L
Burst Order Control
LBO
H or NC
L
Output Register Control
FT
ZZ
H or NC
L or NC
Active
Power Down Control
Standby, IDD = ISB
H
L
Dual Cycle Deselect
Single Cycle Deselect
Single/Dual Cycle Deselect Control
FLXDrive Output Impedance Control
SCD
ZQ
H or NC
L
High Drive (Low Impedance)
Low Drive (High Impedance)
H
Note:
There are pull-up devices on the LBO, ZQ, SCD, and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and
the chip will operate in the default states as specified in the above table.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or
x32) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.05 10/2001
6/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
B
A
B
B
B
C
B
D
Notes
1
X
H
L
X
H
H
L
X
H
H
H
L
X
H
H
H
H
L
Read
H
1
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
Write all bytes
Notes:
L
X
X
X
X
X
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x36 version.
Rev: 1.05 10/2001
7/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Synchronous Truth Table
Operation
State
2
Address
Used
E2
3
4
Diagram
E1
ADSP ADSC ADV
W
DQ
(x36only)
5
Key
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
None
None
X
X
H
L
X
F
F
T
T
T
X
X
X
X
X
X
X
X
X
L
L
X
L
X
X
X
X
X
X
L
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
High-Z
None
X
L
L
H
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
R
L
L
X
H
X
H
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
1. X = Don’t Care, H = High, L = Low.
2. For x36 Version, E = T (True) if E2 = 1; E = F (False) if E2 = 0.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.05 10/2001
8/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CR
CW
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1 and E2) and Write (BA, BB, BC, BD, BW, and GW) control
inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.05 10/2001
9/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CR
CW
CW
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.05 10/2001
10/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS
)
Symbol
VDD
Description
Value
Unit
Voltage on VDD Pins
–0.5 to 4.6
–0.5 to VDD
V
V
V
VDDQ
VCK
Voltage in VDDQ Pins
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 6
VI/O
–0.5 to VDDQ +0.5 (£ 4.6 V max.)
V
V
VIN
–0.5 to VDD +0.5 (£ 4.6 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
IIN
+/–20
+/–20
mA
mA
W
IOUT
PD
1.5
oC
oC
TSTG
–55 to 125
–55 to 125
TBIAS
Temperature Under Bias
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended
period of time, may affect reliability of this component.
Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
VDD
VDDQ
VIH
Min.
3.135
2.375
1.7
Typ.
3.3
2.5
—
Max.
3.6
Unit
V
Notes
VDD
I/O Supply Voltage
V
1
2
2
3
3
VDD +0.3
Input High Voltage
V
VIL
Input Low Voltage
–0.3
0
—
0.8
70
85
V
TA
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
25
°C
°C
TA
–40
25
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V £ VDDQ £ 2.375 V
(i.e., 2.5 V I/O) and 3.6 V £ VDDQ £ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC.
Rev: 1.05 10/2001
11/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 2.0 V
50%
VSS
50%
VDD
VSS – 2.0 V
20% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Input Capacitance
Symbol
Test conditions
Typ.
Max.
Unit
pF
CIN
VIN = 0 V
4
6
5
7
CI/O
VOUT = 0 V
Input/Output Capacitance
pF
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
RQJA
Max
40
Unit
Notes
1,2
single
four
—
°C/W
°C/W
°C/W
RQJA
24
1,2
RQJC
9
3
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient.
Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.05 10/2001
12/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
AC Test Conditions
Parameter
Input high level
Input low level
Conditions
2.3 V
0.2 V
Input slew rate
1 V/ns
Input reference level
Output reference level
Output load
1.25 V
1.25 V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225W
225W
DQ
30pF*
50W
5pF*
VT = 1.25 V
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
VDD ³ VIN ³ VIH
0 V £ VIN £ VIH
–1 uA
–1 uA
1 uA
300 uA
IINZZ
IINM
IOL
ZZ Input Current
VDD ³ VIN ³ VIL
0 V £ VIN £ VIL
–300 uA
–1 uA
1 uA
1 uA
Mode Pin Input Current
Output Leakage Current
Output Disable,
VOUT = 0 to VDD
–1 uA
1 uA
VOH
VOH
VOL
IOH = –4 mA, VDDQ = 2.375 V
IOH = –4 mA, VDDQ = 3.135 V
IOL = 4 mA
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
—
—
—
0.4 V
Rev: 1.05 10/2001
13/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Operating Currents
-200
-180
-166
-150
-133
0
to
-40
to
0
to
-40
to
0
to
-40
to
0
to
-40
to
0
to
-40
to
Parameter
Test Conditions
Symbol
Unit
70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C
Device Selected;
All other inputs
³ VIH or £ VIL
IDD
Pipeline
450
270
470
290
410
270
430
290
380
250
400
270
350
240
370
250
340
220
360
240
mA
mA
Operating
Current
IDD
Output open
Flow Through
ISB
Pipeline
40
40
60
60
40
40
60
60
40
40
60
60
40
40
60
60
40
40
90
70
60
60
mA
mA
mA
mA
Standby
Current
ZZ ³ VDD – 0.2 V
ISB
Flow Through
IDD
Pipeline
120
90
140
110
110
80
130
100
100
80
120
100
100
70
120
90
110
90
Device Deselected;
All other inputs
³ VIH or £ VIL
Deselect
Current
IDD
Flow Through
Rev: 1.05 10/2001
14/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
AC Electrical Characteristics
-200
Max
-180
Max
-166
Max
-150
Max
-133
Max
Parameter
Symbol
Unit
Min
5.0
—
Min
5.5
—
Min
6.0
—
Min
6.7
—
Min
7.5
—
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock Cycle Time
tKC
tKQ
—
3.0
—
—
3.2
—
—
3.5
—
—
3.8
—
—
4.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pipeline
tKQX
1.5
1.5
10.0
—
1.5
1.5
10.0
—
1.5
1.5
10.0
—
1.5
1.5
10.0
—
1.5
1.5
10.0
—
tLZ1
tKC
—
—
—
—
—
—
—
—
—
—
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKQ
7.5
—
8.0
—
8.5
—
9.0
—
9.5
—
Flow
Through
tKQX
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
tLZ1
tKH
tKL
—
—
—
—
—
—
—
—
—
—
Clock LOW Time
—
—
—
—
—
tHZ1
tOE
Clock to Output in High-Z
G to Output Valid
3.0
3.2
—
3.2
3.2
—
3.5
3.5
—
3.8
3.8
—
4.0
4.0
—
tOLZ1
G to output in Low-Z
0
0
0
0
0
tOHZ1
tS
G to output in High-Z
Setup time
—
1.5
0.5
5
3.0
—
—
—
—
1.5
0.5
5
3.2
—
—
—
—
1.5
0.5
5
3.5
—
—
—
—
1.5
0.5
5
3.8
—
—
—
—
1.5
0.5
5
4.0
—
—
—
ns
ns
ns
ns
Hold time
tH
tZZS2
ZZ setup time
tZZH2
tZZR
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.05 10/2001
15/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Write Cycle Timing
Single Write
tS tH
Burst Write
Deselected
Write
CK
ADSP is blocked by E inactive
tKC
tKL
tKH
ADSP
tH
tH
tS
tS
ADSC initiated write
ADSC
ADV
ADV must be inactive for ADSP Write
tH
tS
WR2
WR3
WR1
A0–An
tS tH
GW
BW
tH
tS
tS
tH
WR3
WR1
WR2
BA–BD
tS
tS
tH
tH
E1 masks ADSP
E1
Deselected with E2
E2*
E2 only sampled with ADSP or ADSC
G
tS
tH
Write specified byte for 2A and all bytes for 2B, 2C& 2D
D2C D2D D3A
Hi-Z
D1A
DQA–DQD
D2A
D2B
* Only in 88436B
Rev: 1.05 10/2001
16/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tS
tKH
tS
tH
ADSP is blocked by E inactive
tKC
ADSP
ADSC
ADV
tH
ADSC initiated read
tH
tS
Suspend Burst
Suspend Burst
tS
tH
RD1
RD2
RD3
A0–An
GW
tS
tS
tH
tH
BW
BA–BD
tH
tH
tS
tS
E1 masks ADSP
E1
E2 only sampled with ADSP or ADSC
Deselected with E2
E2*
tOHZ
tOE
G
tKQX
tKQX
tOLZ
Q2B
Q2c
Q3A
Q1A
Q2A
Q2D
DQA–DQD
Hi-Z
tLZ
tHZ
tKQ
Rev: 1.05 10/2001
17/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Flow Through Read-Write Cycle Timing
Single Write
Burst Read
Single Read
CK
tS tH
tKC
ADSP is blocked by E inactive
ADSC initiated read
tKH tKL
ADSP
tS tH
ADSC
ADV
tS tH
tS
tH
RD2
RD1
WR1
A0–An
GW
tS tH
tH
tS
BW
tS
tH
WR1
BA–BD
tS
tS
tH
E1 masks ADSP
E
1
tH
E2 only sampled with ADSP and ADSC
E2*
tOHZ
tOE
G
tS
tH
tKQ
Hi-Z
DQA–DQD
Q1A
D1A
Q2A
Q2A
Q2B
Q2c
Q2D
Burst wrap around to it’s initial state
* Only in 88436B
Rev: 1.05 10/2001
18/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Pipelined SCD Read Cycle Timing
Single Read
Burst Read
tKC
CK
tKL
tKH
tH
tH
tS
ADSP is blocked by E inactive
ADSP
ADSC
tS
ADSC initiated read
tS tH
Suspend Burst
ADV
tH
tS
RD2
RD3
RD1
A0–An
tS
tS
tH
GW
BW
tH
BWA–BWD
tH
tS
E1 masks ADSP
E1
tS tH
E2 only sampled with ADSP or ADSC
Deselected with E2
E2*
tOE
G
tOHZ
tKQX
tKQX
Q3A
tOLZ
tLZ
Hi-Z
DQA–DQD
Q1A
Q2A
Q2B
Q2D
Q2c
tHZ
tKQ
* Only in 88436B
Rev: 1.05 10/2001
19/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Pipelined DCD Read-Write Cycle Timing
Single Write
Single Read
Burst Read
tKL
CK
ADSP
ADSC
tS
tH
tKH
tKC
ADSP is blocked by E1 inactive
tS tH
ADSC initiated read
tS
tH
tH
ADV
tS
tH
RD2
WR1
A0–An
RD1
tS
GW
BW
tS
tH
tH
tS
WR1
BA–BD
tS
tH
E1 masks ADSP
E1
tS tH
E2 only sampled with ADSP and ADSC
E2*
tOE
tOHZ
G
tS
tH
tKQ
Hi-Z
Q1A
D1a
Q2A
DQA–DQD
Q2B
Q2c
Q2D
* Only in 88436B
Rev: 1.05 10/2001
20/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Sleep Mode Timing Diagram
CK
tH
tS
tKC
tKL
tKH
ADSP
ADSC
ZZ
tZZH
tZZS
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 1.05 10/2001
21/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
FLXDrive Output Driver Characteristics
120.0
100.0
Pull Down Drivers
80.0
60.0
40.0
20.0
0.0
VDD
I Out
VOut
-20.0
-40.0
-60.0
VSS
Pull Up Drivers
-80.0
-100.0
-120.0
-140.0
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD HD
3.1V PU LD
3.3V PD HD
3.3V PU LD
3.1V PD HD
3.6V PU LD
3.6V PD LD
3.1V PU HD
3.3V PD LD
3.3V PU HD
3.1V PD LD
3.6V PU HD
Rev: 1.05 10/2001
22/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Package Dimensions—119-Pin BGA
Pin 1
Corner
A
7 6 5 4 3 2
1
A
B
C
D
E
F
G
H
J
G
D
B
P
S
K
L
M
N
P
R
T
U
R
N
Bottom View
Top View
Package Dimensions—119-Pin BGA
Symbol
Description
Width
Min. Nom. Max
13.8 14.0 14.2
21.8 22.0 22.2
A
B
Length
C
Package Height (including ball)
Ball Size
-
2.40
D
0.60 0.75 0.90
E
Ball Height
0.50 0.60 0.70
F
Package Height (excluding balls)
Width between Balls
Package Height above board
Cut-out Package Width
Foot Length
1.46 1.70
G
1.27
K
0.80 0.90 1.00
N
12.00
19.50
7.62
P
R
Width of package between balls
Length of package between balls
Variance of Ball Height
S
T
20.32
0.15
Side View
Unit: mm
Rev: 1.05 10/2001
23/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
512K x 36
512K x 36
256K x 36
256K x 36
256K x 36
Notes:
GS88418B-200
GS88418B-180
GS88418B-166
GS88418B-150
GS88418B-133
GS88436B-200
GS88436B-180
GS88436B-166
GS88436B-150
GS88436B-133
GS88418B-200I
GS88418B-180I
GS88418B-166I
GS88418B-150I
GS88418B-133I
GS88418B-200I
GS88418B-180I
GS88436B-166I
GS88436B-150I
GS88436B-133I
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
S/DCD Pipeline/Flow Through
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
200/7.5
180/8
C
C
C
C
C
C
C
C
C
C
I
166/8.5
150/9
133/9.5
200/7.5
180/8
166/8.5
150/9
133/9.5
200/7.5
180/8
Not Available
Not Available
I
166/8.5
150/9
I
I
133/9.5
200/7.5
180/8
I
I
I
166/8.5
150/9
I
I
133/9.5
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88418BT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.05 10/2001
24/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Page;Revisions;Reason
New
•
GS8841836B Rev 1.00
88418_r1; 88418_r1_01
First Release
Content
• Updated BGA pinout to meet JEDEC standards
• Updated format to comply with Technical Publications
standards
88418_r1_01; 88418_r1_02
88418_r1_02; 88418_r1_03
Format
• Updated Capitance table—removed Input row and changed
Output row to I/O
Content
• Updated speed bin table on page 1 (Added 150 MHz and 133
MHz)
• Updated pinouts on pages 2 & 3 (U2–U5 should all be NC)
• Removed PE, DP, and QE from Pin Description table on page
4; added R7, J3, J5, U2, U3, U4, U5 to NC row
• Added 150 MHz and 133 MHz to Operating Currents table on
page 14
• Added 150 MHz and 133 MHz to Electrical Characteristics
table on page 15
• Deleted BSR table on page 22
88418_r1_03; 88418_r1_04
88418_r1_04; 88418_r1_05
Content
Content
• Added references to 150 MHz and 133 MHz speed bins to
headers and ordering information table
Rev: 1.05 10/2001
25/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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