C3901 [HAMAMATSU]

Current output, high UV sensitivity, excellent linearity, low power consumption; 电流输出，高灵敏度的紫外线，优异的线性度，低功耗


型号：	C3901
厂家：	HAMAMATSU CORPORATION
描述：	Current output, high UV sensitivity, excellent linearity, low power consumption 电流输出，高灵敏度的紫外线，优异的线性度，低功耗
文件：	总6页 (文件大小：205K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

I M A G E S E N S O R

NMOS linear image sensor

S3901/S3904 series

Current output, high UV sensitivity, excellent linearity, low power consumption

NMOS linear image sensors are self-scanning photodiode arrays designed specifically as detectors for multichannel spectroscopy. The scanning

circuit is made up of N-channel MOS transistors, operates at low power consumption and is easy to handle. Each photodiode has a large active

area, high UV sensitivity yet very low noise, delivering a high S/N even at low light levels. NMOS linear image sensors also offer excellent output

linearity and wide dynamic range.

The photodiodes of S3901 series have a height of 2.5 mm and are arrayed in a row at a spacing of 50 µm. The photodiodes of S3904 series also

have a height of 2.5 mm but are arrayed at a spacing of 25 µm. The photodiodes are available in 3 different pixel quantities for each series: 128

(S3901-128Q), 256 (S3901-256Q, S3904-256Q), 512 (S3901-512Q, S3904-512Q) and 1024 (S3904-1024Q). Quartz glass is the standard window

material.

Features

Applications

Wide active area

Pixel pitch: 50 µm (S3901 series)

Multichannel spectrophotometry

Image readout system

25 µm (S3904 series)

Pixel height: 2.5 mm

High UV sensitivity with good stability

Low dark current and high saturation charge allow a long

integration time and a wide dynamic range at room temperature

Excellent output linearity and sensitivity spatial uniformity

Lower power consumption: 1 mW max.

Start pulse and clock pulses are CMOS logic compatible

ꢀ Equivalent circuit

ꢀ Active area structure

Start st

Degital shift register

(MOS shift register)

End of scan

Active video

Clock

Active

photodiode

Vss

Saturation

control gate

Saturation

control drain

Dummy video

Oxidation silicon

Dummy diode

KMPDC0020EA

N type silicon

P type silicon

S3901 series: a=50 µm, b=45 µm

S3904 series: a=25 µm, b=20 µm

KMPDA0059EA

ꢀ Absolute maximum ratings

Parameter

Symbol

Vφ

Topr

Tstg

Value

-40 to +65

-40 to +85

Unit

°C

Input pulse (φ1, φ2, φst) voltage

Power consumption*¹

Operating temperature*²

Storage temperature

*1: Vφ=5.0 V

°C

*2: No dew

NMOS linear image sensor S3901/S3904 series

Shape specifications

ꢀ

Parameter

S3901-128Q S3901-256Q S3901-512Q S3904-256Q S3904-512Q S3904-1024Q

Unit

Number of pixels

Package length

Number of pins

Window material*³

128

256

512

40.6

256

512

1024

40.6

31.75

Quartz

Weight

3.0

3.5

3.0

3.5

*3: Fiber optic plate is available (excluding the S3901-128Q, S3904-256Q).

Specifications (Ta=25 °C)

ꢀ

S3901 series

S3904 series

Parameter

Symbol

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.

Pixel pitch

Pixel height

2.5

µm

Spectral response range

(10% of peak)

200 to 1000

Peak sensitivity wavelength

600

0.2

180

0.6

600

0.1

180

0.3

mlx · s

λp

Photodiode dark current*⁴

Photodiode capacitance*⁴

Saturation exposure*⁴*⁵

Saturation output charge*⁴

Photo response non-uniformity*⁶

Cph

Esat

Qsat

PRNU

*4: Vb=2.0 V, Vφ=5.0 V

*5: 2856 K, tungsten lamp

*6: 50% of saturation, excluding the start pixel and last pixel

Electrical characteristics (Ta=25 °C)

ꢀ

S3901 series

S3904 series

Parameter

Symbol

Condition

Unit

Min.

4.5

1.5

Typ.

Vφ1

Max.

0.4

Min.

4.5

1.5

Typ.

Vφ1

Max.

0.4

High

Low

High

Low

Vφ1, Vφ2 (H)

Vφ1, Vφ2 (L)

Vφs (H)

Vφs (L)

Clock pulse (φ1, φ2)

voltage

Start pulse (φst) voltage

0.4

Video bias voltage*⁷

Vφ - 3.0 Vφ - 2.5

Saturation control gate voltage

Saturation control drain voltage

Vscg

Vscd

trφ1, trφ2

tfφ1, tfφ2

tpwφ1, tpwφ2

trφs, tfφs

tpwφs

φ φ

Clock pulse ( 1,

2) rise / fall tim e*⁸

200

Clock pulse (φ1, φ2) pulse width

Start pulse (φst) rise / fall time

Start pulse (φst) pulse width

Start pulse (φst) and clock pulse

200

tφov

(φ2) overlap

Clock pulse space

Data rate*⁹

X , X

trf - 20

0.1

trf - 20

0.1

kHz

2000

50% of

80 (-128 Q)

120 (-256 Q)

160 (-512 Q)

21 (-128 Q)

36 (-256 Q)

67 (-512 Q)

12 (-128 Q)

20 (-256 Q)

35 (-512 Q)

7 (-128 Q)

11 (-256 Q)

20 (-512 Q)

100 (-256 Q )

150 (-512 Q )

200 (-1024 Q )

27 (-256 Q )

50 (-512 Q )

100 (-1024 Q )

14 (-256 Q )

24 (-512 Q )

45 (-1024 Q )

10 (-256 Q )

16 (-512 Q )

30 (-1024 Q )

saturation

Video delay time

tvd

Clock pulse (φ1, φ2)

line capacitance

5 V bias

2 V bias

Cφ

Saturation control gate (Vscg)

line capacitance

Cscg

Video line capacitance

*7: Vφ is input pulse voltage (refer to

“ Video bias voltage m argin”).

ꢀ

*8: trf is the clock pulse rise or fall time. A clock pulse space of “rise time/fall time - 20 ” ns (nanoseconds) or more should be

input if the clock pulse rise or fall time is longer than 20 ns (refer to

*9: Vb=2.0 V, Vφ=5.0 V

“ Timing chart for driver circuit”).

ꢀ

*10: Measured with C7883 driver circuit.

NMOS linear image sensor S3901/S3904 series

ꢀ Dimensional outlines (unit: mm)

S3901-128Q, S3904-256Q

S3901-256Q, S3904-512Q

Active area

12.8 × 2.5

Active area

6.4 × 2.5

6.4 ± 0.3

3.2 ± 0.3

1 ch

31.75 ± 0.3

Chip surface

Direction of scan

0.51 ± 0.05

2.54 ± 0.13

0.25

0.51 ± 0.05

2.54 ± 0.13

0.25

25.4 ± 0.13

10.16 ± 0.25

25.4 ± 0.13

10.16 ± 0.25

*1: Distance from upper surface of quartz

window to chip surface

*2: Distance from chip surface

to bottom of package

*1: Distance from upper surface of quartz

window to chip surface

*2: Distance from chip surface

to bottom of package

*3: Window thickness

KMPDA0060ED

KMPDA0061ED

ꢀ Pin connection

S3901-512Q, S3904-1024Q

Active area

25.6 × 2.5

12.8 ± 0.3

1 ch

Vss

Vscg

40.6 ± 0.3

Vscd

Chip surface

Vss

Direction of scan

Active video

Dummy video

Vsub

End of scan

0.51 ± 0.05

0.25

Vss, Vsub and NC should be grounded.

KMPDC0056EA

2.54 ± 0.13

25.4 ± 0.13

10.16 ± 0.25

*1: Distance from upper surface of quartz

window to chip surface

*2: Distance from chip surface

to bottom of package

*3: Window thickness

KMPDA0062ED

NMOS linear image sensor S3901/S3904 series

Terminal

Input or output

Description

Pulses for operating the MOS shift register. The video data rate is

equal to the clock pulse frequency since the video output signal is

obtained synchronously with the rise of φ2 pulse.

Pulse for starting the MOS shift register operation. The time interval

between start pulses is equal to the signal accumulation time.

Connected to the anode of each photodiode. This should be

grounded.

Input

φ1, φ2

φst

(CMOS logic compatible)

Input

(CMOS logic compatible)

Vss

Vscg

Vscd

Input

Used for restricting blooming. This should be grounded.

Used for restricting blooming. This should be biased at a voltage

equal to the video bias voltage.

Video output signal. Connects to photodiode cathodes when the

address is on. A positive voltage should be applied to the video

line in order to use photodiodes with a reverse voltage. When the

amplitude of φ1 and φ2 is 5 V, a video bias voltage of 2 V is

recommended.

Active video

Output

This has the same structure as the active video, but is not

connected to photodiodes, so only spike noise is output. This

should be biased at a voltage equal to the active video or left as an

open-circuit when not needed.

Connected to the silicon substrate. This should be grounded.

This should be pulled up at 5 V by using a 10 kΩ resistor. This is a

negative going pulse that appears synchronously with the φ2

timing right after the last photodiode is addressed.

Should be grounded.

Dummy video

Output

Vsub

Output

(CMOS logic compatible)

End of scan

ꢀ Spectral response (typical example)

ꢀ Output charge vs. exposure

(Typ. Vb=2 V, V =5 V, light source: 2856 K)

(Ta=25 ˚C)

10²

0.3

0.2

0.1

Saturation

charge

10¹

S3901 series

10⁰

S3904 series

10^–1

Saturation exposure

10^–2

10^–3

10^–5

10^–4

10^–3

10^–2

10^–1

10⁰

1200

200

1000

400

800

600

Exposure (lx · s)

Wavelength (nm)

KMPDB0042EB

KMPDB0149EA

ꢀꢀConstruction of image sensor

The NMOS image sensor consists of a scanning circuit made

up of MOS transistors, a photodiode array, and a switching

transistor array that addresses each photodiode, all integrated

onto a monolithic silicon chip. “ꢀEquivalent circuit” shows

the circuit of a NMOS linear image sensor.

The MOS scanning circuit operates at low power consump-

tion and generates a scanning pulse train by using a start

pulse and 2-phase clock pulses in order to turn on each ad-

dress sequentially. Each address switch is comprised of an

NMOS transistor using the photodiode as the source, the

video line as the drain and the scanning pulse input section

as the gate.

photodiode, which are respectively connected to the active

video line and the dummy video line via a switching transis-

tor. Each of the active photodiodes is also connected to the

saturation control drain via the saturation control transistor,

so that the photodiode blooming can be suppressed by

grounding the saturation control gate. Applying a pulse sig-

nal to the saturation control gate triggers all reset. (See

“ꢀAuxiliary functions”.)

“ꢀActive area structure” shows the schematic diagram of the

photodiode active area. This active area has a PN junction

consisting of an N-type diffusion layer formed on a P-type

silicon substrate. A signal charge generated by light input

accumulates as a capacitive charge in this PN junction. The

N-type diffusion layer provides high UV sensitivity but low

dark current.

The photodiode array operates in charge integration mode

so that the output is proportional to the amount of light expo-

sure (light intensity × integration time).

Each cell consists of an active photodiode and a dummy

NMOS linear image sensor S3901/S3904 series

ꢀꢀDriver circuit

S3901/S3904 series do not require any DC voltage supply

for operation. However, the Vss, Vsub and all NC terminals

must be grounded. A start pulse φst and 2-phase clock pulses

φ1, φ2 are needed to drive the shift register. These start and

clock pulses are positive going pulses and CMOS logic com-

patible.

The 2-phase clock pulses φ1, φ2 can be either completely

separated or complementary. However, both pulses must not

be “High” at the same time.

The amplitude of start pulse φst is the same as the φ1 and φ2

pulses. The shift register starts the scanning at the “High”

level of φst, so the start pulse interval determines the length of

signal accumulation time. The φst pulse must be held “High”

at least 200 ns and overlap with φ2 at least for 200 ns. To

operate the shift register correctly, φ2 must change from the

“High” level to the “Low” level only once during “High” level of

φst. The timing chart for each pulse is shown in “ꢀTiming

chart for driver circuit”.

A clock pulse space (X1 and X2 in “ꢀTiming chart for driver

circuit”) of a “rise time/fall time - 20” ns or more should be

input if the rise and fall times of φ1, φ2 are longer than 20 ns.

The φ1 and φ2 clock pulses must be held at “High” at least

200 ns. Since the photodiode signal is obtained at the rise of

each φ2 pulse, the clock pulse frequency will equal the video

data rate.

ꢀꢀEnd of scan

The end of scan (EOS) signal appears in synchronization

with the φ2 timing right after the last photodiode is addressed,

and the EOS terminal should be pulled up at 5 V using a 10

kΩ resistor.

ꢀ Timing chart for driver circuit

ꢀ Video bias voltage margin

tpw

s (H)

s (L)

tpw

1 (H)

1 (L)

2 (H)

2 (L)

tpw

tvd

Active video output

End of scan

tf s

Video bias range

tf 1

MIN.

Clock pulse amplitude (V)

KMPDC0022EA

KMPDB0043EA

ꢀꢀSignal readout circuit

There are two methods for reading out the signal from an NMOS

linear image sensor. One is a current detection method using

the load resistance and the other is a current integration method

using a charge amplifier. In either readout method, a positive

bias must be applied to the video line because photodiode

anodes of NMOS linear image sensors are set at 0 V (Vss).

“ꢀVideo bias voltage margin” shows a typical video bias volt-

age margin. As the clock pulse amplitude is higher, the video

bias voltage can be set larger so the saturation charge can be

increased. The rise and fall times of the video output waveform

can be shortened if the video bias voltage is reduced while the

clock pulse amplitude is still higher.When the amplitude of φ1,

φ2 and φst is 5 V, setting the video bias voltage at 2 V is recom-

mended.

To obtain good linearity, using the current integration method is

advised. In this method, the integration capacitance is reset to

the reference voltage level immediately before each photodiode

is addressed and the signal charge is then stored as an integra-

tion capacitive charge when the address switch turns on.

“ꢀReadout circuit example” and “ꢀTiming chart” show a typi-

cal current integration circuit and its pulse timing chart. To en-

sure stable output, the rise of a reset pulse must be delayed at

least 50 ns from the fall of φ2.

Hamamatsu provides the following driver circuits and related

products (sold separately).

Product

name

Type No.

C7883

Content

Feature

High-speed

driver circuit

C7883

+ C8225-01

Precision

driver circuit

C7884

+ C8225-01

High precision

driver circuit

C7884-01

+ C8225-01

C7883,

High-speed operation

Single power supply

(+15 V) operation

Com pact

C7883G

C7884

Low noise

Good output linearity

Boxcar w aveform output

Driver

circuit

C7884G

C7884-01

C7884G -01

C8225-01

A8226

Ultra-low noise

Good output linearity

Boxcar w aveform output

Pulse

generator

C7884 series

C7883 to

C7885 series

Cable

BNC, length 1 m

NMOS linear image sensor S3901/S3904 series

ꢀ Readout circuit example

ꢀ Timing chart

+5 V

50 ns Min.

10 kΩ

EOS

Reset

1, Reset

Dummy

video

Open

10 pF

Vscg

Vss

Active

video

–

Vsub

KMPDC0024EA

Vscd

Op amp (JFET input)

+2 V

KMPDC0023EA

Output voltage Vout is expressed by the following equation.

[ ]

Output charge C

[ ]

Vout V =

10 × 10^-12

[ ]

ꢀ Anti-blooming function

If the incident light intensity is higher than the saturation charge level, even partially, a signal charge in excess of the saturation

charge cannot accumulate in the photodiode. This excessive charge flows out into the video line degrading the signal purity. To

avoid this problem and maintain the signal purity, applying the same voltage as the video bias voltage to the saturation control

drain and grounding the saturation control gate are effective. If the incident light intensity is extremely high, a positive bias should

be applied to the saturation control gate. The larger the voltage applied to the saturation control gate, the higher the function for

suppressing the excessive saturation charge will be. However, this voltage also lowers the amount of saturation charge, so an

optimum bias voltage should be selected.

ꢀ Auxiliary functions

(1) All reset

In normal operation, the accumulated charge in each photodiode is reset when the signal is read out. Besides this method that

uses the readout line, S3901/S3904 series can reset the photodiode charge by applying a pulse to the saturation control gate.

The amplitude of this pulse should be equal to the φ1, φ2 and φst pulses and the pulse width should be longer than 5 µs.

When the saturation control gate is set at the “High” level, all photodiodes are reset to the saturation control drain potential

(equal to video bias). Conversely, when the saturation control gate is set at the “Low” level (0 V), the signal charge accumulates

in each photodiode without being reset.

(2) Dummy video

S3901/S3904 series have a dummy video line to eliminate spike noise contained in the video output waveform. Video signal

with lower spike noise can be obtained by differential amplification applied between the active video line and dummy video

line outputs. When not needed, leave this unconnected.

ꢀ Handling precautions

(1) Electrostatic countermeasures

NMOS linear image sensors are designed to resist static electrical charges. However, take sufficient cautions and countermea-

sures to prevent damage from static charges when handling the sensors.

(2) Window

If dust or grime sticks to the surface of the light input window, it appears as a black blemish or smear on the image. Before using

the image sensor, the window surface should be cleaned. Wipe off the window surface with a soft cloth, cleaning paper or

cotton swab slightly moistened with organic solvent such as alcohol, and then lightly blow away with compressed air. Do not

rub the window with dry cloth or cotton swab as this may generate static electricity.

Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions.

Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein.

Type numbers of products listed inthe specification sheets or supplied as samples may have a suffix "(X)" which means tentative specifications or a suffix "(Z)"

HAMAMATSU PHOTONICS K.K., Solid State Division

1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184, www.hamamatsu.com

U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218

Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 8152-375-0, Fax: (49) 8152-265-8

France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10

United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777

North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01

Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1 int. 6, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741

Cat. No. KMPD1036E03

Jul. 2010 DN

C3901 [HAMAMATSU]

相关型号：

C3901_10

C390A

C390AX500

C390AX550

C390BX500

C390BX550

C390C

C390CX500

C390CX550

C390D

C390DX500

C390DX550