S11071-1106 [HAMAMATSU]
CCD Sensor, 2048 Horiz pixels, 64 Vert pixels, Rectangular, Through Hole Mount, DIP-24;
| 型号： | S11071-1106 |
| 厂家： | 
HAMAMATSU CORPORATION |
| 描述： | CCD Sensor, 2048 Horiz pixels, 64 Vert pixels, Rectangular, Through Hole Mount, DIP-24 CD 传感器 换能器 |
| 文件： | 总10页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CCD image sensors
S11071/S10420-01 series
Improved etaloning characteristics,
High-speed type and low noise type available
The S11071/S10420-01 series are back-thinned CCD image sensors designed for spectrometers. Two types consisting of
a high-speed type (S11071 series) and low noise type (S10420-01 series) are available with improved etaloning charac-
teristics. The S11071/S10420-01 series offer nearly flat spectral response characteristics with high quantum efficiency
from the UV to near infrared region.
Features
Applications
Improved etaloning characteristics
Spectrometers, etc.
High sensitivity over a wide spectral range and nearly
flat spectral response characteristics
-
High CCD node sensitivity: 8 μV/e (S11071 series)
-
6.5 μV/e (S10420-01 series)
High full well capacity and wide dynamic range
(with anti-blooming function)
Pixel size: 14 × 14 μm
Selection guide
Readout speed
max.
Number of
Type no.
Number of effective
pixels
Image size
Suitable
driver circuit
total pixels
[mm (H) mm (V)]
×
(MHz)
S11071-1004
1044 22
1024 16
14.336 0.224
×
×
×
S11071-1006
S11071-1104
S11071-1106
S10420-1004-01
S10420-1006-01
S10420-1104-01
S10420-1106-01
1044 70
1024 64
14.336 0.896
28.672 0.224
×
×
×
×
10
C11288
C11287
2068 22
2048 16
×
×
2068 70
2048 64
28.672 0.896
×
×
×
1044 22
1024 16
14.336 0.224
×
×
×
1044 70
1024 64
14.336 0.896
×
×
×
0.5
2068 22
2048 16
28.672 0.224
×
×
×
2068 70
2048 64
28.672 0.896
×
×
×
Improved etaloning characteristics
Etaloning is an interference phenomenon that occurs when the light
incident on a CCD repeatedly reflects between the front and back
surfaces of the CCD while being attenuated, and causes alternately
high and low sensitivity. When long-wavelength light enters a back-
thinned CCD, etaloning occurs due to the relationship between the
silicon substrate thickness and the absorption length. The S11071/
S10420-01 series back-thinned CCDs have achieved a significant im-
provement in etaloning by using a unique structure that is unlikely
to cause interference.
Etaloning characteristics (typical example)
(Ta=25 °C)
110
100
90
80
70
60
50
40
30
20
Etaloning-improved type
Previous type
10
0
900 910 920 930 940 950 960 970 980 990 1000
Wavelength (nm)
KMPDB0284EB
1
www.hamamatsu.com
CCD image sensors
S11071/S10420-01 series
Structure
Parameter
S11071 series
S10420-01 series
Pixel size (H V)
14 14 μm
×
×
Vertical clock phase
Horizontal clock phase
Output circuit
Package
2-phase
4-phase
Two-stage MOSFET source follower
One-stage MOSFET source follower
24-pin ceramic DIP (refer to dimensional outline)
Window material*1
Cooling
Quartz glass*2
Non-cooled
*1: Temporary window type (ex: S11071-1106N, S10420-1106N-01) is available upon request.
*2: Resin sealing
Absolute maximum ratings (Ta=25 °C)
Parameter
Operating temperature*3
Storage temperature
Symbol
Topr
Tstg
Min.
-50
-50
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-10
-10
-10
-10
-10
-10
-10
-10
Typ.
Max.
+50
+70
+25
+30
+18
+18
+18
+18
+18
+15
+15
+15
+15
+15
+15
+15
+15
Unit
°C
°C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
S11071 series
S10420-01 series
Output transistor
drain voltage
VOD
V
Reset drain voltage
Output amplifier return voltage
Overflow drain voltage
Vertical input source voltage
Horizontal input source voltage
Overflow gate voltage
Vertical input gate voltage
Horizontal input gate voltage
Summing gate voltage
Output gate voltage
Reset gate voltage
Transfer gate voltage
Vertical shift register clock voltage
VRD
Vret
VOFD
VISV
VISH
V
V
V
V
V
V
V
V
V
V
V
V
V
VOFG
VIG1V, VIG2V
VIG1H, VIG2H
VSG
VOG
VRG
VTG
VP1V, VP2V
VP1H, VP2H
VP3H, VP4H
Horizontal shift register clock voltage
-10
-
+15
V
*3: Package temperature
Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the
product within the absolute maximum ratings.
Operating conditions (MPP mode, Ta=25 °C)
S11071 series
S10420-01 series
Parameter
Symbol
Unit
Min.
12
14
11
0
Typ.
15
15
12
13
5
Max.
Min.
Typ.
24
12
12
12
5
Max.
Output transistor drain voltage
Reset drain voltage
Overflow drain voltage
Overflow gate voltage
Output gate voltage
VOD
VRD
VOFD
VOFG
VOG
18
16
13
14
6
-
2
-
-
23
11
11
0
25
13
13
13
6
V
V
V
V
V
V
V
V
V
V
4
-
-
-
-9
-9
4
4
Substrate voltage
VSS
Vret
0
1
VRD
-8
-8
-
0
-
Output amplifier return voltage*4
Input source
VISV, VISH
VIG1V, VIG2V
VIG1H, VIG2H
VP1VH, VP2VH
VP1VL, VP2VL
VP1HH, VP2HH
VP3HH, VP4HH
VP1HL, VP2HL
VP3HL, VP4HL
VSGH
-
VRD
-8
-8
6
-8
-
-
-
8
-7
Test point
Vertical input gate
Horizontal input gate
-9
-9
4
-
8
-7
High
Low
6
-8
Vertical shift register clock voltage
Horizontal shift register clock voltage
V
-9
-9
High
Low
4
6
8
4
6
8
V
-6
-5
-4
-6
-5
-4
High
Low
High
Low
High
Low
4
-6
4
-6
4
6
-5
6
-5
6
8
-4
8
-4
8
4
-6
4
6
-5
6
8
-4
8
Summing gate voltage
Reset gate voltage
V
V
V
VSGL
VRGH
VRGL
VTGH
VTGL
RL
-6
4
-5
6
-4
8
Transfer gate voltage
-9
2.0
-8
2.2
-7
2.4
-9
90
-8
100
-7
110
kΩ
External load resistance
*4: Output amplifier return voltage is a positive voltage with respect to Substrate voltage, but the current flows in the direction of flow
out of the sensor.
2
CCD image sensors
S11071/S10420-01 series
Electrical characteristics (Ta=25 °C)
S11071 series
S10420-01 series
Parameter
Symbol
fc
Unit
MHz
Min.
Typ.
5
Max.
10
-
-
-
-
-
-
-
-
-
-
-
9
-
-
Min.
Typ.
0.25
200
600
400
1200
80
Max.
0.5
-
Signal output frequency*5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-1004(-01)
-1006(-01)
-1104(-01)
-1106(-01)
200
600
400
1200
80
160
10
10
-
-
-
-
-
-
-
-
Vertical shift register
capacitance
pF
CP1V, CP2V
-1004(-01)/-1006(-01)
-1104(-01)/-1106(-01)
Horizontal shift register
capacitance
CP1H, CP2H
CP3H, CP4H
pF
160
10
10
30
60
Summing gate capacitance
Reset gate capacitance
pF
pF
CSG
CRG
-1004(-01)/-1006(-01)
-1104(-01)/-1106(-01)
30
60
Transfer gate capacitance
pF
CTG
-
-
Charge transfer efficiency*6
DC output level*5
Output impedance*5
Power consumption*5 *7
CTE
Vout
Zo
0.99995 0.99999
0.99995 0.99999
-
V
kΩ
mW
7
-
-
8
0.3
75
17
-
18
10
4
19
-
P
-
-
*5: The values depend on the load resistance. (S11071 series: VOD=15 V, RL=2.2 kΩ, S10420-01 series: VOD=24 V, RL=100 kΩ)
*6: Charge transfer efficiency per pixel, measured at half of the full well capacity
*7: Power consumption of the on-chip amplifier plus load resistance
Electrical and optical characteristics (Ta=25 °C, unless otherwise noted)
S11071 series
Typ.
S10420-01 series
Min. Typ. Max.
Parameter
Saturation output voltage
Symbol
Vsat
Unit
V
Min.
Max.
-
-
-
9
500
28
-
-
50
150
7
-
-
Fw Sv
×
-
50
250
5.5
-
Fw Sv
×
-
-
-
Vertical
Horizontal
60
200
8
50
23
60
300
6.5
Full well capacity
Fw
ke-
CCD node sensitivity*8
Dark current*9
Readout noise*10
Dynamic range*11
Sv
DS
Nr
7.5
500
15
-
μV/e-
e-/pixel/s
e- rms
-
50
-
6
Line binning
DR
6520
8700
41700
50000
200 to
1100
±3
200 to
1100
±3
Spectral response range
λ
-
-
-
-
-
-
nm
%
Photoresponse nonuniformity*12
PRNU
±10
±10
*8: The values depend on the load resistance. (S11071 series: VOD=15 V, RL=2.2 kΩ, S10420-01 series: VOD=24 V, RL=100 kΩ)
*9: Dark current is reduced to half for every 5 to 7 °C decrease in temperature.
*10: S11071 series (temperature: 25 °C): fc=2 MHz, S10420-01 series (temperature: -40 °C): fc=20 kHz
*11: Dynamic range = Full well capacity / Readout noise
*12: Measured at one-half of the saturation output (full well capacity) using LED light (peak emission wavelength: 660 nm)
Fixed pattern noise (peak to peak)
Photoresponse nonuniformity =
× 100 [%]
Signal
3
CCD image sensors
S11071/S10420-01 series
Spectral response (without window)*13
Spectral transmittance characteristic of window material
(Typ. Ta=25 °C)
(Typ. Ta=25 °C)
100
80
60
40
20
0
100
80
60
40
20
0
200
400
600
800
1000
1200
100 200 300 400 500 600 700 800 900 1000 1100
Wavelength (nm)
Wavelength (nm)
KMPDB0316EA
KMPDB0303EA
*13: Spectral response with quartz glass is decreased according to
the spectral transmittance characteristic of window material.
Dark current vs. temperature
(Typ.)
100
10
1
0.1
0.01
-50 -40
-30
-20 -10
0
10
20
30
Temperature (°C)
KMPDB0304EA
4
CCD image sensors
S11071/S10420-01 series
Device structure (conceptual drawing of top view in dimensional outline)
S11071 series
Effective pixels
Thinning
Effective pixels
23 22 21 20 19
18 17 16
64
15
14
13
Horizontal
shift register
5
4
3
2
1
2
3
4
5
1024
24
V=16, 64
H=1024, 2048
1
2
3
4
5
6
7
8
9
10
11 12
4 blank pixels
2n signal output
4 blank pixels
6-bevel
Horizontal
shift register
6-bevel
Note: When viewed from the direction of the incident light, the horizontal shift register is
covered with a thick silicon layer (dead layer). However, long-wavelength light
passes through the silicon dead layer and may possibly be detected by the horizontal
shift register. To prevent this, provide light shield on that area as needed.
KMPDC0343EB
S10420-01 series
Effective pixels
Thinning
Effective pixels
23 22 21 20 19
18 17 16
64
15
14
13
Horizontal
shift register
5
4
3
2
1
2
3
4
5
1024
24
V=16, 64
H=1024, 2048
1
2
3
4
5
6
7
8
9
10
11 12
4 blank pixels
2n signal output
4 blank pixels
6-bevel
Horizontal
shift register
6-bevel
Note: When viewed from the direction of the incident light, the horizontal shift register is
covered with a thick silicon layer (dead layer). However, long-wavelength light
passes through the silicon dead layer and may possibly be detected by the horizontal
shift register. To prevent this, provide light shield on that area as needed.
KMPDC0269EC
5
CCD image sensors
S11071/S10420-01 series
Timing chart (line binning)
Integration time
Vertical binning period
Readout period
(shutter has to be open)
(shutter has to be closed)
(shutter has to be closed)
←
3...21 22 16 + 6 (bevel): S11071/S10420-1004, -1104
Tpwv
←
3...69 70 64 + 6 (bevel): S11071/S10420-1006, -1106
1
2
P1V
Toovvrr
P2V, TG
4...1043 1044: S11071/S10420-1004, -1006
4...2067 2068: S11071/S10420-1104, -1106
Tpwh, Tpws Tovrh
1
2
3
P1H
P2H
P3H
P4H, SG
RG
Tpwr
OS
D1
D2
D3...D10, S1...S1024, D11...D18: S11071/S10420-1004, -1006
S1...S2048 : S11071/S10420-1104, -1106
D19
D20
KMPDC0270ED
S11071 series
S10420-01 series
Parameter
Symbol
Unit
Min.
1
Typ.
8
-
100
-
50
50
100
-
50
50
50
-
Max.
-
-
-
-
-
60
-
-
-
Min.
6
20
Typ.
8
-
Max.
Pulse width*14
Rise and fall times*14
Pulse width*14
Tpwv
Tprv, Tpfv
Tpwh
Tprh, Tpfh
Tovrh
-
-
-
-
-
μs
ns
ns
ns
ns
%
ns
ns
ns
%
ns
ns
μs
P1V, P2V, TG
20
50
10
25
40
50
10
25
40
5
1000
10
2000
-
Rise and fall times*14
Pulse overlap time
Duty ratio*14
P1H, P2H, P3H, P4H
500
40
1000
10
1000
50
2000
-
-
60
-
Pulse width*14
Tpws
Tprs, Tpfs
Tovrh
Rise and fall times*14
Pulse overlap time
Duty ratio*14
Pulse width
Rise and fall times
Overlap time
-
-
SG
500
40
100
5
1000
50
1000
-
-
60
-
-
60
-
Tpwr
Tprr, Tpfr
Tovr
RG
5
1
-
-
TG-P1H
2
-
1
2
*14: Symmetrical clock pulses should be overlapped at 50% of maximum pulse amplitude.
6
CCD image sensors
S11071/S10420-01 series
Dimensional outline (unit: mm)
3.3 0.35
A
24
13
12
1
Index mark
Index mark
27.94 0.3
38.10 0.4
Photosensitive surface
Photosensitive area
Type no.
A
B
-1004(-01) 14.336 (H) 0.224 (V)
-1006(-01) 14.336 (H) 0.896 (V)
-1104(-01) 28.672 (H) 0.224 (V)
-1106(-01) 28.672 (H) 0.896 (V)
0.46 0.05
1.27 0.2
2.54 0.13
S11071/
S10420
KMPDA0223EE
7
CCD image sensors
S11071/S10420-01 series
Pin connections
S11071 series
Function
Pin no.
1
Symbol
OS
Remark (standard operation)
RL=2.2 kΩ
Output transistor source
2
3
OD
OG
Output transistor drain
Output gate
+15 V
+5 V
4
5
6
SG
Vret
RD
Summing gate
Output amplifier return
Reset drain
Same pulse as P4H
+1 V
+15 V
7
8
9
P4H
P3H
P2H
P1H
IG2H
IG1H
OFG
OFD
ISH
ISV
CCD horizontal register clock-4
CCD horizontal register clock-3
CCD horizontal register clock-2
CCD horizontal register clock-1
Test point (horizontal input gate-2)
Test point (horizontal input gate-1)
Over flow gate
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
-8 V
-8 V
+13 V
+12 V
Connect to RD
Connect to RD
GND
+15 V
-8 V
Over flow drain
Test point (horizontal input source)
Test point (vertical input source)
Substrate
SS
RD
Reset drain
IG2V
IG1V
P2V
P1V
TG
Test point (vertical input gate-2)
Test point (vertical input gate-1)
CCD vertical register clock-2
CCD vertical register clock-1
Transfer gate
-8 V
Same pulse as P2V
RG
Reset gate
S10420-01 series
Pin no.
1
Symbol
OS
OD
Function
Output transistor source
Output transistor drain
Output gate
Remark (standard operation)
RL=100 kΩ
+24 V
2
3
OG
+5 V
4
5
SG
SS
Summing gate
Substrate
Same pulse as P4H
GND
6
RD
Reset drain
+12 V
7
8
9
P4H
P3H
P2H
P1H
IG2H
IG1H
OFG
OFD
ISH
ISV
CCD horizontal register clock-4
CCD horizontal register clock-3
CCD horizontal register clock-2
CCD horizontal register clock-1
Test point (horizontal input gate-2)
Test point (horizontal input gate-1)
Over flow gate
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
-8 V
-8 V
+12 V
+12 V
Connect to RD
Connect to RD
GND
+12 V
-8 V
Over flow drain
Test point (horizontal input source)
Test point (vertical input source)
Substrate
SS
RD
Reset drain
IG2V
IG1V
P2V
P1V
TG
Test point (vertical input gate-2)
Test point (vertical input gate-1)
CCD vertical register clock-2
CCD vertical register clock-1
Transfer gate
-8 V
Same pulse as P2V
RG
Reset gate
8
CCD image sensors
S11071/S10420-01 series
Precautions (electrostatic countermeasures)
・Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with an
earth ring, in order to prevent electrostatic damage due to electrical charges from friction.
・Avoid directly placing these sensors on a work-desk or work-bench that may carry an electrostatic charge.
・Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to discharge.
・Ground the tools used to handle these sensors, such as tweezers and soldering irons.
It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the
amount of damage that occurs.
Related information
www.hamamatsu.com/sp/ssd/doc_en.html
Precautions
∙ Notice
∙ Image sensors/Precautions
Technical information
∙ FFT-CCD area image sensor/Technical information
Driver circuits for CCD image sensor (S10420-01/S11071 series) C11287/C11288 [sold separately]
The C11287, C11288 are driver circuits designed for HAMAMATSU CCD image sensors S10420-01/S11071 series. The C11287, C11288
can be used in spectrometers, etc. when combined with the CCD image sensor.
Features
Built-in 14-bit A/D converter
Interface to computer: USB 2.0
Power supply: USB bus power operation (C11287)
DC+5 V operation (C11288)
C11287
C11288
9
CCD image sensors
S11071/S10420-01 series
Information described in this material is current as of February, 2014.
Product specifications are subject to change without prior notice due to improvements or other reasons. This document has been carefully prepared and the
information contained is believed to be accurate. In rare cases, however, there may be inaccuracies such as text errors. Before using these products, always
contact us for the delivery specification sheet to check the latest specifications.
Type numbers of products listed in the delivery specification sheets or supplied as samples may have a suffix "(X)" which means preliminary specifications or
a suffix "(Z)" which means developmental specifications.
The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that
one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product
use.
Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission.
www.hamamatsu.com
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 8152-375-0, Fax: (49) 8152-265-8
France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10
United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777
North Europe: Hamamatsu Photonics Norden AB: Thorshamnsgatan 35 16440 Kista, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01
Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1 int. 6, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
China: Hamamatsu Photonics (China) Co., Ltd.: 1201 Tower B, Jiaming Center, No.27 Dongsanhuan Beilu, Chaoyang District, Beijing 100020, China, Telephone: (86) 10-6586-6006, Fax: (86) 10-6586-2866
10
Cat. No. KMPD1120E08 Feb. 2014 DN
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PERICOM
S1109A-FREQ4-OUT3
TTL Output Clock Oscillator, 80MHz Min, 110MHz Max, FULL SIZE, RESISTANCE WELDED, METAL, DIP-4
PERICOM
S1109B-FREQ1-OUT3
TTL Output Clock Oscillator, 20MHz Min, 30MHz Max, HALF SIZE, RESISTANCE WELDED, METAL, DIP-4
PERICOM
S1109C-FREQ1-OUT3
TTL Output Clock Oscillator, 20MHz Min, 30MHz Max, HALF SIZE, RESISTANCE WELDED, METAL, DIP-4
PERICOM
S1109C-FREQ2-OUT3
TTL Output Clock Oscillator, 30MHz Min, 70MHz Max, HALF SIZE, RESISTANCE WELDED, METAL, DIP-4
PERICOM
S1109C-FREQ3-OUT3
TTL Output Clock Oscillator, 70MHz Min, 80MHz Max, FULL SIZE, RESISTANCE WELDED, METAL, DIP-4
PERICOM
S1109C-FREQ4-OUT3
TTL Output Clock Oscillator, 80MHz Min, 110MHz Max, FULL SIZE, RESISTANCE WELDED, METAL, DIP-4
PERICOM
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