HMD8M32M16EB-6 概述
DRAM
HMD8M32M16EB-6 数据手册
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HMD8M32M16EBG
32Mbyte(8Mx32) 72-pin EDO MODE 2K Ref. SIMM Design 5V
Part No. HMD8M32M16EBG
GENERAL DESCRIPTION
The HMD8M32M16EBG is a 8M x 32bit dynamic RAM high density memory module. The module consists of sixteen
CMOS 4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1
or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a
single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All
module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
FEATURES
PIN ASSIGNMENT
w Part Identification
HMD8M32M16EB---- 2048 Cycles/32ms Ref. Solder
PIN SYMBOL PIN
SYMBOL
DQ22
DQ7
DQ23
A7
PIN SYMBOL
HMD8M32M16EBG-- 2048 Cycles/32ms Ref. Gold
w Access times : 50, 60ns
1
2
Vss
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
Vcc
NC
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
DQ8
DQ24
DQ9
w High-density 32MByte design
w Single + 5V ±0.5V power supply
w JEDEC standard PDpin and pinout
w EDO mode operation
3
4
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
Vcc
5
NC
6
Vcc
w TTL compatible inputs and outputs
w FR4-PCB design
7
A8
8
A9
9
/RAS3
/RAS2
NC
OPTIONS
w Timing
MARKING
10
11
12
13
14
15
16
17
18
19
20
50ns access
60ns access
-5
-6
A0
NC
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
A1
NC
A2
NC
w Packages
A3
Vss
72-pin SIMM
M
A4
/CAS0
/CAS2
/CAS3
/CAS1
/RAS0
A5
PRESENCE DETECT PINS
A6
Pin
50ns
NC
60ns
NC
A10
DQ4
PD1
PD1
PD2
PD3
PD4
PD2
Vss
Vss
Vss
Vss
NC
21
DQ20
45
/RAS1
69
PD3
22
23
24
DQ5
DQ21
DQ6
46
47
48
NC
/WE
NC
70
71
72
PD4
NC
NC
Vss
SIMM TOP VIEW
PERFORMANCE RANGE
Speed
TRAC
50ns
60ns
tCAC
13ns
15ns
tRC
tHPC
26ns
30ns
5
6
90ns
110ns
Note: A11 is not used for HMD8M32M16EB
URL:www.hbe.co.kr
REV.1.0 (August.2002)
- 1 -
HANBit Electronics Co.,Ltd.
HANBit
HMD8M32M16EBG
FUNCTIONAL BLOCK DIAGRAM
/CAS0
DQ0-3
/CAS
/RAS
/OE
DQ1
DQ2
DQ3
DQ1
DQ2
DQ3
/CAS
/RAS
/OE
U1
U9
/RAS0
/RAS1
/W A0 -A10(A11) . DQ4
DQ4 A0-A10(A11)
/W
DQ4-7
DQ8-11
DQ12-15
/CAS
/RAS
/OE
DQ1
DQ2
DQ3
DQ1
DQ2
DQ3
/CAS
/RAS
/OE
U3
U11
/W A0 -A10(A11) DQ4
DQ4 A0-A10(A11) /W
/CAS1
/CAS
/RAS
/OE
DQ1
DQ2
DQ3
DQ1
DQ2
DQ3
/CAS
/RAS
/OE
U5
U13
/W A0 -A10(A11) . DQ4
DQ4 A0-A10(A11)
/W
/CAS
/RAS
/OE
DQ1
DQ2
DQ3
DQ1
DQ2
DQ3
/CAS
/RAS
/OE
U7
U15
/W A0 -A10(A11). DQ4
DQ4 A0-A10(A11)
/W
/CAS2
/RAS2
DQ16-19
DQ20-23
/CAS
/RAS
/OE
DQ1
DQ2
DQ3
DQ1
DQ2
DQ3
/CAS
/RAS
/OE
U2
U10
/RAS3
/W A0 -A10(A11). DQ4
DQ4 A0-A10(A11)
/W
/CAS
/RAS
/OE
DQ1
DQ2
DQ3
DQ1
DQ2
DQ3
/CAS
/RAS
/OE
U4
U12
/W A0 -A10(A11). DQ4
DQ4 A0-A10(A11) /W
/CAS3
DQ24-27
DQ28-31
/CAS
/RAS
/OE
DQ1
DQ2
DQ3
DQ1
DQ2
DQ3
/CAS
/RAS
/OE
U14
U6
/W A0 -A10(A11). DQ4
DQ4 A0-A10(A11)
/W
/CAS
/RAS
/OE
DQ1
DQ2
DQ3
DQ1
DQ2
DQ3
/CAS
/RAS
/OE
U8
U16
/W A0 -A10(A11). DQ4
DQ4 A0-A10(A11)
/W
/WE
A0-A10
(A11)
URL:www.hbe.co.kr
REV.1.0 (August.2002)
- 2 -
HANBit Electronics Co.,Ltd.
HANBit
HMD8M32M16EBG
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
SYMBOL
VIN ,OUT
Vcc
RATING
-1V to 7.0V
-1V to 7.0V
16W
PD
o
o
Storage Temperature
TSTG
-55 C to 150 C
Short Circuit Output Current
IOS
50mA
w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
o
( Voltage reference to VSS, T =0 to 70 C )
A
PARAMETER
Supply Voltage
SYMBOL
Vcc
MIN
4.5
0
TYP.
MAX
5.5
UNIT
5.0
V
V
V
V
Ground
Vss
0
-
0
Input High Voltage
Input Low Voltage
VIH
2.4
-1.0
Vcc+1
0.8
VIL
-
DC AND OPERATING CHARACTERISTICS
SYMBOL
SPEED
MIN
MAX
816
736
32
UNITS
Ma
MA
MA
MA
MA
MA
MA
MA
MA
MA
mA
ICC1
-5
-
-6
-
ICC2
ICC3
Don't care
-
-5
-
816
736
896
816
16
-6
-
ICC4
-5
-
-6
-
-
ICC5
ICC6
Don't care
-5
-6
-
816
736
80
-
Il(L)
IO(L)
VOH
VOL
-80
-10
2.4
-
10
mA
-
V
0.4
V
ICC1 : Operating Current * (/RAS , /CAS , Address cycling @tRC=min.)
ICC2 : Standby Current ( /RAS=/CAS=VIH
)
ICC3 : /RAS Only Refresh Current * ( /CAS=VIH, /RAS, Address cycling @tRC=min )
ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min )
URL:www.hbe.co.kr
REV.1.0 (August.2002)
- 3 -
HANBit Electronics Co.,Ltd.
HANBit
HMD8M32M16EBG
ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V )
ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @tRC=min )
IIL : Input Leakage Current (Any input 0V £ VIN £ 6.5V, all other pins not under test = 0V)
IOL : Output Leakage Current (Data out is disabled, 0V £ VOUT £ 5.5V
VOH : Output High Voltage Level (IOH= -5mA )
VOL : Output Low Voltage Level (IOL = 4.2mA )
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the
output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once
while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
CAPACITANCE ( TA=25oC, Vcc = 5V, f = 1Mz )
DESCRIPTION
Input Capacitance (A0-A11)
SYMBOL
CIN1
MIN
MAX
100
130
40
UNITS
pF
-
-
-
-
-
Input Capacitance (/W)
C IN2
pF
Input Capacitance (/RAS0)
CIN3
pF
Input Capacitance (/CAS0-/CAS3)
Input/Output Capacitance (DQ0-31)
CIN4
30
pF
CDQ1
20
pF
o
o
AC CHARACTERISTICS ( 0 C £ TA £ 70 C , Vcc = 5V±10%, See notes 1,2.)
-5
-6
STANDARD OPERATION
SYMBOL
UNIT
MIN
MAX
MIN
MAX
Random read or write cycle time
Access time from /RAS
Access time from /CAS
Access time from column address
/CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
/RAS precharge time
tRC
tRAC
tCAC
tAA
90
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
13
25
60
15
30
tCLZ
tOFF
tT
3
3
3
13
50
3
13
50
2
2
tRP
30
50
13
38
8
40
60
15
45
10
20
15
5
/RAS pulse width
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
- 4 -
10K
10K
/RAS hold time
/CAS hold time
/CAS pulse width
10K
37
10K
45
/RAS to /CAS delay time
/RAS to column address delay time
/CAS to /RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
20
15
5
25
30
0
0
10
0
10
0
URL:www.hbe.co.kr
REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.
HANBit
HMD8M32M16EBG
Column address hold time
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWCR
tWP
8
10
30
0
ns
ns
ns
ns
Column Address to /RAS lead time
Read command set-up time
Read command hold referenced to /CAS
Read command hold referenced to /RAS
Write command hold time
25
0
0
0
0
0
ns
10
50
10
13
8
10
55
10
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write command hold referenced to /RAS
Write command pulse width
Write command to /RAS lead time
Write command to /CAS lead time
Data-in set-up time
tRWL
tCWL
tDS
0
Data-in hold time
tDH
8
10
32
0
Refresh period
tREF
tWCS
tCSR
tCHR
tRPC
tCPA
tCP
32
Write command set-up time
/CAS setup time (C-B-R refresh)
/CAS hold time (C-B-R refresh)
/RAS precharge to /CAS hold time
Access time from /CAS precharge
/CAS precharge time (Fast page)
/RAS pulse width (Fast page )
/W to /RAS precharge time (C-B-R
refresh)
0
5
5
10
5
10
5
30
35
8
10
tRASP
tWRP
50
10
200K
60
10
200K
/W to /RAS hold time (C-B-R refresh)
tWRH
10
10
ns
NOTES
1.An initial pause of 200ms is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 1TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC
5.Assumes that tRCD ³ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
.
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH
or VOL
.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If tWCS
³
tWCS(min) the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read-
write cycles.
11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference
point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA
.
URL:www.hbe.co.kr
REV.1.0 (August.2002)
- 5 -
HANBit Electronics Co.,Ltd.
HANBit
HMD8M32M16EBG
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE
tRC
tRAS
tRP
VIH-
/RAS
VIL-
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH-
/CAS
VIL-
tRAD
tASR
tRAH
tCAH
tRAL
tASC
VIH-
ROW ADDRESS
COLUMN ADDRESS
A
/W
VIL-
tRCH
tRCS
tRRH
VIH-
VIL-
tWEZ
tCEZ
tOEZ
tAA
VIH-
VIL-
tOEA
tCAC
/OE
tCLZ
tREZ
tRAC
VOH-
VOL-
DQ0-DQ7
DATA-OUT
OPEN
TIMING WAVEFORM OF WRITE CYCLE (EARLY WRITE)
NOTE : Dout = Open
tRC
tRAS
/RAS
VIH-
tRP
VIL-
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH-
VIL-
/CAS
A
tRAD
tASR
tRAH
tCAH
tRAL
tASC
VIH-
VIL-
ROW ADDRESS
COLUMN ADDRESS
tCWL
tRWL
tWCS
tWCH
VIH-
VIL-
tWP
/W
VIH-
VIL-
/OE
tDS
tDH
VOH-
VOL-
DQ0-DQ7
DATA-IN
URL:www.hbe.co.kr
REV.1.0 (August.2002)
- 6 -
HANBit Electronics Co.,Ltd.
HANBit
HMD8M32M16EBG
PACKAGING INFORMATION
SIMM Design
2.54 mm
MIN
0.25 mm MAX
1.27 ±0.08mm
Gold : 1.04±0.10 mm
Solder:0.914±0.10mm
1.27 mm
ORDERING INFORMATION
Component
Vcc
Part Number
Density
Org.
Package
Access Time
Number
HMD8M32M16EBG-5
HMD8M32M16EBG-6
32MByte
32MByte
72Pin-SIMM
72Pin-SIMM
16EA
16EA
5V
5V
50ns
60ns
8MX 32bit
8MX 32bit
URL:www.hbe.co.kr
REV.1.0 (August.2002)
- 7 -
HANBit Electronics Co.,Ltd.
HMD8M32M16EB-6 相关器件
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