HMS51232M4L-12 [HANBIT]
SRAM MODULE 2Mbyte (512K x 32-Bit), LOW POWER, 72-Pin SIMM 5V; SRAM模块2Mbyte （ 512K ×32位） ，低功耗， 72引脚SIMM 5V
| 型号： | HMS51232M4L-12 |
| 厂家： | 
HANBIT ELECTRONICS CO.,LTD |
| 描述： | SRAM MODULE 2Mbyte (512K x 32-Bit), LOW POWER, 72-Pin SIMM 5V |
| 文件： | 总10页 (文件大小：393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HANBit
HMS51232M4L
H A N
SRAM MODULE 2Mbyte (512K x 32-Bit), LOW POWER, 72-Pin
B I T
HMS51232M4L
SIMM 5V
Part No.
GENERAL DESCRIPTION
The HMS51232M4L is a static random access memory (SRAM) module containing 524,288 words organized in
a x32-bit configuration. The module consists of four 512K x 8 SRAMs mounted on a 72-pin, single-sided, FR4-
printed circuit board.
The HMS51232M4L also support low data retention voltage for battery back-up operations with low data retention
current. Four chip enable inputs, (/CE_UU1, /CE_UM1, /CE_LM1 and /CE_LL1) are used to enable the module’s
4 bytes independently. Output enable (/OE) and write enable (/WE) can set the memory input and output.
Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW.
Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW.
For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be
powered from a single +5V DC power supply and all inputs and outputs are fully TTL-compatible.
FEATURES
PIN ASSIGNMENT
A18 37
A16 38
Vss 39
A6 40
Vcc 41
A5 42
A4 43
Vcc 44
NC 45
Vss
A3
A2
A1
A0
Vcc
A11
/ OE
A10
Vcc 10
NC 11
1
2
3
4
5
6
7
8
9
Access time : 55, 70ns
High-density 2MByte design
High-reliability, low-power design
Single +5V ±0.5V power supply
Low data retention voltage : 2V(min)
Three state output and TTL-compatible
FR4-PCB design
/ CE_UM1 46
DQ23 47
DQ16 48
DQ17 49
DQ18 50
DQ22 51
DQ21 52
DQ20 53
DQ19 54
Vcc 55
/ CE_LL1 12
DQ7 13
DQ0 14
DQ1 15
DQ2 16
DQ6 17
DQ5 18
DQ4 19
DQ3 20
A15 21
Low profile 72-Pin SIMM
A14 56
A12 57
A7 58
OPTIONS
MARKING
A17 22
Vcc 59
A8 60
/ WE 23
A13 24
Timing
A9 61
Vcc 25
DQ24 62
DQ25 63
DQ26 64
NC 65
DQ8 26
DQ9 27
DQ10 28
NC 29
55ns access
70ns access
Packages
-55
-70
/ CE_UU1 66
DQ31 67
DQ30 68
DQ29 69
DQ28 70
DQ27 71
Vss 72
Vcc 30
/ CE_LM1 31
DQ15 32
DQ14 33
DQ13 34
DQ12 35
DQ11 36
72-pin SIMM
M
72-Pin SIMM
TOP VIEW
1
HANBit Electronics Co.,Ltd.
HANBit
HMS51232M4L
FUNCTIONAL BLOCK DIAGRAM
32
DQ0 - DQ31
19
A0 - A18
A0-18
DQ 0-7
/WE
/OE
U1
/CE
/CE_UU1
A0-18
DQ 8-15
/WE
/OE
U2
/CE
/CE_UM1
A0-18
DQ16-23
/WE
/OE
U3
/CE
/CE_LM1
A0-18
DQ24-31
/WE
/OE
/WE
/OE
U4
/CE
/CE_LL1
TRUTH TABLE
MODE
STANDBY
/OE
/CE
/WE
DQ
POWER
X
H
L
H
L
L
L
X
H
H
L
HIGH-Z
HIGH-Z
Dout
STANDBY
ACTIVE
ACTIVE
ACTIVE
NOT SELECTED
READ
WRITE
X
Din
2
HANBit Electronics Co.,Ltd.
HANBit
HMS51232M4L
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
SYMBOL
VIN,OUT
VCC
RATING
-0.5V to +7.0V
-0.5V to +7.0V
4W
PD
o
o
Storage Temperature
TSTG
-65 C to +150 C
o
o
Operating Temperature
TA
0 C to +70 C
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
o
RECOMMENDED DC OPERATING CONDITIONS
( T =0 to 70 C )
A
PARAMETER
Supply Voltage
SYMBOL
VCC
MIN
4.5V
0
TYP.
MAX
5.5V
5.0V
Ground
VSS
0
-
0
Input High Voltage
Input Low Voltage
VIH
2.2
Vcc+0.5V**
0.8V
VIL
-0.5*
-
*
V (Min.) = -2.0V (Pulse Width 10ns) for I 20 mA
≤ ≤
IL
V (Min.) = Vcc+2.0V (Pulse Width 10ns) for I 20 mA
**
≤
≤
IH
o
o
DC AND OPERATING CHARACTERISTICS (1)(0 C
T
70 C ; Vcc = 5V 0.5V )
≤
≤
±
A
SYMBO
L
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
Input Leakage Current
Output Leakage Current
VIN = Vss to Vcc
ILI
-4
4
A
µ
/CE=VIH or /OE =VIH or /WE=VIL
IL0
-4
4
A
µ
VOUT=Vss to VCC
Output High Voltage
Output Low Voltage
IOH = -4.0mA
IOL = 8.0mA
VOH
VOL
2.4
V
0.4
V
o
* Vcc=5.0V, Temp=25 C
3
HANBit Electronics Co.,Ltd.
HANBit
HMS51232M4L
DC AND OPERATING CHARACTERISTICS (2)
MAX
DESCRIPTION
Power Supply
Current:Operating
TEST CONDITIONS
IIO=0mA,/CE=VIL, VIN=VIL or
VIH, Read
SYMBOL
-55
-70
UNIT
lCC
60
60
mA
/CE=VIH, Other inputs=VIL or VIH
lSB
12
12
mA
Power Supply
Current:Standby
/CE Vcc-0.2V,
inputs=0~Vcc
Other
≥
lSB1
400
400
A
µ
CAPACITANCE
DESCRIPTION
TEST CONDITIONS
VI/O=0V
SYMBOL
CI/O
MAX
UNIT
pF
Input /Output Capacitance
Input Capacitance
32
40
VIN=0V
CIN
pF
*
: Capacitance is sampled and not 100% tested
NOTE
o
o
AC CHARACTERISTICS (0 C
T
70 C ; Vcc = 5V 0.5V, unless otherwise specified)
≤
≤
±
A
TEST CONDITIONS
PARAMETER
Input Pulse Level
VALUE
0.8 to 2.4V
5ns
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
CL=100pF + 1TTL
* See test condition of DC and Operating characteristics
CL*
* Including scope and jig capacitance
4
HANBit Electronics Co.,Ltd.
HANBit
HMS51232M4L
READ CYCLE
-55
-70
PARAMETER
UNIT
MAX
SYMBOL
MIN
MAX
MIN
Read Cycle Time
tRC
tAA
tCO
tOE
55
70
ns
Address Access Time
55
55
25
70
70
35
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to Output
Output Enable to Output
Output Enable to Low-Z Output
Chip Enable to Low-Z Output
Output Disable to High-Z Output
Chip Disable to High-Z Output
Output Hold from Address Change
tOLZ
tLZ
tOHZ
tHZ
5
10
0
5
10
0
20
20
25
25
0
0
tOH
10
10
WRITE CYCLE
-55
-70
PARAMETER
UNIT
SYMBOL
MIN
55
45
0
MAX
MIN
70
60
0
MAX
Write Cycle Time
tWC
tCW
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width
tAW
tWP
tWR
tWHZ
tDW
tDH
45
40
0
60
50
0
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End of Write to Output Low-Z
0
20
0
25
25
0
30
0
tOW
5
5
5
HANBit Electronics Co.,Ltd.
HANBit
HMS51232M4L
TIMING DIAGRAMS
( Address Controlled) ( /CE = /OE = V , /WE = V )
TIMING WAVEFORM OF READ CYCLE
IL
IH
tRC
Address
tAA
tOH
Data out
Previous Data Valid
Data Valid
(/WE = V
)
TIMING WAVEFORM OF READ CYCLE
IH
tRC
Address
tHZ(3,4)
tAA
tCO
/CE
/OE
tLZ(4)
tOHZ
tOE
tOH
tOLZ
High-Z
Data Out
Data Valid
(Read Cycle)
Notes
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH
or VOL levels.
4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device
to device.
6
HANBit Electronics Co.,Ltd.
HANBit
HMS51232M4L
( /WE Controlled )
TIMING WAVEFORM OF WRITE CYCLE
tWC
Address
/OE
tAW
tWR(5)
tCW(3)
/CE
tAS(4)
tWP(2)
/WE
tDW
tDH
High-Z
Data In
Data Valid
tOHZ
tOW
Data Out
High-Z
( /CE Controlled )
TIMING WAVEFORM OF WRITE CYCLE
tWC
Address
/CE
tAW
tWR(5)
tCW(3)
tAS(4)
/WE
tWP(2)
tDW
tDH
Data In
Data Valid
High-Z
Data Out
( Write Cycle)
Notes
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among
/CE going low and /WE going low : A write ends at the earliest transition among /CE going high and/WE going high.
tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of /CE going low to the end of write.
7
HANBit Electronics Co.,Ltd.
HANBit
HMS51232M4L
4. tAS is measured from the address valid to the beginning of wirte.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as/CE, or /WE going high.
FUNCTIONAL DESCRIPTION
/CE
H
/WE
X*
H
/OE
X
MODE
Not Select
Output Disable
Read
I/O PIN
High-Z
High-Z
DOUT
SUPPLY CURRENT
l SB, l SB1
lCC
L
H
L
H
L
lCC
L
L
X
Write
DIN
lCC
Note: X means Don't Care
DATA RETENTION CHARACTERISTICS (TA = 0 to 70
*
)
PARAMETER
VCC for Data Retention
Data Retention Current
SYMBOL
VDR
TEST CONDITION
MIN
MAX
5.5
UNIT
/CE VCC-0.2V
2
-
V
VCC=3.0V, /CE VCC-0.2V
VIN VCC-0.2V or VIN 0.2V
See Data Retention
IDR
50
A
µ
Data Retention Set-up Time
Recovery Time
tSDR
tRDR
0
5
-
-
ns
ns
Wave forms(below)
* L-Version Only
DATA RETENTION WAVEFORM 1 (/ CE Con trolled)
tSDR
tRDR
Data Retention Mode
Vcc
4.5V
2.2V
VDR
/CE
Vss
/CE Vcc- 0.2V
8
HANBit Electronics Co.,Ltd.
HANBit
HMS51232M4L
PACKAGING INFORMATION
SIMM Design
1 0 8 .2 0 m m
3 .1 8 m m
TYP(2 x)
1 6 m m
6 .3 5 m m
7 2
1
2 .0 3 m m
1 .0 2 m m
6 .3 5 m m
1 .2 7 m m
3 .3 4 m m
9 5 .2 5 m m
2 .5 4 m m
MIN
0 .2 5 m m MAX
1 .2 9 ±0 .0 8 m m
Gold : 1 .0 4 ±0 .1 0 m m
1 .2 7
Sold er: 0 .9 1 4 ±0 .1 0 m m
(Solder & Gold Plating Lead)
9
HANBit Electronics Co.,Ltd.
HANBit
HMS51232M4L
ORDERING INFORMATION
1
2
3
4
5
6
7
8
H M S 5 1 2 3 2 M 4 L-1 5
15ns Access Time
HANBit
Component, Low Power
Memory
Modules
SIMM
x32bit
SRAM
512K
1. - Product Line Identifier
HANBit ------------------------------------------------------- H
2. - Memory Modules
3. - SRAM
4. - Depth : 512K
5. - Width : x 32bit
6. - Package Code
SIMM ------------------------------------------------------- M
ZIP
------------------------------------------------------- Z
7. - Number of Memory Components, Low Power -------L
8. - Access time
10 ----------------------------------------------------------- 10ns
12 ----------------------------------------------------------- 12ns
15 ----------------------------------------------------------- 15ns
17 ----------------------------------------------------------- 17ns
20 ----------------------------------------------------------- 20ns
10
HANBit Electronics Co.,Ltd.
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