HSD16M64B8A-10L [HANBIT]
DRAM;
| 型号： | HSD16M64B8A-10L |
| 厂家： | 
HANBIT ELECTRONICS CO.,LTD |
| 描述： | DRAM 动态存储器 |
| 文件： | 总10页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HANBit
HSD16M64B8A
Synchronous DRAM Module 128Mbyte (16Mx64-Bit), SO-DIMM,
4Banks, 4K Ref., 3.3V
Part No. HSD16M64B8A
GENERAL DESCRIPTION
The HSD16M64B8A is a 16M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists
of eight CMOS 4M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 144-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The
HSD16M64B8 is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting into 144-pin edge
connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be
useful for a variety of high bandwidth, high performance memory system applications All module components may be
powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
• Part Identification
HSD16M64B8A-F/10L : 100MHz (CL=3)
HSD16M64B8A-F/10 : 100MHz (CL=2)
HSD16M64B8A-F/12 : 125MHz (CL=3)
HSD16M64B8A-F/13 : 133MHz (CL=3)
F means Auto & Self refresh with Low-Power (3.3V)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• The used device is 4M x 8bit x 4Banks SDRAM
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
- 1 -
HANBit
HSD16M64B8A
PIN ASSIGNMENT
PIN Symbol PIN Symbol PIN
Symbol
PIN
Symbol
PIN Symbol
PIN
Symbol
1
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
2
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
DQ13
DQ14
DQ15
Vss
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
DQ45
DQ46
DQ47
Vss
97
DQ22
DQ23
Vcc
A6
98
DQ54
DQ55
Vcc
3
4
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
5
6
101
103
105
107
109
7
8
A7
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
NC
NC
A8
BA0
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
NC
NC
Vss
A9
Vss
DQ4
DQ5
DQ6
DQ7
Vss
DQ36
DQ37
DQ38
DQ39
Vss
CLK0
Vcc
CKE0
Vcc
BA1
111 A10_AP
A11
/RAS
/WE
/CS0
NC
/CAS
NC
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Vcc
DQM2
DQM3
Vss
Vcc
DQM6
DQM7
Vss
NC
DQM0
DQM1
Vcc
DQM4
DQM5
Vcc
NC
NC
CLK1
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ56
DQ57
DQ58
DQ59
Vcc
Vss
A0
A3
NC
NC
A1
A4
NC
NC
A2
A5
Vcc
Vcc
Vss
Vss
DQ16
DQ17
DQ18
DQ19
Vss
DQ48
DQ49
DQ50
DQ51
Vss
DQ28
DQ29
DQ30
DQ31
Vss
DQ60
DQ61
DQ62
DQ63
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ40
DQ41
DQ42
DQ43
Vcc
DQ20
DQ21
DQ52
DQ53
SDA
SCL
DQ12
DQ44
Vcc
Vcc
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
- 2 -
HANBit
HSD16M64B8A
FUNCTIONAL BLOCK DIAGRAM
DQ0-63
CKE
CAS
CLK
CLKA
DQM0
CKE0
/CA
DQ0-7
U1
/RAS
/CS0
RAS
CE
DQM0
WE
WE
WE
A0-A11
BA0-1
CKE
CAS
CLK
DQ8-15
U2
RAS
CE
DQM1
DQM1
A0-A11
BA0-1
CKE
CAS
CLK
CLKB
DQM2
DQ16-23
U3
RAS
CE
DQM2
BA0-1
A0-A11
CKE
CAS
CLK
DQ24-31
U4
RAS
CE
DQM3
BA0-1
DQM3
WE
WE
WE
WE
WE
A0-A11
CKE
CAS
CLK
CLKC
DQM4
DQ32-39
U5
RAS
CE
DQM4
BA0-1
A0-A11
CKE
CAS
CLK
DQ40-47
U6
RAS
CE
DQM5
BA0-1
DQM5
A0-A11
CLKD
DQM6
CKE
CAS
CLK
DQ48-55
U7
RAS
CE
DQM6
BA0-1
A0-A11
CKE
CAS
CLK
DQ56-63
U8
RAS
CE
DQM7
BA0-1
DQM7
A0-A11
/WE
A0 - A11
BA0-1
Vcc
Vss
Two 0.1uF Capacitors
per each SDRAM
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
- 3 -
HANBit
HSD16M64B8A
PIN FUNCTION DESCRIPTION
PIN
CLK
NAME
System clock
INPUTT FUNCTION
Active on the positive going edge to sample all inputs.
/CE
Chip enable
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
A0 ~ A11
Address
BA0~ BA1 Bank select address
/RAS
/CAS
/WE
Row address strobe
Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7 Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
DQ0 ~ 63
Data input/output
VDD/VSS Power supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
SYMBOL
VIN ,OUT
Vcc
RATING
-1V to 4.6V
-1V to 4.6V
8W
PD
o
o
Storage Temperature
TSTG
-55 C to 150 C
Short Circuit Output Current
IOS
200mA
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
- 4 -
HANBit
HSD16M64B8A
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) )
PARAMETER
Supply Voltage
SYMBOL
Vcc
VIH
MIN
3.0
2.0
-0.3
2.4
-
TYP.
MAX
3.6
UNIT
V
NOTE
3.3
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
3.0
Vcc+0.3
0.8
V
1
VIL
0
-
V
2
VOH
VOL
-
V
IOH = -2mA
IOL = 2mA
3
-
0.4
V
Input leakage current
I LI
-10
-
10
uA
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.
£
2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V £ VIN £ VDDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
DESCRIPTION
SYMBOL
CCLK
MIN
2.5
2.5
2.5
4.0
MAX
4.0
UNITS
Clock
pF
pF
pF
pF
/RAS, /CAS,/WE,/CS, CKE, DQM
Address
CIN
5.0
CADD
5.0
DQ (DQ0 ~ DQ7)
COUT
6.5
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
VERSION
TEST
NOT
E
PARAMETER
SYMBOL
UNIT
-
CONDITION
-12
-10
10L
13
Burst length = 1
Operating current
(One bank active)
12
0
ICC1
tRC ³ tRC(min)
120 110 110
mA
1
IO = 0mA
CKE £ VIL(max)
tCC=10ns
Precharge standby current ICC2
P
1
1
mA
mA
in
CKE & CLK £ VIL(max)
tCC=¥
power-down mode
ICC2PS
CKE ³ VIH(min)
CS* ³ VIH(min), tCC=10ns
Input signals are changed
one time during 20ns
Precharge standby current
in
mA
ICC2N
20
non power-down mode
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
- 5 -
HANBit
HSD16M64B8A
CKE ³ VIH(min)
ICC2NS
CLK £ VIL(max), tCC=¥
Input signals are stable
CKE £ VIL(max), tCC=10ns
CKE&CLK £ VIL(max)
tCC=¥
7
ICC3P
5
5
Active standby current in
power-down mode
mA
ICC3PS
CKE³ VIH(min),
CS*³ VIH(min), tCC=10ns
Input signals are changed
one time during 20ns
CKE³ VIH(min)
ICC3
N
30
20
Active standby current in
non power-down mode
(One bank active)
mA
ICC3NS
CLK £VIL(max), tCC=¥
Input signals are stable
IO = 0 mA
Operating current
(Burst mode)
Page burst
15
0
ICC4
145 125 125
220 210 210
mA
mA
1
2
4Banks Activated
tCCD = 2CLKs
22
0
Refresh current
ICC5
tRC ³ tRC(min)
1.5
mA
mA
Self refresh current
ICC6
CKE £ 0.2V
800
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
AC OPERATING TEST CONDITIONS
(vcc = 3.3V ± 0.3V, TA = 0 to 70°C)
PARAMETER
Value
UNIT
AC Input levels (Vih/Vil)
2.4/0.4
1.4
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
- 6 -
HANBit
HSD16M64B8A
+3.3V
V =1.4V
tt
1200W
50pF*
50W
DOUT
DOUT
Z0=50
W
870W
50pF
V
V
(DC) = 2.4V, I = -2mA
OH
OH
(DC) = 0.4V, I = 2mA
OL
OL
(Fig. 2) AC output load circuit
(Fig. 1) DC output load
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
SYMBOL
UNIT
NOTE
-13
15
20
20
45
-12
16
20
20
48
-10
20
20
20
50
-10L
20
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRP(min)
ns
ns
ns
ns
1
1
1
1
20
Row precharge time
tRP(min)
20
tRAS(min)
tRAS(max)
50
Row active time
100
ns
Row cycle time
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
65
68
70
2
70
ns
CLK
-
1
2
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
2 CLK + 20 ns
1
1
1
2
CLK
CLK
CLK
2
2
3
Col. address to col. address delay
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
-
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -8/H/L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
- 7 -
HANBit
HSD16M64B8A
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-13
MAX MIN
-12
MAX MIN
-10
MAX MIN
-10L
PARAMETER
SYMBOL
UNIT
NOTE
MIN
MAX
CLK cycle
CAS
7.5
8
-
10
10
10
12
time
latency=3
CAS
tCC
1000
1000
1000
1000
ns
1
1,2
2
-
latency=2
CAS
CLK to valid
output delay
5.4
-
6
-
6
6
6
7
latency=3
CAS
tSAC
ns
ns
latency=2
CAS
Output data
hold time
2.7
-
3
-
3
3
3
3
latency=3
CAS
tOH
latency=2
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
3
3
2
1
1
3
3
2
1
1
3
3
2
1
1
ns
ns
ns
ns
ns
3
3
3
3
3
tSS
tSH
tSLZ
Input hold time
CLK to output in Low-Z
CLK to output CAS
5.4
-
6
-
6
6
6
7
ns
ns
2
in Hi-Z
latency=3
tSHZ
CAS
latency=2
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered
ie., [(tr + tf)/2-1]ns should be added to the parameter.
SIMPLIFIED TRUTH TABLE
/R
A
S
/C
A
S
D
Q
M
CKE
CKE
n
/C
S
/W
E
BA
0,1
A10/
AP
A11
A9~A0
n-1
COMMAND
NOTE
Register
Refresh
Mode register set
Auto refresh
H
H
X
H
L
L
L
L
L
L
X
OP code
1,2
3
L
L
H
X
X
X
Entry
3
Self
refres
h
L
H
L
H
X
L
H
X
H
X
3
Exit
L
H
X
X
X
3
Bank active & row addr.
H
H
H
V
Row address
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
- 8 -
HANBit
HSD16M64B8A
Auto
precharge
precharge
Read &
column
address
L
Column
Address
(A0 ~ A9)
4
disable
Auto
H
H
X
X
L
L
H
H
L
L
H
L
X
X
V
V
H
4,5
disable
Column
Address
(A0 ~ A9)
Auto
precharge
precharge
Write &
column
address
L
4
disable
Auto
H
4,5
6
disable
Burst Stop
H
H
X
X
L
L
L
L
H
H
L
L
X
X
X
Precharg Bank selection
V
X
L
X
e
All banks
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock suspend or
active power down
X
X
X
H
L
Entry
H
Precharge power
down mode
H
L
Exit
L
H
X
X
V
X
DQM
H
H
X
X
X
7
H
L
X
H
X
X
H
No operation command
H
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
TIMING DIAGRAMS
Please refer to attached timing diagram chart (II)
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
- 9 -
HANBit
HSD16M64B8A
PACKAGING INFORMATION
Unit :
Inch [mm]
PCB Thickness: 1.0mm (10.t - 1.1t)
Immersion Gold PCB Pattern
ORDERING INFORMATION
( F MEANS AUTO & SELF REFRESH WITH LOW-POWER (3.3V))
Part Number
Density
Org.
Package
Ref.
Vcc
MODE
MAX.frq
144 Pin-
SODIMM
144 Pin-
SODIMM
144 Pin-
SODIMM
144 Pin-
SODIMM
144 Pin-
SODIMM
144 Pin-
SODIMM
144 Pin-
SODIMM
144 Pin-
SODIMM
CL3
133MHz
CL3
HMD16M64B8A-13
HMD16M64B8A-12
HMD16M64B8A-10L
HMD16M64B8A-10
HMD16M64B8A-F13
HMD16M64B8A-F12
HMD16M64B8A-F10L
HMD16M64B8A-F10
128MByte 16M x 64
128MByte 16M x 64
128MByte 16M x 64
128MByte 16M x 64
128MByte 16M x 64
128MByte 16M x 64
128MByte 16M x 64
128MByte 16M x 64
4K
4K
4K
4K
4K
4K
4K
4K
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
125MHz
CL3
100MHz
CL2
100MHz
CL3
133MHz
CL3
125MHz
CL3
100MHz
CL2
100MHz
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
- 10 -
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