CD4050BE [HARRIS]
CMOS Hex Buffer/Converters; CMOS六缓冲器/转换器
| 型号： | CD4050BE |
| 厂家： | 
HARRIS CORPORATION |
| 描述： | CMOS Hex Buffer/Converters |
| 文件： | 总10页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4049UB, CD4050B
Semiconductor
August 1998
File Number 926.2
CMOS Hex Buffer/Converters
Features
• CD4049UB Inverting
• CD4050B Non-Inverting
The Harris CD4049UB and CD4050B are inverting and
non-inverting hex buffers, respectively, and feature logic-
level conversion using only one supply voltage (V ). The
CC
• High Sink Current for Driving 2 TTL Loads
• High-To-Low Level Logic Conversion
input-signal high level (V ) can exceed the V
IH
supply
CC
[ /Title
(CD40
49UB,
voltage when these devices are used for logic-level
conversions. These devices are intended for use as CMOS
to DTL/TTL converters and can drive directly two DTL/TTL
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package
CD405 loads. (V
= 5V, V ≤ 0.4V, and I
OL
≥ 3.3mA.)
OL
CC
o
Temperature Range; 100nA at 18V and 25 C
0B)
/Sub-
ject
(CMO
S Hex
Buffer/
Con-
The CD4049UB and CD4050B are designated as
replacements for CD4009UB and CD4010B, respectively.
Because the CD4049UB and CD4050B require only one
power supply, they are preferred over the CD4009UB and
CD4010B and should be used in place of the CD4009UB
and CD4010B in all inverter, current driver, or logic-level
conversion applications. In these applications the
• 5V, 10V and 15V Parametric Ratings
Applications
• CMOS to DTL/TTL Hex Converter
• CMOS Current “Sink” or “Source” Driver
• CMOS High-To-Low Logic Level Converter
CD4049UB and CD4050B are pin compatible with the
CD4009UB and CD4010B respectively, and can be
verters)
/Autho substituted for these devices in existing as well as in new
Ordering Information
designs. Terminal No. 16 is not connected internally on the
r ()
/Key-
words
(Harris
TEMP.
PKG.
NO.
CD4049UB or CD4050B, therefore, connection to this
terminal is of no consequence to circuit operation. For
applications not requiring high sink-current or voltage
conversion, the CD4069UB Hex Inverter is recommended.
o
PART NUMBER RANGE ( C)
PACKAGE
-55 to 125 16 Ld PDIP
-55 to 125 16 Ld PDIP
CD4049UBE
CD4050BE
CD4049UBF
CD4050BF
CD4050BM
E16.3
E16.3
F16.3
F16.3
M16.3
Semi-
con-
ductor,
CD400
0,
-55 to 125 16 Ld CERDIP
-55 to 125 16 Ld CERDIP
-55 to 125 16 Ld SOIC
NOTE: Wafer and die for this part number is available which meets
all electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
metal
gate,
CMOS
Pinouts
CD4049UB (PDIP, CERDIP)
CD4050B (PDIP, CERDIP, SOIC)
TOP VIEW
TOP VIEW
V
1
2
3
4
5
6
7
8
16 NC
15 L = F
14 F
V
1
2
3
4
5
6
7
8
16 NC
15 L = F
14 F
CC
CC
G = A
A
G = A
A
H = B
B
13 NC
12 K = E
11 E
H = B
B
13 NC
12 K = E
11 E
I = C
C
I = C
C
10 J = D
10 J = D
9
D
9 D
V
V
SS
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
1
CD4049UB, CD4050B
Functional Block Diagrams
CD4049UB
CD4050B
3
5
2
3
2
A
B
C
D
E
F
G = A
H = B
I = C
A
B
C
D
E
F
G = A
H = B
I = C
4
5
7
4
7
6
6
9
10
12
15
9
10
12
15
J = D
K = E
L = F
J = D
K = E
L = F
11
14
11
14
1
1
V
V
V
V
CC
SS
CC
SS
8
8
NC = 13
NC = 16
NC = 13
NC = 16
Schematic Diagrams
V
CC
V
CC
P
N
P
N
P
N
R
OUT
R
IN
IN
OUT
V
SS
V
SS
FIGURE 1A. SCHEMATIC DIAGRAM OF CD4049UB, 1 OF 6
IDENTICAL UNITS
FIGURE 1B. SCHEMATIC DIAGRAM OF CD4050B, 1 OF 6
IDENTICAL UNITS
2
CD4049UB, CD4050B
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . -0.5V to 20V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Resistance (Typical, Note 1)
PDIP Package . . . . . . . . . . . . . . . . . . .
CERDIP Package. . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
JA
JC
90
130
100
N/A
55
N/A
DD
o
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265 C
Operating Conditions
o
o
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
o
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
o
LIMITS AT INDICATED TEMPERATURE ( C)
TEST CONDITIONS
25
V
V
IN
O
PARAMETER
(V)
(V)
0,5
0,10
0,15
0,20
0,5
0,5
0,10
0,15
0,5
0,5
0,10
0,15
0,5
0,10
0,15
0,5
0,10
0,15
-
V
(V)
-55
1
-40
1
85
30
125
30
MIN
TYP
0.02
0.02
0.02
0.04
5.2
6.4
16
48
-1.2
-3.9
-3.0
-8.0
0
MAX
UNITS
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
V
CC
Quiescent Device Current
-
5
-
-
1
I
(Max)
DD
-
10
15
20
4.5
5
2
2
60
60
2
-
4
4
120
600
2.1
120
600
1.8
-
4
-
20
20
-
20
Output Low (Sink) Current
(Min)
0.4
0.4
0.5
1.5
4.6
2.5
9.5
13.5
-
3.3
4
3.1
3.8
9.6
25
2.6
3.2
8
-
I
OL
2.9
2.4
-
10
15
5
10
6.6
5.6
-
26
20
18
24
-0.65
-2.1
-1.65
-4.3
-
-
Output High (Source) Current
(Min)
-0.81
-2.6
-2.0
-5.2
0.05
0.05
0.05
4.95
9.95
-0.73
-2.4
-1.8
-4.8
0.05
0.05
0.05
4.95
9.95
-0.58
-1.9
-1.35
-3.5
0.05
0.05
0.05
4.95
9.95
-0.48
-1.55
-1.18
-3.1
0.05
0.05
0.05
4.95
9.95
-
I
OH
5
-
10
15
5
-
-
Out Voltage Low Level
(Max)
0.05
V
OL
-
10
5
-
0
0.05
V
-
-
0
0.05
V
Output Voltage High Level
(Min)
-
5
4.95
9.95
5
-
-
V
V
OH
-
10
15
5
10
15
-
V
-
14.95 14.95 14.95 14.95 14.95
-
V
Input Low Voltage, V (Max)
IL
4.5
9
1
2
1
2
1
2
1
2
-
1
V
CD4049UB
-
10
15
5
-
-
2
V
13.5
0.5
1
-
2.5
1.5
3
2.5
1.5
3
2.5
1.5
3
2.5
1.5
3
-
-
2.5
1.5
3
V
Input Low Voltage, V (Max)
IL
-
-
-
V
CD4050B
-
10
15
5
-
-
-
V
1.5
0.5
1
-
4
4
4
4
-
4
V
Input High Voltage, V Min
IH
-
4
4
4
4
4
-
-
V
CD4049UB
-
10
15
8
8
8
8
8
-
-
V
1.5
-
12.5
12.5
12.5
12.5
12.5
-
-
V
3
CD4049UB, CD4050B
DC Electrical Specifications
(Continued)
o
LIMITS AT INDICATED TEMPERATURE ( C)
TEST CONDITIONS
25
V
V
IN
O
PARAMETER
(V)
4.5
9
(V)
V
(V)
-55
3.5
7
-40
3.5
7
85
3.5
7
125
3.5
7
MIN
3.5
7
TYP
MAX
UNITS
CC
Input High Voltage, V Min
IH
-
5
-
-
-
-
V
V
CD4050B
-
-
10
15
18
-
-
13.5
-
11
11
11
±1
11
±1
11
-
V
-5
±10
Input Current, I Max
IN
0,18
±0.1
±0.1
±0.1
µA
o
AC Electrical Specifications T = 25 C, Input t , t = 20ns, C = 50pF, R = 200kΩ
A
r
f
L
L
TEST CONDITIONS
LIMITS (ALL PACKAGES)
PARAMETER
Propagation Delay Time
V
V
TYP
60
32
45
25
45
70
40
45
30
40
32
20
15
15
10
55
22
50
15
50
80
40
30
30
20
15
15
MAX
120
65
UNITS
IN
CC
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Low to High, t
CD4049UB
PLH
10
10
15
15
5
10
5
90
15
5
50
90
Propagation Delay Time
5
140
80
Low to High, t
CD4050B
PLH
10
10
15
15
5
10
5
90
15
5
60
80
Propagation Delay Time
5
65
High to Low, t
CD4049UB
PHL
10
10
15
15
5
10
5
40
30
15
5
30
20
Propagation Delay Time
5
110
55
High to Low, t
CD4050B
PHL
10
10
15
15
5
10
5
100
30
15
5
100
160
80
Transition Time, Low to High, t
Transition Time, High to Low, t
5
TLH
THL
10
15
5
10
15
5
60
60
10
15
-
10
15
-
40
30
Input Capacitance, C
CD4049UB
22.5
IN
Input Capacitance, C
CD4050B
-
-
5
7.5
pF
IN
4
CD4049UB, CD4050B
Typical Performance Curves
o
o
T
= 25 C
T
A
= 25 C
A
SUPPLY VOLTAGE (V ) = 5V
CC
SUPPLY VOLTAGE (V ) = 5V
CC
5
4
3
2
1
5
4
3
MINIMUM
MAXIMUM
MINIMUM
MAXIMUM
2
1
0
1
2
3
4
0
1
2
3
4
V , INPUT VOLTAGE (V)
V , INPUT VOLTAGE (V)
I
I
FIGURE 2. MINIMUM AND MAXIMUM VOLTAGE TRANSFER
CHARACTERISTICS FOR CD4049UB
FIGURE 3. MINIMUM AND MAXIMUM VOLTAGE TRANSFER
CHARACTERISTICS FOR CD4050B
o
o
T
= 25 C
A
T
= 25 C
A
70
60
50
40
30
20
10
70
60
15V
10V
15V
10V
50
40
30
20
10
GATE TO SOURCE VOLTAGE (V ) = 5V
GS
GATE TO SOURCE VOLTAGE (V ) = 5V
GS
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
V
, DRAIN TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
DS
FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN
CHARACTERISTICS
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
V
o
, DRAIN TO SOURCE VOLTAGE (V)
DS
-8
-7
-6
-5
-4
-3
-2
-1
0
-8
-7
-6
-5
-4
-3
-2
-1
0
o
T
= 25 C
T
= 25 C
A
A
-5
-5
GATE TO SOURCE VOLTAGE
= -5V
-10
GATE TO SOURCE VOLTAGE
= -5V
-10
-15
-20
-25
-30
-35
V
GS
V
GS
-15
-10V
-15V
-20
-25
-30
-10V
-15V
-35
FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
5
CD4049UB, CD4050B
Typical Performance Curves (Continued)
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
SUPPLY VOLTAGE
SUPPLY VOLTAGE
o
V
= 10V
CC
V
= 10V
125 C
o
CC
125 C
o
o
T
= -55 C
T
A
= -55 C
A
V
= 5V
V
= 5V
CC
CC
o
-55 C
o
-55 C
o
o
125 C
125 C
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
V , INPUT VOLTAGE (V)
V , INPUT VOLTAGE (V)
I
I
FIGURE 8. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS
AS A FUNCTION OF TEMPERATURE FOR CD4049UB
FIGURE 9. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS
AS A FUNCTION OF TEMPERATURE FOR CD4050B
5
10
o
o
T
= 25 C
T
= 25 C
A
A
5
4
10
10
4
3
2
10
10
15V; 1MHz
15V; 100kHz
10V; 100kHz
15V; 10kHz
10V; 10kHz
15V; 1kHz
3
2
10
10
LOAD CAPACITANCE
= 50pF
10
C
L
(11pF FIXTURE + 39pF EXT)
= 15pF
10
C
L
(11pF FIXTURE + 4pF EXT)
SUPPLY VOLTAGE V
= 5V FREQUENCY (f) = 10kHz
10
CC
2
3
4
5
2
3
4
5
6
7
8
10
10
10
10
10
10
10
10
10
10
10
10
10
f, INPUT FREQUENCY (kHz)
t , t , INPUT RISE AND FALL TIME (ns)
r
f
FIGURE 10. TYPICAL POWER DISSIPATION vs FREQUENCY
CHARACTERISTICS
FIGURE 11. TYPICAL POWER DISSIPATION vs INPUT RISE
AND FALL TIMES PER INVERTER FOR CD4049UB
6
10
o
T
= 25 C
A
5
4
3
2
10
10
10
10
15V; 1MHz
15V; 100kHz
10V; 100kHz
15V; 10kHz
10V; 10kHz
15V; 1kHz
10
1
SUPPLY VOLTAGE V
= 5V FREQUENCY (f) = 10kHz
CC
10
2
3
4
5
6
7
8
10
10
10
10
10
10
10
t , t , INPUT RISE AND FALL TIME (ns)
r
f
FIGURE 12. TYPICAL POWER DISSIPATION vs INPUT RISE
AND FALL TIMES PER INVERTERFOR CD4050B
6
CD4049UB, CD4050B
Test Circuits
V
CC
V
CC
V
CC
INPUTS
INPUTS
OUTPUTS
V
IH
V
SS
+
DVM
-
V
IL
I
DD
V
SS
V
SS
NOTE: Test any one input with other inputs at V
or V
.
CC
SS
FIGURE 13. QUIESCENT DEVICE CURRENT TEST CIRCUIT
FIGURE 14. INPUT VOLTAGE TEST CIRCUIT
CMOS 10V LEVEL TO DTL/TTL 5V LEVEL
V
= 5V
CC
V
CC
COS/MOS
IN
OUTPUT
TO DTL/TTL
INPUTS
OUTPUTS
V
CC
CD4049
INPUTS
I
10V = V
5V = V
IH
OH
V
0 = V
IL
0 = V
OL
SS
V
SS
V
In Terminal - 3, 5, 7, 9, 11, or 14
Out Terminal - 2, 4, 6, 10, 12 or 15
SS
V
V
Terminal - 1
Terminal - 8
NOTE: Measure inputs sequentially, to both V
CC
and V connect
SS
CC
SS
all unused inputs to either V
or V .
CC
SS
FIGURE 16. LOGIC LEVEL CONVERSION APPLICATION
FIGURE 15. INPUT CURRENT TEST CIRCUIT
V
DD
0.1µF
I
500µF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
L
10kHz,
100kHz, 1MHz
C
INCLUDES FIXTURE CAPACITANCE
L
FIGURE 17. DYNAMIC POWER DISSIPATION TEST CIRCUITS
7
CD4049UB, CD4050B
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
D
E
BASE
PLANE
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
A2
A
-C-
-
SEATING
PLANE
B1
C
8, 10
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
5
eC
C
B
D1
E
5
eB
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
e
-
0.430
0.150
-
10.92
3.81
7
B
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in JE-
N
16
16
DEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
8
CD4049UB, CD4050B
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.840
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
21.34
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
16
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
9
CD4049UB, CD4050B
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
10.50
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.3977
0.2914
-
-A-
o
0.4133 10.10
3
h x 45
D
0.2992
7.40
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
16
16
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
10
相关型号：
CD4050BEE4
4000/14000/40000 SERIES, HEX 1-INPUT NON-INVERT GATE, PDIP16, ROHS COMPLIANT, PLASTIC, DIP-16
ROCHESTER
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