CD4051BE [HARRIS]
CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion; CMOS模拟多路复用器/多路解复用器与逻辑电平转换
| 型号： | CD4051BE |
| 厂家： | 
HARRIS CORPORATION |
| 描述： | CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion |
| 文件： | 总15页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4051B, CD4052B, CD4053B
Semiconductor
August 1998
File Number 902.2
CMOS Analog Multiplexers/Demultiplexers
with Logic Level Conversion
Features
• Wide Range of Digital and Analog Signal Levels
- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V
The CD4051B, CD4052B, and CD4053B analog multiplexers
are digitally-controlled analog switches having low ON
impedance and very low OFF leakage current. Control of
- Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20V
P-P
• Low ON Resistance, 125Ω (Typ) Over 15V
Signal Input
P-P
analog signals up to 20V
can be achieved by digital
Range for V -V = 18V
P-P
signal amplitudes of 4.5V to 20V (if V -V
DD EE
= 3V, a
DD SS
• High OFF Resistance, Channel Leakage of ±100pA (Typ)
V
-V of up to 13V can be controlled; for V -V
DD EE
DD DD
of at least 4.5V is
at V -V = 18V
DD EE
level differences above 13V, a V -V
DD DD
• Logic-Level Conversion for Digital Addressing Signals of
required). For example, if V
= +4.5V, V
= 0V, and
DD
DD
= -13.5V, analog signals from -13.5V to +4.5V can be
3V to 20V (V -V = 3V to 20V) to Switch Analog
V
DD SS
DD
Signals to 20V
(V -V = 20V)
P-P DD EE
controlled by digital inputs of 0V to 5V. These multiplexer
circuits dissipate extremely low quiescent power over the
• Matched Switch Characteristics, r
ON
= 5Ω (Typ) for
full V -V
DD DD
and V -V supply-voltage ranges,
DD DD
V
-V = 15V
DD EE
independent of the logic state of the control signals. When
a logic “1” is present at the inhibit input terminal, all
channels are off.
• Very Low Quiescent Power Dissipation Under All Digital-
Control Input and Supply Conditions, 0.2µW (Typ) at
V
-V = V -V = 10V
DD SS DD EE
The CD4051B is a single 8-Channel multiplexer having three
binary control inputs, A, B, and C, and an inhibit input. The
three binary signals select 1 of 8 channels to be turned on,
and connect one of the 8 inputs to the output.
• Binary Address Decoding on Chip
• 5V, 10V and 15V Parametric Ratings
• 10% Tested for Quiescent Current at 20V
The CD4052B is a differential 4-Channel multiplexer having
two binary control inputs, A and B, and an inhibit input. The
two binary input signals select 1 of 4 pairs of channels to be
turned on and connect the analog inputs to the outputs.
• Maximum Input Current of 1µA at 18V Over Full Package
Temperature Range, 100nA at 18V and 25 C
o
• Break-Before-Make Switching Eliminates Channel
Overlap
The CD4053B is a triple 2-Channel multiplexer having three
separate digital control inputs, A, B, and C, and an inhibit
input. Each control input selects one of a pair of channels
which are connected in a single-pole, double-throw
configuration.
Applications
• Analog and Digital Multiplexing and Demultiplexing
• A/D and D/A Conversion
• Signal Gating
When these devices are used as demultiplexers, the
“CHANNEL IN/OUT” terminals are the outputs and the
“COMMON OUT/IN” terminals are the inputs.
Ordering Information
TEMP.
RANGE ( C)
PKG.
NO.
o
PART NUMBER
PACKAGE
CD4051BF, CD4052BF,
CD4053BF
-55 to 125 16 Ld CERDIP F16.3
CD4051BE, CD4052BE,
CD4053BE
-55 to 125 16 Ld PDIP
-55 to 125 16 Ld SOIC
E16.3
CD4051BM, CD4052BM,
CD4053BM
M16.15
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
1
CD4051B, CD4052B, CD4053B
Pinouts
CD4051B (PDIP, CERDIP, SOIC)
TOP VIEW
CD4052B (PDIP, CERDIP)
TOP VIEW
4
6
1
2
3
4
5
6
7
8
16 V
15 2
14 1
13 0
12 3
11 A
10 B
0
2
1
2
3
4
5
6
7
8
16 V
15 2
14 1
DD
Y CHANNELS
IN/OUT
DD
CHANNELS
IN/OUT
X CHANNELS
IN/OUT
COM OUT/IN
7
COMMON “Y” OUT/IN
CHANNELS IN/OUT
3
1
13 COMMON “X” OUT/IN
Y CHANNELS
IN/OUT
CHANNELS
IN/OUT
5
12 0
X CHANNELS
IN/OUT
INH
INH
11 3
10 A
V
V
V
V
EE
SS
EE
SS
9
C
9 B
CD4053B (PDIP, CERDIP)
TOP VIEW
by
bx
cy
1
2
3
4
5
6
7
8
16 V
DD
15 OUT/IN bx OR by
14 OUT/IN ax OR ay
13 ay
IN/OUT
OUT/IN CX OR CY
IN/OUT CX
INH
IN/OUT
12 ax
11 A
10 B
V
V
EE
SS
9
C
Functional Block Diagrams
CD4051B
CHANNEL IN/OUT
7
4
6
2
5
5
4
1
3
2
1
0
V
16
12 15 14 13
DD
TG
TG
TG
TG
TG
TG
TG
TG
11
A †
COMMON
OUT/IN
10
B †
BINARY
TO
1 OF 8
DECODER
WITH
3
LOGIC
LEVEL
CONVERSION
9
C †
INHIBIT
6
INH †
V
7
8
V
EE
SS
2
CD4051B, CD4052B, CD4053B
Functional Block Diagrams (Continued)
CD4052B
X CHANNELS IN/OUT
3
2
1
0
11
15
14
12
TG
TG
TG
TG
TG
TG
TG
TG
V
16
DD
COMMON X
OUT/IN
13
10
9
A †
B †
BINARY
TO
1 OF 4
3
LOGIC
LEVEL
COMMON Y
OUT/IN
DECODER
WITH
CONVERSION
6
INHIBIT
INH †
1
0
5
1
2
2
4
3
8
7
V
V
EE
SS
Y CHANNELS IN/OUT
CD4053B
BINARY TO
1 OF 2
DECODERS
WITH
IN/OUT
by bx
12 15
LOGIC
LEVEL
CONVERSION
V
16
DD
cy
5
cx
1
ay
14
ax
13
INHIBIT
COMMON
OUT/IN
ax OR ay
TG
TG
TG
TG
TG
TG
14
11
A †
COMMON
OUT/IN
bx OR by
15
10
9
B †
C †
COMMON
OUT/IN
cx OR cy
4
6
INH †
V
DD
8
V
V
EE
7
SS
†All inputs protected by standard CMOS protection network
3
CD4051B, CD4052B, CD4053B
TRUTH TABLES
INPUT STATES
INHIBIT
C
B
A
“ON” CHANNEL(S)
CD4051B
0
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
0
0
1
0
2
0
3
0
4
0
5
6
0
0
7
1
None
CD4052B
INHIBIT
B
0
0
1
1
X
A
0
1
0
1
X
0
0x, 0y
1x, 1y
2x, 2y
3x, 3y
None
0
0
0
1
CD4053B
INHIBIT
A OR B OR C
0
0
1
X
ax or bx or cx
ay or by or cy
None
0
1
X = Don’t Care
4
CD4051B, CD4052B, CD4053B
Absolute Maximum Ratings
Supply Voltage (V+ to V-)
Voltages Referenced to V Terminal . . . . . . . . . . . -0.5V to 20V
DC Input Voltage Range . . . . . . . . . . . . . . . . . . -0.5V to V
DD
Thermal Information
o
o
Thermal Resistance (Typical, Note 1)
PDIP Package . . . . . . . . . . . . . . . . . . .
CERDIP Package. . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C
θ
( C/W)
θ
( C/W)
JA
JC
90
115
115
N/A
45
N/A
SS
+0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA
o
o
Operating Conditions
o
o
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265 C
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
o
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, V
= ±5V, A = +1,
SUPPLY
V
R
= 100Ω, Unless Otherwise Specified (Note 3)
L
o
CONDITIONS
LIMITS AT INDICATED TEMPERATURES ( C)
25
PARAMETER
V
(V)
V
(V)
V
(V)
V
(V)
-55
-40
85
125
MIN
TYP
MAX
UNITS
IS
EE
SS
DD
SIGNAL INPUTS (V ) AND OUTPUTS (V
)
IS
OS
Quiescent Device
Current, I Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
5
10
20
100
800
310
200
-
5
10
20
100
850
330
210
-
150
300
600
3000
1200
520
300
-
150
300
600
3000
1300
550
320
-
-
-
-
-
-
-
-
-
-
-
-
0.04
0.04
0.04
0.08
470
180
125
15
5
10
20
100
1050
400
240
-
µA
µA
µA
µA
Ω
DD
-
10
-
-
15
20
5
-
-
Drain to Source ON
Resistance r Max
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ON
10
15
5
Ω
0 ≤ V ≤ V
IS DD
Ω
Change in ON
Resistance (Between
Any Two Channels),
Ω
10
15
18
-
-
-
-
10
-
Ω
∆r
ON
-
-
-
-
5
-
Ω
OFF Channel Leakage
Current: Any Channel
OFF (Max) or ALL
±100 (Note 2) ±1000 (Note 2)
±0.01
±100
(Note 2)
µA
Channels OFF (Common
OUT/IN) (Max)
Capacitance:
-
-5
5-
5
Input, C
-
-
-
-
-
5
-
pF
IS
Output, C
OS
CD4051
CD4052
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
30
18
9
-
-
-
pF
pF
pF
CD4053
Feedthrough
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.2
30
15
10
-
pF
ns
ns
ns
IOS
Propagation Delay Time
(Signal Input to Output
V
R
C
= 200kΩ,
= 50pF,
5
60
30
20
DD
L
L
10
15
t , t = 20ns
r
f
5
CD4051B, CD4052B, CD4053B
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, V
= ±5V, A = +1,
SUPPLY
V
R
= 100Ω, Unless Otherwise Specified (Continued) (Note 3)
L
o
CONDITIONS
LIMITS AT INDICATED TEMPERATURES ( C)
25
PARAMETER
V
(V)
V
C
(V)
V
(V)
V
(V)
-55
-40
85
125
MIN
TYP
MAX
UNITS
IS
EE
SS
DD
CONTROL (ADDRESS OR INHIBIT), V
Input Low Voltage, V
Max
,
V
= V
V
R
= V ,
SS
= 1kΩ to V ,
< 2µA on All
5
1.5
3
1.5
3
1.5
3
1.5
3
-
-
-
-
-
-
-
-
1.5
V
V
IL
IL
DD
EE
through
1kΩ;
V
L
SS
10
3
I
IS
= V
OFF Channels
IH
DD
15
5
4
4
4
4
-
4
V
through
Input High Voltage, V
Min
,
3.5
7
3.5
7
3.5
7
3.5
7
3.5
7
-
V
IH 1kΩ
10
15
18
-
-
V
11
±0.1
11
±0.1
11
±1
11
±1
11
-
V
-5
Input Current, I (Max)
IN
V
= 0, 18
±10
±0.1
µA
IN
Propagation Delay Time:
Address-to-Signal
OUT (Channels ON or
OFF) See Figures 10,
11, 14
t , t = 20ns,
0
0
0
5
10
15
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
450
160
120
225
720
320
240
450
ns
ns
ns
ns
r
f
C
= 50pF,
L
L
0
0
0
R
= 10kΩ
0
-5
Propagation Delay Time:
Inhibit-to-Signal OUT t , t = 20ns,
0
0
0
0
0
0
5
10
15
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
160
120
200
720
320
240
400
ns
ns
ns
ns
r
f
(Channel Turning ON)
See Figure 11
C
R
= 50pF,
= 1kΩ
L
L
0
-10
Propagation Delay Time:
Inhibit-to-Signal OUT t , t = 20ns,
0
0
0
0
0
0
5
10
15
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200
90
70
130
5
450
210
160
300
7.5
ns
ns
ns
ns
pF
r
f
(Channel Turning
OFF) See Figure 15
C
R
= 50pF,
= 10kΩ
L
L
0
-10
Input Capacitance, C
IN
(Any Address or Inhibit
Input)
NOTE:
2. Determined by minimum feasible leakage measurement for automatic testing.
Electrical Specifications
TEST CONDITIONS
LIMITS
PARAMETER
V
(V)
V
(V)
R
(kΩ)
L
TYP
30
UNITS
IS
DD
Cutoff (-3dB) Frequency Chan- 5 (Note 3)
nel ON (Sine Wave Input)
10
1
V
at Common OUT/IN
at Any Channel
CD4053
CD4052
CD4051
MHz
MHz
MHz
MHz
OS
V
EE
= V
,
25
SS
V
20
OS
-----------
20Log
= –3dB
V
IS
V
60
OS
6
CD4051B, CD4052B, CD4053B
Electrical Specifications
TEST CONDITIONS
LIMITS
TYP
0.3
PARAMETER
V
(V)
V
(V)
R (kΩ)
L
UNITS
%
IS
DD
Total Harmonic Distortion, THD 2 (Note 3)
5
10
3 (Note 3)
5 (Note 3)
10
15
0.2
%
0.12
%
V
= V , f = 1kHz Sine Wave
SS IS
%
EE
-40dB Feedthrough Frequency 5 (Note 3)
(All Channels OFF)
10
1
V
at Common OUT/IN
at Any Channel
CD4053
CD4052
CD4051
8
10
12
8
MHz
MHz
MHz
MHz
MHz
MHz
MHz
OS
V
= V
,
EE
SS
V
OS
-----------
20Log
= –40dB
V
IS
V
OS
-40dB Signal Crosstalk
Frequency
5 (Note 3)
V = V
10
1
Between Any 2 Channels
3
,
SS
Between Sections,
CD4052 Only
Measured on Common
6
EE
V
OS
-----------
Measured on Any Chan-
nel
10
20Log
= –40dB
V
IS
Between Any Two
Sections, CD4053
Only
In Pin 2, Out Pin 14
In Pin 15, Out Pin 14
2.5
6
MHz
MHz
Address-or-Inhibit-to-Signal
Crosstalk
-
10
10
(Note 4)
65
65
mV
PEAK
PEAK
V
EE
= 0, V = 0, t , t = 20ns, V
SS
mV
r
f
CC
= V
- V (Square Wave)
DD
SS
NOTES:
V
– V
EE
2
3. Peak-to-Peak voltage symmetrical about
DD
-----------------------------
4. Both ends of channel.
Typical Performance Curves
300
250
200
150
100
50
600
V
- V = 10V
EE
DD
V
- V = 5V
EE
DD
500
400
o
T
= 125 C
A
o
T
= 125 C
A
300
200
100
0
o
T
= 25 C
A
o
T
= 25 C
A
o
T
= -55 C
A
o
T
= -55 C
A
0
-10
-4
-3
-2
-1
0
1
2
3
4
5
-7.5
-5
-2.5
0
2.5
5
7.5
10
V
, INPUT SIGNAL VOLTAGE (V)
V , INPUT SIGNAL VOLTAGE (V)
IS
IS
FIGURE 1. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
FIGURE 2. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
7
CD4051B, CD4052B, CD4053B
Typical Performance Curves (Continued)
600
500
400
300
200
100
0
250
o
T
= 25 C
V
- V = 15V
EE
A
DD
V
- V = 5V
EE
DD
200
150
100
50
o
T
= 125 C
A
o
T
= 25 C
A
o
T
= -55 C
A
10V
15V
0
-10
-7.5
-5
-2.5
V , INPUT SIGNAL VOLTAGE (V)
IS
0
2.5
5
7.5
10
-10
-7.5
-5
-2.5
0
2.5
5
7.5
10
V
, INPUT SIGNAL VOLTAGE (V)
IS
FIGURE 3. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
FIGURE 4. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
5
6
10
o
TEST CIRCUIT
V
V
V
= 5V
= 0V
= -5V
o
T
= 25 C
DD
SS
EE
A
R
= 100kΩ, R = 10kΩ
L
L
V
DD
ALTERNATING “O”
AND “I” PATTERN
= 50pF
1kΩ
B/D
CD4029
4
2
0
500Ω
f
C
T
= 25 C
L
A
4
3
2
10
10
10
100Ω
A B C
V
DD
V
= 15V
DD
1110 9
100Ω
13
14
15
12
1
CD4051
V
= 10V
-2
-4
-6
5
DD
3
2
4
8 7
6
C
V
= 5V
DD
L
100Ω
Ι
C
= 15pF
L
10
2
3
4
5
-6
-4
-2
0
2
4
6
1
10
10
10
10
10
V
, INPUT SIGNAL VOLTAGE (V)
SWITCHING FREQUENCY (kHz)
IS
FIGURE 5. ON CHARACTERISTICS FOR 1 OF 8 CHANNELS
(CD4051B)
FIGURE 6. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4051B)
5
5
o
10
10
10
o
V
= 15V
T
= 25 C
DD
A
T
= 25 C
A
ALTERNATING “O”
AND “I” PATTERN
= 50pF
ALTERNATING “O”
AND “I” PATTERN
V
= 10V
DD
TEST CIRCUIT
C
V
L
C
= 50pF
DD
L
4
3
2
f
4
10
10
CD4029
B/D
A B
TEST CIRCUIT
V
V
DD
f
V
= 15V
DD
DD
9
3
5
4
100Ω
1
C
L
100Ω
10 9
12
3
C
L
10
10
3
5
2
4
13
13
2
1
15
14
100Ω
12
CD4053
14
15
11
V
= 10V
10
11
6
CD4052
DD
V
= 5V
6
7
DD
2
V
= 5V
10
DD
7
8
8
C
= 15pF
L
C
= 15pF
Ι
L
Ι
10
10
2
10
3
4
5
2
3
4
5
1
10
10
10
10
1
10
10
10
10
10
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
FIGURE 7. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4052B)
FIGURE 8. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4053B)
8
CD4051B, CD4052B, CD4053B
Test Circuits and Waveforms
V
= 15V
V
= 7.5V
V
DD
= 5V
V
= 5V
DD
DD
DD
5V
5V
7.5V
16
16
16
16
V
= 0V
V
= 0V
SS
SS
V
= 0V
SS
V
= 0V
= 0V
EE
7
8
7
8
7
8
7
8
V
= -10V
V
= -5V
V
= -7.5V
EE
EE
EE
V
SS
(D)
(C)
(B)
(A)
NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels
are: “0” = V and “1” = V . The analog signal (through the TG) may
SS DD
swing from V to V
.
EE
DD
FIGURE 9. TYPICAL BIAS VOLTAGES
t = 20ns
r
t = 20ns
r
t = 20ns
f
t = 20ns
f
90%
90%
50%
90%
50%
90%
50%
50%
10%
10%
10%
10%
10%
TURN-ON TIME
90%
50%
90%
10%
10%
TURN-OFF TIME
TURN-ON
TIME
TURN-OFF TIME
t
PHZ
FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON
(R = 1kΩ)
FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF
(R = 1kΩ)
L
L
V
V
V
DD
DD
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
I
I
DD
DD
I
DD
CD4053
CD4051
CD4052
FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF
9
CD4051B, CD4052B, CD4053B
Test Circuits and Waveforms (Continued)
V
V
V
DD
DD
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
I
DD
I
I
DD
DD
CD4052
CD4051
CD4053
FIGURE 13. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF
V
DD
V
DD
OUTPUT
OUTPUT
OUTPUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
R
C
L
R
V
C
L
L
DD
L
R
C
L
L
V
V
DD
EE
V
EE
V
V
DD
DD
V
EE
V
V
V
EE
EE
V
V
V
DD
EE
V
V
SS
SS
CLOCK
IN
CLOCK
IN
V
SS
CLOCK
IN
V
SS
SS
SS
V
V
CD4051
V
CD4053
SS
SS
CD4052
SS
FIGURE 14. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT
V
V
DD
DD
OUTPUT
OUTPUT
OUTPUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
V
DD
R
50pF
V
R
50pF
L
L
R
L
50pF
14
13
12
11
10
9
V
EE
EE
V
V
EE
V
V
DD
V
DD
DD
DD
V
V
V
DD
SS
DD
V
SS
CLOCK
IN
V
V
V
V
V
CLOCK
IN
V
V
EE
EE
SS
CLOCK
IN
EE
SS
SS
SS
V
V
V
SS
SS
SS
t
AND t
PLH
t
AND t
PLH
t
AND t
PHL
PHL
PHL PLH
CD4052
CD4051
CD4053
FIGURE 15. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT
V
DD
V
DD
V
DD
µA
1K
V
IH
1
2
3
4
5
6
7
8
16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
1K
1K
15
14
13
12
11
10
9
µA
µA
15
14
13
12
11
10
9
1K
1K
V
V
IH
IH
V
1K
IH
V
IH
V
IL
V
IL
V
V
IL
IL
V
IH
CD4053B
CD4052B
CD4051B
V
IL
V
IL
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 6)
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 2x)
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL by)
FIGURE 16. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)
10
CD4051B, CD4052B, CD4053B
Test Circuits and Waveforms (Continued)
V
DD
V
KEITHLEY
160 DIGITAL
MULTIMETER
DD
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TG
“ON”
10kΩ
1kΩ
RANGE
Y
X
X-Y
PLOTTER
V
SS
H.P.
MOSELEY
7030A
CD4052
Ι
CD4051
CD4053
Ι
FIGURE 17. QUIESCENT DEVICE CURRENT
FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT
CIRCUIT
V
V
DD
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
DD
DD
Ι
Ι
V
V
SS
SS
CD4051
CD4053
CD4052
V
V
SS
SS
NOTE: Measureinputssequentially,
to both V and V connect all
NOTE: Measureinputssequentially,
to both V and V connect all
DD
SS
DD
SS
unused inputs to either V
or V
SS
.
unused inputs to either V
or V .
SS
DD
DD
FIGURE 19. INPUT CURRENT
5V
P-P
CHANNEL
OFF
CHANNEL
ON
RF
VM
COMMON
RF
VM
R
5V
P-P
L
OFF
CHANNEL
1K
R
V
L
DD
CHANNEL
ON
RF
VM
CHANNEL
OFF
6
7
8
R
R
L
L
FIGURE 20. FEEDTHROUGH (ALL TYPES)
FIGURE 21. CROSSTALK BETWEEN ANY TWO CHANNELS
(ALL TYPES)
5V
P-P
CHANNEL IN Y
ON OR OFF
CHANNEL IN X
ON OR OFF
RF
VM
R
R
L
L
FIGURE 22. CROSSTALK BETWEEN DUALS OR TRIPLETS (CD4052B, CD4053B)
11
CD4051B, CD4052B, CD4053B
Test Circuits and Waveforms (Continued)
DIFFERENTIAL
SIGNALS
CD4052
CD4052
COMMUNICATIONS
LINK
DIFF.
AMPLIFIER/
LINE DRIVER
DIFF.
RECEIVER
DIFF.
MULTIPLEXING
DEMULTIPLEXING
FIGURE 23. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052B
Special Considerations
In applications where separate power sources are used to
drive V and the signal inputs, the V current capability
DD
DD
should exceed V /R (R = effective external load). This
DD
provision avoids permanent current flow or clamp action on
the V supply when power is applied or removed from the
L
L
DD
CD4051B, CD4052B or CD4053B.
A
B
C
A
B
CD4051B
CD4051B
CD4051B
C
INH
Q
0
COMMON
OUTPUT
A
A
B
E
D
E
Q
Q
1
2
1/2
CD4556
B
C
INH
A
B
C
INH
FIGURE 24. 24-TO-1 MUX ADDRESSING
12
CD4051B, CD4052B, CD4053B
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1
2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
D
E
BASE
PLANE
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
A2
A
-C-
-
SEATING
PLANE
B1
C
8, 10
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
5
eC
C
B
D1
E
5
eB
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
e
-
0.430
0.150
-
10.92
3.81
7
B
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in JE-
N
16
16
DEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
13
CD4051B, CD4052B, CD4053B
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.840
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
21.34
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
16
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
14
CD4051B, CD4052B, CD4053B
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
0.0688
0.0098
0.020
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
1.75
0.25
0.51
0.25
10.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
-
1
2
3
L
-
SEATING PLANE
A
9
-A-
0.0075
0.3859
0.1497
0.0098
0.3937
0.1574
-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
16
16
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
15
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