CD74HCT393E [HARRIS]
High Speed CMOS Logic Dual 4 -Stage Binary Counter; 高速CMOS逻辑双路4 -stage二进制计数器
| 型号： | CD74HCT393E |
| 厂家： | 
HARRIS CORPORATION |
| 描述： | High Speed CMOS Logic Dual 4 -Stage Binary Counter |
| 文件： | 总7页 (文件大小：35K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC393,
CD74HCT393
Semiconductor
High Speed CMOS Logic
September 1997
Dual 4 -Stage Binary Counter
Features
Description
• Fully Static Operation
• Buffered Inputs
• Common Reset
The Harris CD74HC393 and CD74HCT393 are 4-stage
ripple-carry binary counters. Al counter stages are master-
slave flip-flops. The state of the stage advances one count
on the negative transition of each clock pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
• Negative-Edge Clocking
• Typical f
MAX
= 60 MHz at V = 5V, C = 15pF,
CC L
o
Ordering Information
T = 25 C
A
• Fanout (Over Temperature Range)
PKG.
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
NO.
E14.3
E14.3
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
CD74HC393E
CD74HCT393E
CD74HC393M
CD74HCT393M
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
14 Ld PDIP
14 Ld PDIP
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
14 Ld SOIC M14.15
14 Ld SOIC M14.15
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30%of V
IL IH CC
at
2. Wafer or die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or
Harris customer service for ordering information.
V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Pinout
CD74HC393, CD74HCT393
(PDIP, SOIC)
TOP VIEW
1CP
1MR
1Q0
1Q1
1Q2
1Q3
GND
1
2
3
4
5
6
7
14 V
CC
13 2CP
12 2MR
11 2Q0
10 2Q1
9
8
2Q2
2Q3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1653.1
Copyright © Harris Corporation 1997
1
CD74HC393, CD74HCT393
Functional Diagram
3
1Q
1Q
1Q
1Q
0
1
2
3
1
2
4
5
6
1CP
1MR
BINARY
COUNTER
11
10
9
2Q
2Q
2Q
2Q
0
1
2
3
13
12
2CP
2MR
BINARY
COUNTER
8
GND = 7
= 14
V
CC
TRUTH TABLE
OUTPUTS
CP COUNT
Q
Q
Q
Q
3
0
1
2
0
1
L
L
L
L
H
L
L
H
H
L
L
L
L
L
2
3
H
L
L
L
4
H
H
H
H
L
L
5
H
L
L
L
6
H
H
L
L
7
H
L
L
8
H
H
H
H
H
H
H
H
9
H
L
L
L
10
11
12
13
14
15
H
H
L
L
H
L
L
H
H
H
H
H
L
L
H
H
H
CP COUNT
MR
L
OUTPUT
No Change
Count
↑
↓
L
X
H
L L L L
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
2
CD74HC393, CD74HCT393
Logic Diagram
Q
Q
Q
Q
Q
Q
Q
Q
Φ
Φ
Φ
Φ
Φ
Φ
Φ
Φ
1(13)
CP
R
R
R
R
2(12)
MR
3(11)
4(10)
5(9)
6(8)
Q
Q
Q
Q
3
0
1
2
3
CD74HC393, CD74HCT393
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
175
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IL
-0.02
2
1.9
1.9
1.9
OH
IH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
IH
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
4
CD74HC393, CD74HCT393
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE: For dual-supply systems theorectical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
nCP
nMR
0.4
1
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
TYP
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Maximum Clock
Frequency
f
MAX
2
6
30
35
80
16
14
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
24
28
100
20
17
5
-
-
-
-
-
-
-
-
-
4
20
24
120
24
20
5
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5
6
2
Clock Pulse Width
t
W
4.5
6
Reset Recovery Time
t
REC
2
4.5
6
5
5
5
5
5
5
5
CD74HC393, CD74HCT393
Prerequisite for Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V)
MIN
80
TYP
MAX
MIN
100
20
MAX
MIN
120
24
MAX
UNITS
ns
CC
Reset Pulse Width
t
2
-
-
-
-
-
-
-
-
-
-
-
-
W
4.5
16
ns
6
14
17
20
ns
HCT TYPES
Maximum Clock
Frequency
f
t
4.5
27
-
-
22
-
18
-
MHz
MAX
Clock Pulse Width
Reset Recovery Time
Reset Pulse Width
t
4.5
4.5
4.5
19
5
-
-
-
-
-
-
24
5
-
-
-
29
5
-
-
-
ns
ns
ns
W
REC
t
16
20
24
W
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
(V)
PARAMETER
HC TYPES
SYMBOL CONDITIONS
MIN TYP MAX
MIN
MAX
MIN
MAX UNITS
Propagation Delay Time
(Figure 1)
t
t
C = 50pF
2
-
-
45
-
55
-
70
ns
PLH,
L
PHL
Q to Q + 1
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
-
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
n
n
C =15pF
L
C = 50pF
6
8
9
12
225
59
-
L
nCP to nQ
t
t
C = 50pF
2
-
150
30
-
190
38
-
0
PLH,
L
PHL
4.5
5
-
C =15pF
12
-
L
C = 50pF
6
26
190
38
33
240
48
41
285
57
48
135
27
-
33
245
49
42
300
60
51
355
71
60
170
34
-
50
295
59
50
360
72
61
430
86
73
205
41
-
L
nCP to nQ
nCP to nQ
nCP to nQ
t
t
t
t
C = 50pF
2
-
1
2
3
PLH,
L
t
PHL
4.5
6
-
-
C = 50pF
2
-
PLH,
L
t
PHL
4.5
6
-
-
C = 50pF
2
-
PLH,
L
t
PHL
4.5
6
-
-
-
-
-
-
-
-
-
-
-
-
MR to Q
C = 50pF
2
-
n
PLH,
L
t
PHL
4.5
5
-
C =15pF
11
-
L
C = 50pF
6
23
75
15
13
10
-
29
95
19
16
10
-
35
110
22
19
10
-
L
Output Transition Time
(Figure 1)
t
, t
C = 50pF
2
-
TLH THL
L
4.5
6
-
-
Input Capacitance
C
C = 50pF
-
-
IN
L
Power Dissipation Capacitance
(Notes 4, 5)
C
C =15pF
5
20
PD
L
6
CD74HC393, CD74HCT393
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
HCT TYPES
MIN TYP MAX
MIN
MAX
MIN
MAX UNITS
Propagation Delay Time
(Figure 1)
t
t
C = 50pF
4.5
-
-
12
-
15
-
18
ns
PLH,
L
PHL
Q to Q + 1
C =15pF
5
-
-
-
-
4
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
n
n
L
nCP to nQ
t
t
C = 50pF
4.5
5
32
-
40
-
48
-
0
PLH,
L
PHL
C =15pF
13
-
L
nCP to nQ
nCP to nQ
nCP to nQ
t
t
t
t
C = 50pF
4.5
44
55
66
1
2
3
PLH,
L
t
PHL
C = 50pF
4.5
4.5
-
-
-
-
50
62
-
-
63
78
-
-
75
93
ns
ns
PLH,
L
t
PHL
C = 50pF
PLH,
L
t
PHL
MR to Q
C = 50pF
4.5
5
-
-
-
-
-
-
13
-
32
-
-
-
-
-
-
40
-
-
-
-
-
-
48
-
ns
ns
ns
pF
pF
n
PLH,
L
t
PHL
C =15pF
L
Output Transition
Input Capacitance
t
, t
C = 50pF
4.5
-
15
10
-
19
10
-
22
10
-
TLH THL
L
C
C =15pF
-
IN
L
Power Dissipation Capacitance
(Notes 4, 5)
C
C =15pF
5
21
PD
L
NOTES:
4. C
is used to determine the dynamic power consumption, per stage.
2
PD
5. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
f
t = 6ns
t = 6ns
t = 6ns
r
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
7
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