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CD74HCT4094 [HARRIS]

High Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State; 高速CMOS逻辑8级移位和存储总线寄存器，三态
CD74HCT4094
型号： CD74HCT4094
厂家： HARRIS CORPORATION    HARRIS CORPORATION
描述：

High Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State
高速CMOS逻辑8级移位和存储总线寄存器，三态

存储
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CD74HC4094,  
CD74HCT4094  
Semiconductor  
High Speed CMOS Logic  
November 1997  
8-Stage Shift and Store Bus Register, Three-State  
Features  
Description  
• Buffered Inputs  
The Harris CD74HC4094 and CD74HCT4094 are 8-stage  
serial shift registers having a storage latch associated with  
• Separate Serial Outputs Synchronous to Both  
Positive and Negative Clock Edges For Cascading  
[ /Title  
(CD74H  
C4094,  
CD74H  
CT4094  
)
each stage for strobing data from the serial input to parallel  
buffered three-state outputs. The parallel outputs may be  
connected directly to common bus lines. Data is shifted on  
positive clock transitions. The data in each shift register  
stage is transferred to the storage register when the Strobe  
input is high. Data in the storage register appears at the  
outputs whenever the Output-Enable signal is high.  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
/Sub-  
ject  
Two serial outputs are available for cascading a number of  
these devices. Data is available at the QS serial output  
1
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
terminal on positive clock edges to allow for high-speed  
operation in cascaded system in which the clock rise time is  
(High  
Speed  
CMOS  
Logic 8-  
fast. The same serial information, available at the QS  
terminal on the next negative clock edge, provides a means  
for cascading these devices when the clock rise time is slow.  
2
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
Ordering Information  
• HCT Types  
PKG.  
- 4.5V to 5.5V Operation  
o
PART NUMBER TEMP. RANGE ( C) PACKAGE  
NO.  
E16.3  
E16.3  
- Direct LSTTL Input Logic Compatibility,  
CD74HC4094E  
CD74HCT4094E  
CD74HC4094M  
CD74HCT4094M  
NOTES:  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
16 Ld PDIP  
16 Ld PDIP  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
16 Ld SOIC M16.15  
16 Ld SOIC M16.15  
Pinout  
CD74HC4094, CD74HCT4094  
(PDIP, SOIC)  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
TOP VIEW  
2. Wafer or die for this part number is available which meets all elec-  
trical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
STROBE  
DATA  
CP  
1
2
3
4
5
6
7
8
16 V  
CC  
15 OE  
14 Q  
13 Q  
12 Q  
11 Q  
4
5
6
7
Q
Q
Q
Q
0
1
2
3
10 QS  
2
9
QS  
GND  
1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1779.1  
Copyright © Harris Corporation 1997  
1
CD74HC4094, CD74HCT4094  
Functional Diagram  
2
3
9
DATA  
CP  
8-STAGE  
SHIFT  
REGISTER  
QS  
QS  
1
10  
2
8-BIT  
STORAGE  
REGISTER  
1
STROBE  
4
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
6
7
5
6
7
THREE-  
STATE  
OUTPUT  
15  
14  
13  
12  
11  
OE  
GND = 8  
= 16  
V
CC  
TRUTH TABLE  
PARALLEL OUTPUTS  
INPUTS  
SERIAL OUTPUTS  
CP  
↑
OE  
L
STR  
X
D
X
X
X
L
Q
Q
QS (NOTE 4)  
QS  
2
0
n
1
Z
Z
Q’6  
NC  
Q’6  
Q’6  
Q’6  
NC  
NC  
↓
L
X
Z
NC  
L
Z
Q
7
↑
H
H
H
H
L
NC  
NC  
NC  
NC  
↑
H
Q
-1  
n
n
↑
H
H
H
H
Q
-1  
↓
H
NC  
NC  
Q
7
NOTES:  
3. H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, NC = No charge, Z = High Impedance Off-state,  
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.  
4. At the positive clock edge the information in the seventh register stage is transferred to the 8th register stage and QS output.  
1
2
CD74HC4094, CD74HCT4094  
Logic Diagram  
3
CD74HC4094, CD74HCT4094  
Absolute Maximum Ratings  
Thermal Information  
o
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 5)  
θ
( C/W)  
CC  
DC Input Diode Current, I  
JA  
IK  
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
90  
For V < -0.5V or V > V  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
OK  
For V < -0.5V or V > V  
I
I
CC  
160  
o
DC Output Diode Current, I  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C  
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
o
DC Output Source or Sink Current per Output Pin, I  
O
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
(SOIC - Lead Tips Only)  
DC V  
or Ground Current, I  
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA  
CC  
CC  
Operating Conditions  
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
5. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
TYP  
-40 C TO 85 C -55 C TO 125 C  
V
(V)  
CC  
PARAMETER  
HC TYPES  
SYMBOL  
V (V)  
I
I
(mA)  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
O
High Level Input  
Voltage  
V
-
-
-
2
4.5  
6
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
3.15  
-
-
3.15  
-
-
3.15  
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
2
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IL  
-0.02  
2
1.9  
1.9  
1.9  
OH  
IH  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IL  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
IH  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
8
-
80  
-
160  
µA  
CC  
CC  
4
CD74HC4094, CD74HCT4094  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
HCT TYPES  
SYMBOL  
V (V)  
I
I
(mA)  
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
O
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
CMOS Loads  
V
V
V
or V  
-0.02  
4.5  
4.5  
4.5  
4.5  
4.4  
4.4  
4.4  
OH  
IH  
IH  
IL  
IL  
High Level Output  
Voltage  
TTL Loads  
-4  
3.98  
-
-
-
-
3.84  
-
3.7  
-
V
V
V
Low Level Output  
Voltage  
CMOS Loads  
V
or V  
0.02  
4
-
-
0.1  
0.26  
-
-
0.1  
0.33  
-
-
0.1  
0.4  
OL  
Low Level Output  
Voltage  
TTL Loads  
Input Leakage  
Current  
I
V
and  
0
0
-
5.5  
5.5  
-
-
-
-
-
±0.1  
8
-
-
-
±1  
80  
-
-
-
±1  
µA  
µA  
µA  
I
CC  
GND  
Quiescent Device  
Current  
I
V
or  
160  
490  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
∆I  
CC  
(Note)  
V
4.5 to  
5.5  
100  
360  
450  
CC  
-2.1  
NOTE: For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
INPUT  
UNIT LOADS  
D
CP, OE  
0.4  
1.5  
STR  
1.0  
NOTE: Unit Load is ∆I  
360µA max at 25 C.  
limit specified in DC Electrical Table, e.g.,  
CC  
o
Prerequisite for Switching Specifications  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
CHARACTERISTIC  
HC TYPES  
SYMBOL  
V
(V)  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
CC  
CP Pulse Width  
t
2
80  
16  
14  
80  
16  
14  
-
-
-
-
-
-
100  
20  
-
-
-
-
-
-
120  
24  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
W
4.5  
6
2
17  
20  
STR Pulse Width  
t
100  
20  
120  
24  
WH  
4.5  
6
17  
20  
5
CD74HC4094, CD74HCT4094  
Prerequisite for Switching Specifications (Continued)  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
CHARACTERISTIC  
Data Set-up Time  
SYMBOL  
t
V
(V)  
MIN  
50  
10  
9
MAX  
MIN  
65  
13  
11  
3
MAX  
MIN  
75  
15  
13  
3
MAX  
UNITS  
ns  
CC  
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SU  
4.5  
ns  
6
2
ns  
Data Hold Time  
t
3
ns  
H
4.5  
6
3
3
3
ns  
3
3
3
ns  
STR Set-up Time  
STR Hold Time  
t
SU  
2
100  
20  
17  
0
125  
25  
21  
0
150  
30  
26  
0
ns  
4.5  
6
ns  
ns  
t
2
ns  
H
4.5  
6
0
0
0
ns  
0
0
0
ns  
Maximum CP Frequency  
f
CL (MAX)  
2
6
5
4
MHz  
MHz  
MHz  
4.5  
6
30  
35  
24  
28  
20  
24  
HCT TYPES  
CP Pulse Width  
STR Pulse Width  
Data Set-up Time  
Data Hold Time  
STR Set-up Time  
STR Hold Time  
t
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
16  
16  
10  
4
-
-
-
-
-
-
-
20  
20  
13  
4
-
-
-
-
-
-
-
24  
24  
15  
4
-
-
-
-
-
-
-
ns  
ns  
W
t
WH  
t
ns  
SU  
t
ns  
H
t
20  
0
25  
0
30  
0
ns  
SU  
t
ns  
H
Maximum CP Frequency  
f
CL (MAX)  
30  
24  
20  
MHz  
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
MIN TYP MAX  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
(V)  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS  
MIN  
MAX  
MIN  
MAX UNITS  
Propagation Delay Time  
(Figure 1)  
t
t
C = 50pF  
2
-
-
150  
-
190  
-
225  
ns  
PLH,  
L
PHL  
CP to QS  
4.5  
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12  
-
30  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
38  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
45  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1
C =15pF  
L
C = 50pF  
6
26  
135  
27  
-
33  
170  
34  
-
38  
205  
41  
-
L
CP to QS  
t
t
t
C = 50pF  
2
-
2
PLH,  
L
t
PHL  
4.5  
5
-
C =15pF  
11  
-
L
C = 50pF  
6
23  
195  
39  
-
29  
245  
49  
-
35  
295  
59  
-
L
CP to Q  
C = 50pF  
2
-
n
PLH,  
L
t
PHL  
4.5  
5
-
16  
-
6
33  
180  
36  
31  
42  
225  
45  
38  
50  
270  
54  
46  
STR to Q  
C = 50pF  
2
-
n
PLH,  
L
t
PHL  
4.5  
6
-
-
6
CD74HC4094, CD74HCT4094  
Switching Specifications Input t , t = 6ns (Continued)  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
SYMBOL CONDITIONS  
V
CC  
(V)  
PARAMETER  
Output Enable to Q  
MIN TYP MAX  
MIN  
MAX  
220  
44  
37  
155  
31  
26  
95  
19  
16  
-
MIN  
MAX UNITS  
t
t
t
t
t
C = 50pF  
2
4.5  
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
175  
35  
30  
125  
25  
21  
75  
15  
13  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
265  
53  
45  
190  
38  
32  
110  
22  
19  
-
ns  
ns  
n
PZH, PZL  
L
-
ns  
Output Disable to Q  
t
C = 50pF  
2
-
ns  
n
PHZ, PLZ  
L
4.5  
6
-
ns  
-
ns  
Output Transition Time  
, t  
TLH THL  
C = 50pF  
2
-
ns  
L
4.5  
6
-
ns  
-
ns  
Output Disabling Time  
Maximum CP Frequency  
Input Capacitance  
t
C =15pF  
5
10  
60  
-
ns  
PHZ, PLZ  
L
f
C =15pF  
5
-
-
-
MHz  
pF  
pF  
MAX  
L
C
C = 50pF  
-
10  
-
10  
-
10  
-
IN  
L
Power Dissipation Capacitance  
(Notes 6, 7)  
C
C =15pF  
5
90  
PD  
L
Three-State Output  
Capacitance  
C
C = 50pF  
-
-
-
-
-
15  
39  
-
-
15  
-
-
-
15  
-
pF  
ns  
O
L
HCT TYPES  
Propagation Delay Time  
(Figure 1)  
t
t
C = 50pF  
4.5  
PLH,  
L
PHL  
CP to QS  
C =15pF  
5
4.5  
5
-
-
-
-
-
-
16  
-
-
36  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
1
2
L
CP to QS  
t
t
t
C = 50pF  
L
PLH,  
t
PHL  
C =15pF  
15  
-
L
CP to Q  
C = 50pF  
4.5  
5
43  
-
n
PLH,  
L
t
PHL  
C =15pF  
18  
-
L
STR to Q  
C = 50pF  
4.5  
39  
n
PLH,  
L
t
PHL  
Output Enable to Q  
t
t
t
t
t
C = 50pF  
4.5  
4.5  
4.5  
5
-
-
-
-
-
-
-
-
-
35  
35  
15  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
n
PZH, PZL  
L
Output Disable to Q  
t
C = 50pF  
L
n
PHZ, PLZ  
Output Transition Time  
Output Disabling Time  
Maximum CP Frequency  
Input Capacitance  
, t  
C = 50pF  
-
-
-
ns  
TLH THL  
L
t
C =15pF  
14  
60  
-
-
-
ns  
PHZ, PLZ  
L
f
C =15pF  
5
-
-
-
MHz  
pF  
MAX  
L
C
C = 50pF  
-
10  
-
10  
-
10  
-
IN  
L
Power Dissipation Capacitance  
(Notes 6, 7)  
C
C =15pF  
5
110  
pF  
PD  
L
Three-State Output  
Capacitance  
C
C = 50pF  
-
-
-
15  
-
15  
-
15  
pF  
O
L
NOTES:  
6. C  
is used to determine the dynamic power consumption, per register.  
2
PD  
7. P = V  
f (C  
PD  
+ C ) where f = Input Frequency, C = Output Load Capacitance, V  
= Supply Voltage.  
D
CC  
i
L
i
L
CC  
7
CD74HC4094, CD74HCT4094  
Test Circuits and Waveforms  
6ns  
6ns  
INPUT LEVEL  
GND  
90%  
S
10%  
V
V
S
CLOCK  
t
INPUT LEVEL  
t
t
t
W
SU  
H
W
SERIAL IN  
GND  
t
t
PLH  
PHL  
V
OH  
V
S
V
OL  
Q , QS  
n
1
2
t
t
PHL  
PLH  
V
OH  
V
S
V
OL  
QS  
FIGURE 1. DATA PROPAGATION DELAYS, SET-UP AND HOLD TIMES  
INPUT LEVEL  
t = 6ns  
t = 6ns  
r
SERIAL IN  
CLOCK  
f
GND  
OE  
90%  
V
t
t
H
S
SU  
INPUT LEVEL  
GND  
10%  
V
V
S
S
t
t
PLZ  
PZL  
OUTPUT  
LOW TO OFF  
t
W
V
V
S
S
10%  
V
OH  
t
t
V
PHZ  
PZH  
STROBE  
Q
S
V
90%  
OL  
OUTPUT  
HIGH TO OFF  
t
t
PLH, PHL  
V
OH  
OUTPUTS  
OUTPUTS  
CONNECTED  
OUTPUTS  
CONNECTED  
V
n
S
DISCONNECTED  
V
OL  
FIGURE 2. STROBE PROPAGATION DELAYS AND SET-UP  
AND HOLD TIMES  
FIGURE 3. ENABLE AND DISABLE TIMES  
8

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