概述
数据手册HFA5253 概述
800MHz, Ultra High-Speed Monolithic Pin Driver 800MHz的，超高速单片引脚驱动器
HFA5253 数据手册
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PDF下载HFA5253
Semiconductor
October 1998
File Number 4003.4
800MHz, Ultra High-Speed Monolithic Pin
Driver
Features
• High Digital Data Rate . . . . . . . . . . . . . . . . . . . . . 800MHz
• Very Fast Rise/Fall Times. . . . . . . . . . . . . . . . . . . . . 500ps
• Wide Output Range . . . . . . . . . . . . . . . . . . . . . +8V to -3V
• Precise 50Ω Output Impedance
The HFA5253 is a very high speed monolithic pin driver
solution for high performance test systems. The device will
switch at high data rates between two input voltage levels
providing variable amplitude pulses. Slew Rate Control pins
provide independent control over positive and negative slew
rate allowing the customer to optimize the pin driver speed
for their application. The output impedance is trimmed to
achieve a precision 50Ω source for impedance matching.
Two differential ECL/TTL compatible inputs control the
• High Impedance, Three-State Output Control
• Slew Rate Control
Applications
operation of the HFA5253, one controlling the V
/V
HIGH LOW
• IC Tester Pin Electronics
• Pattern Generators
• Pulse Generators
switching and the other controlling the output’s high-
impedance state. The HFA5253’s 800MHz data rate makes it
compatible with today’s high-speed VLSI test systems and
the +8V to -3V output swing satisfies the most stringent
testing requirements of all common logic families.
• Level Comparator/Translator
The HFA5253 is manufactured in Harris’ proprietary
complementary bipolar UHF-1 process.
Part Number Information
TEMP. RANGE
PKG.
NO.
o
PART NUMBER
( C)
PACKAGE
HFA5253CB
0 to 50
20 Ld PSOP
M20.3A
Pinout
Block Diagram
HFA5253 (PSOP)
INPUT BUFFER
TOP VIEW
V
HIGH
+SRC
1
2
V
V
V
V
V
V
20
19
CC1
CC1
CC2
CC2
HIGH
+SRC
Q
Q
V
CC
DATA
DATA
-
3
18 NC
+
50Ω
4
17 DATA
16 DATA
V
OUT
5
OUT
NC
6
15
NC
HIZ
HIZ
+
-
V
14 HIZ
13 HIZ
12
7
EE2
EE2
EE1
EE1
V
V
V
8
V
EE
9
-SRC
-SRC
10
11 V
LOW
V
LOW
INPUT BUFFER
POWER PSOP PACKAGE
(HEAT SLUG SURFACE IS ELECTRICALLY FLOATING)
TRUTH TABLE FOR V
OUT
DATA
0
1
0
1
V
V
LOW
HIGH
HIZ
HIZ
HIZ
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
89
HFA5253
Pin Descriptions
NAME
FUNCTION
V
Positive Supply. Nominal value is 11.2V ±0.2V. Reducing supply voltage below 11.0V will reduce positive output voltage swing.
The total supply voltage from V to V should not exceed 18.0V for normal operation or exceed 19.0V to prevent damage.
CC1
CC1
Harris recommends two wire bonds to this pad to provide the lowest possible impedance. In addition, power supply decoupling
chip capacitors of 470pF, 0.1µF and a 10µF tantalum are recommended. Do not connect the V and V pins together im-
EE1
CC1
CC2
mediately, rather run separate traces until they can be joined at a large bypass capacitor (0.1µF || 10.0µF).
V
Negative Supply. Nominal value is -6.4V ±0.2V. A supply voltage more positive than -6.2V will reduce negative output voltage
swing. The total supply voltage from V to V should not exceed 18.0V for normal operation or exceed 19.0V to prevent
EE1
CC2
CC1
damage. Harris recommends two wire bonds to this pad to provide the lowest possible impedance. In addition, power supply de-
coupling chip capacitors of 470pF, 0.1µF and a 10µF tantalum are recommended. Do not connect the V and V pins to-
EE1
EE1
EE2
gether immediately, rather run separate traces until they can be joined at a large bypass capacitor (0.1µF || 10.0µF).
V
Output Stage Positive Supply. Nominal voltage and cautions are the same as for V
. Having decoupling chip capacitors close
CC1
to V
and V
is essential since large AC current will flow through this pad to the output during transients. Harris recommends
CC2
two wire bonds for this pad. Do not connect the V
EE2
and V
CC2
pins together immediately, rather run separate traces until they
CC1
can be joined at a large bypass capacitor (0.1µF || 10.0µF).
V
Output Stage Negative Supply. Nominal voltage and cautions are the same as for V
to V and V
. Having decoupling chip capacitors close
EE1
is essential since large AC current will flow through this pad to the output during transients. Harris recommends
EE2
CC2
EE2
two wire bonds for this pad. Do not connect the V
and V
pins together immediately, rather run separate traces until they
EE2
EE1
can be joined at a large bypass capacitor (0.1µF || 10.0µF).
V
Input Voltage High is used to set the output high level V . V is sensitive to capacitively coupled AC noise. Protection from
OH HIGH
HIGH
high frequency noise can be achieved with a low pass filter consisting of a 50Ω chip resistor and a 470pF chip capacitor. Without
this precaution the pin driver may oscillate due to feedback from the output through the PC board ground.
V
Input Voltage Low is used to set the output low level V . V is sensitive to capacitively coupled AC noise. Protection from
OL LOW
LOW
high frequency noise can be achieved with a low pass filter consisting of a 50Ω chip resistor and a 470pF chip capacitor. Without
this precaution the pin driver may oscillate due to feedback from the output through the PC board ground.
V
Driver Output. The output impedance has been laser trimmed to match a 50Ω transmission line ±2Ω. Custom output impedance
trimming is available (contact sales office for details) to provide the best match possible to your 50Ω system.
OUT
DATA, DATA Differential Digital Inputs used to switch V
OUT
to the V
or V
level. Harris recommends this input pair be driven by com-
LOW
HIGH
plementary ECL signals to provide optimal switching speeds and timing accuracy. However a large Common Mode and Differen-
tial Voltage Range is provided to accommodate a variety of signals including single ended TTL and CMOS. When using single
ended signals the other input must be tied to an appropriate threshold voltage.
HIZ, HIZ
+SRC
Differential Digital Inputs used to switch V from an Active to a High Impedance State. Harris recommends that this input pair
OUT
be driven by complementary ECL signals to provide optimal switching speeds and timing accuracy. However a large Common
Mode and Differential Voltage Range is provided to accommodate a variety of signals including single ended TTL and CMOS.
When using single ended signals the other input must be tied to an appropriate threshold voltage.
The Positive Slew Rate Control Pin adjusts the rising edge slew rate with an external current I
. I draws current (0mA
STEAL STEAL
to 10mA) from an internal current source limiting the rate of change of the high impedance node. Typically an external resistor to
GND is sufficient to set the slew rate at a desired level. Leaving the +SRC Pin open will give the highest speed performance. The
external current I
STEAL
for a resistor R
STEAL
connected from +SRC to GND may be calculated by: I
STEAL
= (V
CC
- 0.35)/R .
STEAL
-SRC
The Negative Slew Rate Control Pin adjusts the falling edge slew rate with an external current I supplies current
. I
STEAL STEAL
(0mA to 10mA) to an internal current source limiting the amount of current being drawn from the circuit and thus limiting the rate
of change of the high impedance node. Typically an external resistor to GND is sufficient to set the slew rate at a desired level.
Leaving the -SRC Pin open will give the highest speed performance. The external current I
for a resistor R connected
STEAL
STEAL
from -SRC to GND may be calculated by: I
= (V + 0.35)/R .
EE STEAL
STEAL
90
HFA5253
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19V
Differential Input Voltage (DATA and HIZ) . . . . . . . . . . . . . . . . . . 5V
Output Current Continuous (Note 1) . . . . . . . . . . . . . . . . . . . 160mA
Thermal Resistance (Typical, Note 2)
20 Ld PSOP Package . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
JA
JC
49
2
(θ Measured At Copper Slug Top Center with Infinite Heat Sink)
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . 175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . 150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
JC
o
Input Voltage (Any pin except as specified) . . . . . . . . . . V
to V
CC
EE
o
V
Voltage (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to -4V
OUT
o
o
V
V
V
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
to -4V
HIGH
LOW
HIGH
CC
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to V
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
EE
to V
Voltage. . . . . . . . . . . . . 11V to 0V (V
> V
)
(PSOP - Lead Tips Only)
LOW
HIGH LOW
Slew Rate Control Current (+SRC, -SRC) . . . . . . . . . . . . . . . . 12mA
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 50 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Internal Power Dissipation may limit Output Current below 160mA.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
3. Shorting the output to a voltage outside the specified range may damage the output.
Electrical Specifications
V
= +11.2V; V = -6.4V; V = -0.9V; V = -1.75V; +SRC and -SRC are Not Connected, Unless
EE IH IL
CC
Otherwise Specified
(NOTE 4)
TEST
LEVEL
TEMP.
( C)
o
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
INPUT CHARACTERISTICS (V
, V )
HIGH LOW
V
V
V
V
V
V
V
V
Input Offset Voltage
Input Offset Voltage
Input Bias Current
Input Bias Current
Voltage Range
A
A
A
A
A
A
A
A
A
25
25
25
25
25
25
25
25
25
-150
-150
-50
-400
-3.5
-3.5
0
-50
-50
110
-110
-
+50
+50
400
50
mV
mV
µA
µA
V
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
V
V
= -3.25V to +8.5V
= -3.5V to +8.25V
HIGH
LOW
8.5
8.5
9.5
4
Voltage Range
-
V
to V
Differential Voltage Range
V
≥ V
LOW
-
V
LOW
Interaction (Notes 5, 17)
HIGH
/V
HIGH LOW
At 500mV
At 250mV
-
2
mV
mV
-
20
40
LOGIC INPUT CHARACTERISTICS (DATA, DATA, HIZ, HIZ)
Logic Input Voltage Range
B
B
A
A
A
A
25
25
25
25
25
25
-3
-
8
5
V
Logic Differential Input Voltage
0.4
-
V
DATA/DATA Logic Input High Current
DATA/DATA Logic Input Low Current
HIZ/HIZ Logic Input High Current
HIZ/HIZ Logic Input Low Current
TRANSFER CHARACTERISTICS
V
V
V
V
= 0V, V = -2V
IL
-50
110
-300
70
700
50
400
50
µA
µA
µA
µA
IH
IH
IH
IH
= 0V, V = -2V
IL
-700
-50
= 0V, V = -2V
IL
= 0V, V = -2V
IL
-400
-80
V
V
V
Voltage Gain
Voltage Gain
V
V
= -1V to 6.5V
= -1.5V to 6V
A
A
A
A
B
B
C
C
25
25
25
25
25
25
25
25
0.95
0.95
-0.1
-0.8
-
0.97
1
1
V/V
V/V
%
HIGH
LOW
HIGH
LOW
0.97
/V
HIGH LOW
Linearity Error
Fullscale = 5V, Note 6
Fullscale = 10.5V, Note 7
-
0.1
0.8
-
-
100
-
%
V
/V
HIGH LOW
-3dB Bandwidth
200mV
MHz
V/ns
V
P-P
Typical Slew Rate Control Range
+SRC Pin Voltage
I
= 0mA to 10mA, 5V Step
1.0
-
2.8
-
STEAL
V
- 0.35
CC
-SRC Pin Voltage
-
V
+ 0.35
-
V
EE
SWITCHING CHARACTERISTICS (Z
Propagation Delay (Notes 8, 10)
= 16 inches of RG-58 Terminated with 50Ω)
LOAD
B
B
25
25
1
-
-
2
ns
ps
Propagation Delay Match (Rising to Falling Edge,
Notes 8, 10)
-100
100
Rising Edge Propagation Delay vs Duty Cycle
(Notes 9, 10)
B
25
-120
-20
80
ps
91
HFA5253
Electrical Specifications
V
= +11.2V; V = -6.4V; V = -0.9V; V = -1.75V; +SRC and -SRC are Not Connected, Unless
CC
EE
IH
IL
Otherwise Specified (Continued)
(NOTE 4)
TEST
LEVEL
TEMP.
( C)
o
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Falling Edge Propagation Delay vs Duty Cycle
(Notes 9, 10)
B
25
-80
20
120
ps
Active to HIZ Delay (Note 10)
HIZ to Active Delay (Note 10)
B
B
25
25
1.5
2.8
2.0
3.3
2.5
3.8
ns
ns
TRANSIENT RESPONSE (Z
= 16 inches of RG-58 Terminated with 5pF)
LOAD
Rise/Fall Time
1V , 20% - 80% (Note 11)
P-P
B
B
B
B
B
B
B
B
B
25
25
25
25
25
25
25
25
25
350
450
890
1.3
100
1.0
1.2
2.0
5
500
ps
ps
ns
ps
ns
ns
ns
%
3V , 10% - 90% (Note 11)
P-P
700
1000
5V , 10% - 90% (Note 12)
P-P
1.1
1.7
Rise/Fall Time Match (Note 12)
-
-
-
-
-
-
-
-
-
-
-
-
Minimum Output Pulse Width (Note 13)
1V
3V
5V
3V
P-P
P-P
P-P
P-P
Overshoot/Undershoot/Preshoot
Data Settling Time (Note 14)
OUTPUT CHARACTERISTICS
Output Voltage Swing
To 1%
10
ns
No Load at V
= 11V, V = -6.2V
EE
A
A
A
A
C
A
A
25
25
25
25
25
25
25
-3
0.25
45
-
-
8
9.0
49
100
-
V
V
CC
Output Amplitude Voltage
V
- V
OL
OH
DC Output Resistance (Note 15)
Output Leakage - HIZ
-3V to 8V
-3V to 8V
47
-
Ω
-100
-
nA
pF
mA
V
Output Capacitance - HIZ
5
Output Current - Active
80
100
-
-
Output Short Circuit Range (Note 3)
POWER SUPPLY CHARACTERISTICS (V
-4.0
9.0
= 5V Active, No Load)
HIGH
V
V
Power Supply Rejection Ratio (Note 16)
A
A
A
B
B
A
A
A
A
25
25
25
25
25
25
25
25
25
-
14
14
96
74
22
11.2
-6.4
-
40
40
mV/V
mV/V
mA
mA
mA
V
HIGH
Power Supply Rejection Ratio (Note 16)
-
90
-
LOW
Total Supply Current
98
I
I
/I
CC1 EE1
Supply Current
Supply Current
-
/I
CC2 EE2
-
-
Supply Voltage Range
V
V
V
V
11.0
-6.6
17.2
-
11.4
-6.2
18.0
1.72
CC
EE
CC
CC
V
- V
V
EE
= 11.2V, V = -6.4V, No Load
Power Dissipation
NOTES:
-
W
EE
4. Test Level: A = 100% production tested, B = Typical or limit based on lab characterization of a limited number of lots, C = Design Information,
goal or condition.
5. V
to V
Interaction is measured as the change in V
(the active channel) due to a change in the inactive channel. V
Interaction
HIGH
LOW
OUT
HIGH
Interaction at 250mV is
at 250mV is measured as the deviation from 1V as V
measured as the deviation from 0V as V
is changed from 0V to 750mV (Referred to V
). V
LOW
LOW
is changed from 1V to 250mV (Referred to V
OUT
).
HIGH
OUT
6. For V
7. For V
= 0V to 5V, for V
= 0V to 5V, Fullscale = 5V, 0.1% = 5mV. Output Amplitude (V
- V
) = 1V
HIGH
.
HIGH
HIGH
LOW
= -2.5V to 8V, for V
HIGH
LOW
P-P
- V
= -3.0V to 7.5V, Fullscale = 10.5V, 0.1% = 10.5mV. Output Amplitude (V
) = 1V
LOW P-P.
LOW
8. 3V Step, 50% duty cycle, 200ns period.
9. 0V to 3V Step, 200ns period, Pulse Width is varied from 5ns to 195ns.
10. Test is performed into a 50Ω load with a 3V step. Measurement is made from the 50% of the input to 50% of output.
11. Limit based on calculation.
12. 5V Step, 50% duty cycle, 100ns period.
13. Minimum Pulse Width is measured 50% to 50% of specified amplitude with pulse peak at 100% of amplitude.
14. 3V Step, measured from 50% of input to ±1% of reference value at 50ns.
15. Dynamic Output Resistance will be higher (Typ 48.5Ω) than DC Output Resistance. DC Output Resistance is measured at 0V with I
set
OUT
from 0mA to 40mA.
16. V
= 2.6V, V
= 2.3V, V = 10.2V to 11.2V, V = -5.4V to -6.4V.
CC EE
HIGH
17. Input voltages V
LOW
and V
are corrected for Offset Voltage and Gain Error.
HIGH
LOW
92
HFA5253
stage and the collector-base capacitance of the output stage
transistors connected to the node VSO. The Slew Rate Control
Pins, +SRC and -SRC, allow the user to control the amount of
Functional Block Diagram
The HFA5253 functional block diagram is shown in on the first
page of this data sheet.
current available in the V
and V switch, respectively
HIGH
LOW
The control inputs, DATA and DATA, determine the output level.
If DATA is at logic “1” and DATA is at logic “0”, the output level
and thus the slew rate of node VSO.
The output stage consists of cascaded emitter followers
constructed in a typical push-pull manner as shown in the
Schematic Diagram. However, transdiodes are added to
increase the voltage breakdown characteristics of the output
during high impedance mode. HIZ and HIZ control the mode
of the output stage. A trimmed, NiCr resistor is added to
provide the 50Ω output impedance.
will be the same as V
logic “1”, the output will be the same as V
LOW
inputs, HIZ and HIZ, cause the output to become either active
or high-impedance. If HIZ is at logic “1” and HIZ is at logic “0”,
the output will be in high impedance mode. If HIZ is at logic “0”
and HIZ is at logic “1”, the output will be enabled. The output
impedance in the enabled mode is trimmed to 50Ω.
. If DATA is at logic “0” and DATA is at
. The control
HIGH
Overall, a symmetry of device types and paths is constructed
Circuit Schematic
The Pin Driver circuit consists of a switch, an output buffer,
and two differential control elements as shown in the circuit
Schematic Diagram.
to improve slew and delay symmetry. Both the V
to V
HIGH
OUT
path and the V
LOW
to V path contain three NPN and
OUT
three PNP transistors operating at similar collector currents.
Thus the transient response of V to V and V to
HIGH LOW LOW
V
are kept symmetrical. Also, a trimmable current
HIGH
A two stage approach, separating the switch from the output
buffer, allows the speed and accuracy requirements of the
switch to be de-coupled from the load driving capability of
the buffer.
reference (not shown) allows the AC parameters to be
adjusted to maintain unit to unit consistency.
Application Information
The patented switch circuitry [3] uses cascaded emitter
The HFA5253 is a pin driver designed for use in automatic
test equipment (ATE) and high speed pulse generators. Pin
drivers, especially those with very high-speed performance,
have generally been implemented with discrete transistors
(sometimes GaAs) on a circuit board or in a hybrid. Recent
IC process improvements, specifically Harris’ UHF1 process
[2], have enabled the manufacturing of the 500MHz and
800MHz silicon monolithic pin drivers, HFA5250, HFA5251
and now the HFA5253.
followers as input buffers and also to switch the input V
HIGH
and V
LOW
to node VSO. Dual differential pairs controlled by the
data timing (DATA and DATA) direct current to select either the
V
or V switch. Matching transistor types and
HIGH
LOW
transdiodes improve linearity and lowers the voltage offset and
offset drift. Stacking two emitter-base junctions allows the
V
to V range to be extended to two Emitter - Base
HIGH
LOW
breakdown voltages of the process. The speed of the pin driver
is largely determined by the current flowing through the switch
Schematic Diagram
V
V
V
/V
HIGH LOW
CONTROL
SWITCHING STAGE
OUTPUT STAGE
HIZ CONTROL
CC2
CC1
+SRC
HIZ
HIZ
DATA
DATA
V
OUT
V
LOW
V
HIGH
VSO
V
EE1
-SRC
V
EE2
93
HFA5253
The ultra high speed performance of the HFA5253 is a result
Linearity Error is calculated for every data point in the range
and the worst case value is recorded.
of UHF1 process leverages: low parasitic collector-to-
substrate capacitance of the bonded wafer, low collector-to-
base parasitic capacitance of the self-aligned base/emitter
V
TO V
INTERACTION
Interaction is the change in V
HIGH
LOW
V
to V
(the
OUT
HIGH
LOW
technology and ultra high f NPN (8GHz) and PNP (5.5GHz)
T
active channel) due to the inactive channel. V
HIGH
poly-silicon transistors.
Interaction is measured as the change in V
from 1V as
OH
Definition of Terms
V
is moved from 0V to 750mV (V
is corrected for
LOW
gain and offset errors). V
LOW
Interaction is measured as
LOW
the change in V from 0V as V
V
AND V
OL
OH
is moved from 1V to
OL
HIGH
corrected for gain and offset errors).
Output High Voltage and Output Low Voltage. V
voltage at V
OUT
is the
when the HIZ input is low and the DATA
OH
250mV (with V
HIGH
The minimum recommended difference between V
HIGH
input is high. V is the voltage at V
when HIZ is low and
and V levels are set with the V
HIGH
OL OUT
and V
for the HFA5253 is 250mV.
LOW
DATA is low. The V
OH OL
and V
inputs respectively.
Speed Advantage
LOW
OFFSET VOLTAGE
Offset Voltage is the DC error between the voltage placed on
or V and the resulting V and V . V
Harris Pin Drivers on bonded-wafer technology definitely have
a speed advantage, coming from the low collector-to-
substrate capacitance and the high f of the transistors. In
T
V
HIGH
LOW
OH OL HIGH
addition, the patented switching stage which fits uniquely to
Harris’ UHF1 process is another big contributor for the high
speed. This switching circuitry requires low series-resistance
NPN and PNP transdiodes available in UHF1. The rise and
fall times of the pin driver are largely determined by the slew
rate at the node VSO in the Schematic. The dominant
mechanism for the slew rate is the charging/discharging of the
collector-base capacitors of the transistors connected to the
node VSO. The charging/discharging currents are coming
from the switching stage current sources. The fast rise and fall
times are achieved because of the negligible collector-to-
substrate capacitance and the small base-collector
Offset Voltage Error is obtained by measuring V
with
OH
set to -2.5V to minimize
V
set to 0V and V
HIGH
interaction effects. V
LOW
Offset Voltage Error is the
LOW
measurement of V with V
set to 0V and V
set to
HIGH
OL
LOW
+7.5V.
GAIN
Gain is defined as the ratio of output voltage change to
input voltage change for a defined range. V
Gain is
fixed at
HIGH
calculated with the following equation with V
LOW
-2.5V:
V
(V
at 6.5V) – V (V
at -1V)
capacitance due to the self-aligned recessed oxide [2].
OH HIGH
OH HIGH
V
GAIN = ------------------------------------------------------------------------------------------------------------------
HIGH
7.5
The DATA/DATA differential stage is not a factor for the speed if
its current sources have enough current not to bottleneck the
transient. However it should be noted that the propagation
delay mismatch is determined by this stage. Sufficient current is
allocated to the differential stage current sources to best match
the low-to-high and high-to-low transient propagation delays.
V
V
Gain is calculated in a similar manner:
LOW
V
(V
at 6V) – V (V
at -1.5V)
OL LOW
OL LOW
GAIN = -------------------------------------------------------------------------------------------------------------
LOW
7.5
V
is held fixed at 7.5V. These Gain calculations minimize
HIGH
the effects of Interaction and End Point Nonlinearities.
The specified load condition is a 16 inch 50Ω SMA cable with a
5pF capacitor at the end of the cable. This load simulates a
typical ATE environment for a DUT (Device Under Test) with
high impedance (>1kΩ) digital inputs. The rise/fall time for
LINEARITY ERROR
Linearity Error is a measure of output voltage worst case
deviation from a straight line that has been corrected for
offset and 7.5V Gain. Linearity Error is given as a
HFA5253 with 5V
is typically 1.3ns. Pin drivers, built out of
P-P
the same circuit structure as shown in the Schematic, can be
made faster by trimming for a higher power supply current.
Currently the pin driver has rise/fall times of less than 1ns (10%
to 90% of 5V ) when I is trimmed to 125mA. Further
percentage of fullscale and is done in two ranges, 5V and
10.5V. DATA is measure at 0.5V steps from -2.5V to 8V for
V
and -3V to 7.5V for V
. The Linearity Error
HIGH
LOW
equation is as follows for 10.5V fullscale:
P-P
CC
speed enhancement will be made if there is a market demand.
V
(IDEAL) = V × Gain + Offset
IN
OUT
Basic ATE System Application
V
– V
(IDEAL)
OUT
Figure 1 shows a pin driver in a typical per-pin ATE system. The
pin driver works closely with the Dual-Level Comparator and
the Active Load. When the DUT pin acts as an input waiting for
a series of digital signals, the pin driver becomes active with a
logic “0” applied on the HIZ pin and provides the DUT pin with
digital signals. When the DUT pin acts as an output, the pin
driver output will be in high impedance mode (HIZ) with a logic
OUT
Linearity Error = --------------------------------------------------------------
10.5
The Linearity Error equation is as follows for 5V fullscale:
V
– V
(IDEAL)
OUT
5
OUT
Linearity Error = --------------------------------------------------------------
94
HFA5253
“1” applied to the “HIZ” pin. During this high impedance mode
the pin driver presents a capacitance of less than 5pF to the
DUT. Special care has to be taken to match the impedance (to
50Ω) at the pin driver output to minimize reflections.
connected to each of the pins, DATA and HIZ through a 50Ω
chip resistor to monitor the pulse signals.
PARTS LIST
QTY
6
VALUE
470pF
COMPONENT
Chip Cap: 0805
The Dual-Level Comparator detects the logic levels of the
DUT pin when it acts as an output. The comparator has two
threshold level inputs, V
and V . The logic level
CH
CL
4
0.1µF
Chip Cap: 0805
Tant.
information of the DUT pin output is sent to the
edge/window comparator through the Dual-Level
Comparator. The edge/window comparator interprets this
information in terms of corresponding transient
performance in conjunction with the timing information.
Thus it detects any possible failure transients.
2
10µF
8
50Ω
Chip Res: 0805
Chip Res: 0805
Wide Body
HFA5253
2
100Ω
7
SMA Jacks
20 Lead PSOP
4-40
1
The formatter sends a sequence of digital information to the
pin driver which contains logic information over time. The
Active Load is enabled when the DUT pin acts as an output.
It simulates the load of the DUT pin by sinking or sourcing
programmed current. Finally the sequencer controls the
overall activities of the automatic testing.
4
1” Standoff
1/4” Screws
4
4-40
2
Twisted Wire Assemblies with 4 Wires Each:
One for V , V , +SRC, GND; and 1 for V , V
,
CC HIGH EE LOW
-SRC, GND.
Decoupling Circuit for Oscillation-Free Operation
The input pins, V
, V , +SRC, and -SRC need to be
HIGH LOW
To ensure oscillation-free operation in ATE or pulse generator
applications, the pin driver needs an appropriate decoupling
circuit on a printed circuit board which consists of chip
capacitors and chip resistors. Figures 2, 3, and 4 refer to a
proven decoupling circuit currently working in the lab and a 1X
scale film of its associated PC board (metal level). Do not
protected from any capacitively coupled AC noise. Normally
this protection can be achieved by having a low pass filter
consisting of a 50Ω chip resistor and a chip capacitor, 470pF
for V
/V and 0.1µF for +SRC/-SRC. Without this
HIGH LOW
protection circuit the pin driver may oscillate due to signals
fed back from the output through the PC board ground.
connect the V
and V
pins or the V
and V pins
CC1
CC2
EE1
EE2
The power supply pins, V
, V
, V
, and V
,
EE2
together immediately, rather run separate traces until they can
CC1 CC2 EE1
require decoupling chip capacitors of 470pF, 0.1µF, 10µF.
Having decoupling capacitors close to V and V is
be joined at a large bypass capacitor (0.1µF || 10.0µF).
CC2 EE2
The control pins, DATA, DATA, HIZ, and HIZ are fed ECL
signals through 50Ω micro-strip lines terminated with 50Ω for
impedance matching since the input impedance at these
pins is much higher than 50Ω. At the end of the micro-strip
lines there is usually a high-speed pulse generator with an
output impedance of 50Ω. A 50Ω micro-strip line is
essential since large AC current will flow through either
or V during transients.
V
CC2
EE2
The output of the pin driver is usually connected to the device-
under-test (DUT) through 50Ω micro-strip line and coaxial cable
which carries the signal to a high input impedance DUT pin.
TIMING
CLOCK,
START
HIZ
ACTIVE
LOAD
DATA
50Ω
MEMORY
MEMORY
FORMATTER
DUT
DATA
PIN DRIVER
EDGE/
WINDOW
COMPARATOR
V
V
DATA
FAIL
CH
CL
SEQUENCER
DUAL LEVEL COMPARATOR
FAIL
MEMORY
TIMING
FIGURE 1. TYPICAL ATE SYSTEM
95
HFA5253
(+11.2V) V
GND
V
+SRC
CC
HIGH
0.1µF
D-SCOPE
50
+
470pF
0.1µF
50
20
10µF
470pF
470pF
1
2
50
19
18
17
16
15
14
13
12
11
3
100
DATA
4
HFA5253
5
DATA
50
V
OUT
6
7
HIZ
50
8
470pF
470pF
9
50
10
100
HIZ
50
0.1µF
50
0.1µF
10µF
+
470pF
HIZ-SCOPE
(-6.4V) V
GND
V
-SRC
EE
LOW
FIGURE 2. DECOUPLING CIRCUIT SCHEMATIC
HFA5253
EVAL BOARD
HARRIS SEMICONDUCTOR
D-SCOPE
GND
DATA
V
H
+SRC
470pF
0.1µ
470pF
50
10µ
V
CC
DATA
100
50
50
50
50
470pF
470pF
50
50
V
OUT
V
EE
10µ
50
0.1µ
100
HIZ
-SRC
470pF
470pF
V
L
GND
HIZ
HIZ-SCOPE
FIGURE 3. 1X PC BOARD LAYOUT (BOTTOM VIEW)
FIGURE 4. 1X PC BOARD LAYOUT (TOP VIEW)
References
[1] Taewon Jung and Donald K. Whitney Jr., “A 500MHz
ATE Pin Driver,” Bipolar Circuits and Technology
Meeting Proceedings, pp238-241, October 1992.
[3] Donald K. Whitney Jr., “Symmetrical, High Speed,
Voltage Switching Circuit,” United States Patent
Pending, Filed November 1991.
[2] Chris K. Davis et. al., “UHF1: A High Speed Complementary
Bipolar Analog Process on SOI,” Bipolar Circuits and Tech-
nology Meeting Proceedings, pp260-263, October 1992.
96
HFA5253
Typical Performance Curves
6
4
I
= 0mA
I
= 10mA
STEAL
STEAL
2
I
= 5mA
STEAL
0
I
= CURRENT FLOWING OUT OF +SRC FOR
STEAL
RISING EDGE OR -SRC FOR FALLING EDGE
-2
0
2
4
6
8
10
TIME (ns)
12 14 16 18
20
FIGURE 5. 5V STEP RESPONSE vs SLEW RATE CONTROL
6
4
I
= -10mA
STEAL
2
I
= -5mA
STEAL
I
= 0mA
STEAL
0
I
= CURRENT FLOWING OUT OF +SRC FOR
STEAL
RISING EDGE OR -SRC FOR FALLING EDGE
-2
0
2
4
6
8
10
TIME (ns)
12
14
16
18
20
FIGURE 6. 5V STEP RESPONSE vs SLEW RATE CONTROL
97
HFA5253
Typical Performance Curves (Continued)
3
2
1
0
1.087ns
0
2.5
5
TIME (ns)
FIGURE 7. MINIMUM PULSE WIDTH, 1V/DIV.; 500ps/DIV.
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
V
HIGH
V
LOW
-4
-2
0
2
4
6
8
10
V
(V)
IN
FIGURE 8. V
ERROR vs V
IN
OUT
98
HFA5253
Typical Performance Curves (Continued)
0.2
0.02
TYPICAL 5 UNITS
0.15
0.1
0.015
0.01
0.05
0.005
0.0
0
-0.005
-0.01
-0.05
-0.1
-4
-2
0
2
4
6
8
10
V
(V)
IN
FIGURE 9. V
LINEARITY ERROR 10.5V FULLSCALE
HIGH
0.25
0.2
TYPICAL 5 UNITS
0.02
0.15
0.1
0.01
0.05
0.0
0
-0.05
-4
-2
0
2
4
6
8
V
(V)
IN
FIGURE 10. V
LINEARITY ERROR 10.5V FULLSCALE
LOW
99
HFA5253
Typical Performance Curves (Continued)
1.06
MINIMUM RECOMMENDED
TO V VOLTAGE
V
ACTIVE (NOMINAL 1.0V)
HIGH
V
HIGH
LOW
1.05
1.04
1.03
1.02
1.01
1
0.99
0.98
0
0.1
0.2
0.3
0.4
0.5
INPUT (V)
0.6
0.7
0.8
0.9
1
V
LOW
FIGURE 11. V
/V INTERACTION
HIGH LOW
0.01
V
ACTIVE (NOMINAL 0.0V)
LOW
0
-0.01
-0.02
-0.03
-0.04
MINIMUM RECOMMENDED
V
TO V
VOLTAGE
HIGH
LOW
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
V
INPUT (V)
HIGH
FIGURE 12. V
/V INTERACTION
HIGH LOW
100
HFA5253
Typical Performance Curves (Continued)
30
o
75 C
20
o
50 C
10
o
25 C
0
-10
-20
-30
-40
-50
-60
o
25 C
o
50 C
o
75 C
-4
-2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
FIGURE 13. HIZ OUTPUT LEAKAGE
3.5
3
TYPICAL 6 UNITS
2.5
2
1.5
1
0.5
0
NOTE: SLEW RATE WILL CONTINUE TO DECLINE AS +SRC
CURRENT IS INCREASED BEYOND 12mA
0
1
2
3
4
5
6
7
8
9
10
11
12
+SRC CURRENT (mA)
FIGURE 14. (+) SLEW RATE vs I
STEAL
101
HFA5253
Typical Performance Curves (Continued)
3.5
TYPICAL 6 UNITS
3
2.5
2
1.5
1
0.5
0
NOTE: SLEW RATE WILL CONTINUE TO DECLINE AS
-SRC CURRENT IS INCREASED BEYOND 12mA
-15
-10
-5
0
-SRC CURRENT (mA)
FIGURE 15. (-) SLEW RATE vs I
STEAL
3.5
3
V
= 8V, I
= 0mA
STEAL
AVERAGE OF 8 UNITS
HIGH
2.5
2
V
= 0V, I = 0mA
STEAL
LOW
V
= -3V, I
= 0mA
STEAL
LOW
1.5
1
V
= 8V, I
= 10mA
STEAL
HIGH
V
= 0V, I = 10mA
STEAL
LOW
0.5
0
V
= -3V, I
= 10mA
LOW
STEAL
0
1
2
3
4
5
6
7
8
9
10
VOLTAGE STEP (V
- V
) (V)
HIGH
LOW
NOTE: The family of curves shows slew rate as a function of common mode voltage. A voltage is provided for each trace specifying one level of the
voltage step for which slew rate is measured. Example 1: Top Trace (V = 8V, I = 0mA). A voltage step of 1V goes from V = 7V to
HIGH STEAL
= 8V. Example 2: Trace (V
LOW
= 0mA). A voltage step of 1V
V
= 8V and a voltage step of 9V goes from V
= -1V to V
= -3V, I
HIGH
goes from V
LOW
HIGH
LOW
STEAL
= -3V to V
HIGH
= -2V and a voltage step of 9V goes from V
= -3V to V = 6V.
LOW
LOW
HIGH
FIGURE 16. (+) SLEW RATE vs AMPLITUDE
102
HFA5253
Typical Performance Curves (Continued)
4
V
= 8V, I
= 0mA
STEAL
HIGH
AVERAGE OF 8 UNITS
3.5
3
V
= 0V, I
= 0mA
STEAL
LOW
V
= -3V, I
= 0mA
STEAL
LOW
2.5
2
1.5
1
V
HIGH
= 8V, I
= 10mA
STEAL
= 0V, I
V
= 10mA
LOW
STEAL
= -3V, I
V
= 10mA
STEAL
LOW
0.5
0
1
2
3
4
5
6
7
8
9
10
VOLTAGE STEP (V
-V ) (V)
HIGH LOW
NOTE: The family of curves shows slew rate as a function of common mode voltage. A voltage is provided for each trace specifying one level of the
voltage step for which slew rate is measured. Example 1: Top Trace (V = 8V, I = 0mA). A voltage step of 1V goes from V = 8V to
HIGH STEAL
= -1V. Example 2: Trace (V
HIGH
= 0mA). A voltage step of 1V
V
= 7V and a voltage step of 9V goes from V
= 8V to V
= -3V, I
LOW
goes from V
HIGH
LOW
LOW
= -3V.
STEAL
= -2V to V
= -3V and a voltage step of 9V goes from V
= 6V to V
HIGH
LOW
HIGH
LOW
FIGURE 17. (-) SLEW RATE vs AMPLITUDE
C
= 6.5pF
LOAD
0.6
0.4
0.2
0
C
= 4pF
LOAD
C
= 10.2pF
LOAD
Z
= 1kΩ || C
LOAD
LOAD
0
1
2
3
4
5
TIME (ns)
6
7
8
9
10
FIGURE 18. 0.5V STEP RESPONSE vs C
LOAD
103
HFA5253
Typical Performance Curves (Continued)
0.6
0.4
0.2
C
= 10.2pF
LOAD
C
= 4pF
LOAD
0
C
= 6.5pF
LOAD
Z
= 1kΩ || C
LOAD
LOAD
-0.2
0
1
2
3
4
5
6
7
8
9
10
TIME (ns)
FIGURE 19. 0.5V STEP RESPONSE vs C
LOAD
104
HFA5253
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
2670µm x 1730µm x 525µm
METALLIZATION:
Nitride, 4kÅ ±0.5kÅ
TRANSISTOR COUNT:
113
Type: Metal 1: Cu (2%) SiAl/TiW
Thickness: Metal 1: 8kÅ ±0.4kÅ
Backside: Gold
SUBSTRATE POTENTIAL:
Floating
Type: Metal 2: Cu (2%) Al
Thickness: Metal 2: 16kÅ ±0.8kÅ
Metallization Mask Layout
HFA5253
+SRC
V
V
CC1
HIGH
DATA
DATA
V
CC2
V
OUT
HIZ
HIZ
V
EE2
-SRC
V
V
EE1
LOW
105
HFA5253
Power Small Outline Plastic Packages (PSOP)
N
M20.3A
INDEX
AREA
0.25(0.010)
M
B M
H
20 LEAD POWER SMALL OUTLINE PLASTIC PACKAGE
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
13.00
8.63
7.60
4.82
NOTES
A
A1
B
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
1
2
3
L
-
SEATING PLANE
A
9
C
0.0091
0.4961
0.325
-
-A-
o
h x 45
D
D
0.5118 12.60
3
D1
E
0.340
0.2992
0.190
8.25
7.40
4.44
10
-C-
α
µ
0.2914
0.175
4
e
A1
C
E1
e
10
B
0.10(0.004)
0.050 BSC
1.27 BSC
-
0.25(0.010) M
C
A M B S
H
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
h
5
TOP VIEW
L
6
N
20
20
7
N
o
o
o
o
0
8
0
8
-
α
Rev. 0 6/95
E1
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
D1
1
2
3
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or
gate burrs. Mold flash, protrusion and gate burrs shall not ex-
ceed 0.15mm (0.006 inch) per side.
POWER SOP PACKAGE
(HEAT SLUG SURFACE IS ELECTRICALLY FLOATING)
4. Dimension “E” does not includeinterlead flashor protrusions.
Interlead flash and protrusions shall not exceed 0.25mm
(0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a vi-
sual index feature must be located within the crosshatched
area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or
greater above the seating plane, shall not exceed a maxi-
mum value of 0.61mm (0.024 inch)
10. Exposed copper heat slug flush with top surface of package.
All other dimensions conform to JEDEC MS-013AC Issue C.
11. Controlling dimension: MILLIMETER. Converted inch di-
mensions are not necessarily exact.
106
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