LM555N [HARRIS]
Timers for Timing Delays and Oscillator Application in Commercial, Industrial and Military Equipment; 计时器在商业，工业和军事装备的定时延迟和振荡器的应用
| 型号： | LM555N |
| 厂家： | 
HARRIS CORPORATION |
| 描述： | Timers for Timing Delays and Oscillator Application in Commercial, Industrial and Military Equipment |
| 文件： | 总6页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CA555, CA555C,
S E M I C O N D U C T O R
LM555, LM555C, NE555
Timers for Timing Delays and Oscillator Application
in Commercial, Industrial and Military Equipment
May 1997
Features
Description
• Accurate Timing From Microseconds Through Hours
• Astable and Monostable Operation
• Adjustable Duty Cycle
The CA555 and CA555C are highly stable timers for use in
precision timing and oscillator applications. As timers, these
monolithic integrated circuits are capable of producing accu-
rate time delays for periods ranging from microseconds
through hours. These devices are also useful for astable
oscillator operation and can maintain an accurately con-
trolled free running frequency and duty cycle with only two
external resistors and one capacitor.
• Output Capable of Sourcing or Sinking up to 200mA
• Output Capable of Driving TTL Devices
• Normally ON and OFF Outputs
o
• High Temperature Stability . . . . . . . . . . . . . . 0.005%/ C
• Directly Interchangeable with SE555, NE555, MC1555,
and MC1455
Applications
• Precision Timing
• Sequential Timing
• Time Delay Generation
The circuits of the CA555 and CA555C may be triggered by
the falling edge of the waveform signal, and the output of
these circuits can source or sink up to a 200mA current or
drive TTL circuits.
• Pulse Generation
• Pulse Detector
• Pulse Width and Position
Modulation
These types are direct replacements for industry types in
packages with similar terminal arrangements e.g. SE555
and NE555, MC1555 and MC1455, respectively. The CA555
type circuits are intended for applications requiring premium
electrical performance. The CA555C type circuits are
intended for applications requiring less stringent electrical
characteristics.
Ordering Information
PART NUMBER
TEMP.
PKG.
NO.
o
(BRAND)
RANGE ( C)
PACKAGE
CA0555E
-55 to 125 8 Ld PDIP
-55 to 125 8 Ld SOIC
-55 to 125 8 Ld SOIC †
-55 to 125 8 Pin Metal Can
E8.3
CA0555M (555)
CA0555M96 (555)
CA0555T
M8.15
M8.15
T8.C
E8.3
CA0555CE
0 to 70
0 to 70
0 to 70
0 to 70
8 Ld PDIP
CA0555CM (555C)
CA0555CM96 (555C)
CA0555CT
8 Ld SOIC
M8.15
M8.15
T8.C
E8.3
8 Ld SOIC †
8 Pin Metal Can
LM555N
-55 to 125 8 Ld PDIP
LM555CN
0 to 70
0 to 70
8 Ld PDIP
8 Ld PDIP
E8.3
NE555N
E8.3
NOTE: † Denotes Tape and Reel
Pinouts
Functional Block Diagram
CA555, CA555C (PDIP, SOIC)
LM555, LM555C, NE555 (PDIP)
TOP VIEW
V+
8
TRIGGER
CONTROL
VOLTAGE
5
2
1
2
3
4
8
7
6
5
GND
TRIGGER
OUTPUT
RESET
V+
DISCHARGE
THRESHOLD
TRIGGER
COMPAR
3
7
CONTROL
VOLTAGE
6
4
OUTPUT
THRESHOLD
COMPAR
CA555, CA555C (METAL CAN)
TOP VIEW
V+
8
TAB
FLIP-FLOP
GND
1
3
7
5
DISCHARGE
6 THRESHOLD
2
TRIGGER
1
GND
CONTROL
VOLTAGE
OUTPUT
4
RESET
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 834.4
Copyright © Harris Corporation 1997
8-3
CA555, CA555C, LM555, LM555C, NE555
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Thermal Resistance (Typical, Note 1)
Metal Can Package . . . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
JA
JC
170
100
160
85
N/A
N/A
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
Operating Conditions
Temperature Range
CA555, LM555 . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
o
Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
o
o
o
CA555C, LM555C, NE555 . . . . . . . . . . . . . . . . . . . . .0 C to 70 C
o
o
o
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications T = 25 C, V+ = 5V to 15V Unless Otherwise Specified
A
CA555, LM555
CA555C, LM555C, NE555
PARAMETER
DC Supply Voltage
SYMBOL
TEST CONDITIONS
MIN
TYP
-
MAX
18
5
MIN
TYP
-
MAX UNITS
V+
I+
4.5
4.5
16
V
mA
mA
V
DC Supply Current (Low State),
(Note 2)
V+ = 5V, R = ∞
-
3
-
3
6
L
V+ = 15V, R = ∞
-
10
12
-
-
10
15
L
2
2
Threshold Voltage
Trigger Voltage
V
-
( / )V+
3
-
( / )V+
3
-
TH
V+ = 5V
1.45
1.67
5
1.9
5.2
-
-
1.67
5
-
V
V+ = 15V
4.8
-
-
V
Trigger Current
-
0.5
0.1
0.7
0.1
3.33
10
-
0.5
0.1
0.7
0.1
3.33
10
-
µA
µA
V
Threshold Current (Note 3)
Reset Voltage
I
-
0.25
1.0
-
-
0.25
TH
0.4
0.4
1.0
Reset Current
-
-
-
mA
V
Control Voltage Level
V+ = 5V
2.9
3.8
10.4
-
2.6
4
V+ = 15V
9.6
9
11
V
Output Voltage
Low State
V
V+ = 5V, I
SINK
= 5mA
-
-
-
-
-
-
-
-
0.25
-
0.35
V
OL
I
= 8mA
0.1
0.1
0.4
2.0
2.5
3.3
13.3
12.5
0.5
30
0.25
0.15
0.5
2.2
-
-
-
V
SINK
V+ = 15V, I
= 10mA
-
0.1
0.4
2.0
2.5
3.3
13.3
12.5
1
0.25
V
SINK
= 50mA
I
I
I
-
0.75
V
SINK
SINK
SINK
= 100mA
= 200mA
-
2.5
V
-
-
-
-
-
-
-
-
V
Output Voltage
High State
V
V+ = 5V, I
SOURCE
= 100mA 3.0
= 100mA 13.0
-
2.75
V
OH
V+ = 15V, I
SOURCE
-
12.75
V
I
= 200mA
-
-
-
-
-
-
-
-
-
V
SOURCE
Timing Error (Monostable)
Frequency Drift with Temperature
Drift with Supply Voltage
R , R = 1kΩ to 100kΩ,
2
%
1
2
C = 0.1µF
Tested at V+ = 5V, V+ = 15V
o
100
0.2
50
ppm/ C
0.05
0.1
%/V
8-4
CA555, CA555C, LM555, LM555C, NE555
o
Electrical Specifications T = 25 C, V+ = 5V to 15V Unless Otherwise Specified (Continued)
A
CA555, LM555
CA555C, LM555C, NE555
PARAMETER
Output Rise Time
SYMBOL
TEST CONDITIONS
MIN
TYP
100
100
MAX
MIN
TYP
100
100
MAX UNITS
t
-
-
-
-
-
-
-
-
ns
ns
R
Output Fall Time
NOTES:
t
F
2. When the output is in a high state, the DC supply current is typically 1mA less than the low state value.
3. The threshold current will determine the sum of the values of R and R to be used in Figure 4 (astable operation); the maximum total
1
2
R
+ R = 20MΩ.
2
1
Schematic Diagram
THRESHOLD
COMPARATOR
TRIGGER
COMPARATOR
V+
FLIP-FLOP
OUTPUT
8
4.7K
830
1
4.7K
1K
5K
6.8K
D
D
2
Q
Q
16
10
Q
19
Q
Q
4
3
Q
20
OUTPUT
3
3.9K
7K
THRESHOLD
6
Q
Q
7
1
Q
Q
5
2
D
3
D
4
4.7K
5K
5K
10K
Q
18
Q
Q
11 12
CONTROL
VOLTAGE
220
Q
21
Q
Q
17
Q
13
9
5
Q
15
4.7K
2
TRIGGER
Q
14
RESET
100K
4
Q
8
RESET
7
DISCHARGE
Q
6
100
DISCHARGE
1
V-
NOTE: Resistance values are in ohms.
Typical Applications
Reset Timer (Monostable Operation)
Figure 1 shows the CA555 connected as a reset timer. In this gized). The action allows the voltage across the capacitor to
mode of operation capacitor C is initially held discharged by increase exponentially with the constant t = R C . When the
T
1 T
a transistor on the integrated circuit. Upon closing the “start” voltage across the capacitor equals 2/3 V+, the comparator
switch, or applying a negative trigger pulse to terminal 2, the resets the flip-flop which in turn discharges the capacitor rap-
integral timer flip-flop is “set” and releases the short circuit idly and drives the output to its low state.
across C which drives the output voltage “high” (relay ener-
T
8-5
CA555, CA555C, LM555, LM555C, NE555
V+
100
RESET
5V
o
T
= 25 C
A
R
680
V+ = 5V
1
4
10
1
7
6
8
5
EO
R
= 1kΩ
1
3
CA555
1N4001
10kΩ
100kΩ
1
2
10K
680
1MΩ
0.1
10MΩ
RELAY
COIL
C
4.7K
T
0.01µF
0.01
0.001
S
1
START
-5
10
-4
10
-3
10
-2
-1
10
10
1
10
TIME DELAY(s)
NOTE: All resistance values are in ohms.
FIGURE 3. TIME DELAY vs RESISTANCE AND CAPACITANCE
Repeat Cycle Timer (Astable Operation)
FIGURE 1. RESET TIMER (MONOSTABLE OPERATION)
Since the charge rate and threshold level of the comparator
are both directly proportional to V+, the timing interval is rel-
atively independent of supply voltage variations. Typically,
the timing varies only 0.05% for a 1V change in V+.
Figure 4 shows the CA555 connected as a repeat cycle
timer. In this mode of operation, the total period is a function
of both R and R
1
R
R
2.
Applying a negative pulse simultaneously to the reset termi-
nal (4) and the trigger terminal (2) during the timing cycle
V+
5V
discharges C and causes the timing cycle to restart.
T
1
2
4
Momentarily closing only the reset switch during the timing
interval discharges C , but the timing cycle does not restart.
T
7
8
5
EO
Figure 2 shows the typical waveforms generated during this
mode of operation, and Figure 3 gives the family of time
3
CA555
6
RELAY
COIL
delay curves with variations in R and C .
1
T
1
2
SWITCH S “OPEN”
1
3V
INPUT
VOLTAGE (TERMINAL 2)
C
0.01µF
T
SWITCH S “CLOSED”
1
0
3.3V
CAPACITOR
FIGURE 4. REPEAT CYCLE TIMER (ASTABLE OPERATION)
VOLTAGE (TERMINALS 6, 7)
0
T = 0.693 (R + 2R ) C = t + t
2
1
2
T
1
t
D
where t = 0.693 (R + R ) C
T
1
1
2
5V
and t = 0.693 (R ) C
2
2
T
OUTPUT
VOLTAGE
the duty cycle is:
(TERMINAL 3)
t
R + R
1 2
R + 2R
1 2
0
1
--------------- ------------------------
=
t
+ t
1
2
FIGURE 2. TYPICAL WAVEFORMS FOR RESET TIMER
Typical waveforms generated during this mode of operation
are shown in Figure 5. Figure 6 gives the family of curves of
free running frequency with variations in the value of
(R + 2R ) and C .
1
2
T
8-6
CA555, CA555C, LM555, LM555C, NE555
t
2
t
100
10
1
o
T
= 25 C, V+ = 5V
A
5V
R
+ 2R = 1kΩ
1
2
10kΩ
1
0
100kΩ
1MΩ
10MΩ
0.1
0.01
3.3V
1.7V
0
0.001
-1
2
3
4
5
10
1
10
10
10
10
10
FREQUENCY (Hz)
Top Trace: Output voltage (2V/Div. and 0.5ms/Div.)
Bottom Trace: Capacitor voltage (1V/Div. and 0.5ms/Div.)
FIGURE 5. TYPICAL WAVEFORMS FOR REPEAT CYCLE TIMER
FIGURE 6. FREE RUNNING FREQUENCY OF REPEAT CYCLE
TIMER WITH VARIATION IN CAPACITANCE AND
RESISTANCE
Typical Performance Curves
150
10
9
8
7
6
5
4
3
2
1
o
T
= 125 C
A
o
T
= -55 C
A
o
100
50
25 C
o
0 C
o
50 C
o
25 C
o
70 C
o
125 C
0
0.1
0.2
0.3
0.4
0
2.5
5
7.5
10
12.5
15
MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE)
SUPPLY VOLTAGE (V)
NOTE: Where x is the decimal multiplier of the supply voltage.
FIGURE 7. MINIMUM PULSE WIDTH vs MINIMUM TRIGGER
VOLTAGE
FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE
2.0
10.0
V+ = 5V
o
T
= -55 C
A
o
1.6
1.2
0.8
0.4
0
T
= -55 C
A
o
25 C
o
25 C
1.0
0.1
o
125 C
o
125 C
5V ≤ V+ ≤ 15V
0.01
1
10
SINK CURRENT (mA)
100
1
10
SOURCE CURRENT (mA)
100
FIGURE 9. OUTPUT VOLTAGE DROP (HIGH STATE) vs
SOURCE CURRENT
FIGURE 10. OUTPUT VOLTAGE LOW STATE vs SINK
CURRENT
8-7
CA555, CA555C, LM555, LM555C, NE555
Typical Performance Curves (Continued)
10.0
10.0
1.0
V+ = 10V
V+ = 15V
o
-55 C
o
T
= -55 C
A
1.0
o
25 C
o
125 C
o
125 C
o
125 C
o
25 C
o
25 C
o
T
= -55 C
0.1
0.1
A
0.01
0.01
1
10
SINK CURRENT (mA)
100
1
10
SINK CURRENT (mA)
100
FIGURE 11. OUTPUT VOLTAGE LOW STATE vs SINK
CURRENT
FIGURE 12. OUTPUT VOLTAGE LOW STATE vs SINK
CURRENT
1.100
o
T
= 25 C
A
1.000
0.990
0.980
1.005
0.995
0.985
0
2.5
5
7.5
10
12.5
15
17.5
-75
-50 -25
0
25
50
75
100 125
o
TEMPERATURE ( C)
SUPPLY VOLTAGE (V)
FIGURE 13. DELAY TIME vs SUPPLY VOLTAGE
FIGURE 14. DELAY TIME vs TEMPERATURE
300
250
200
o
= -55 C
T
A
150
100
50
o
0 C
o
25 C
o
70 C
o
125 C
0
0.1
0.2
0.3
0.4
MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE)
NOTE: Where x is the decimal multiplier of the supply voltage.
FIGURE 15. PROPAGATION DELAY TIME vs TRIGGER VOLTAGE
8-8
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