HB56G236SB-7L [HITACHI]
Fast Page DRAM Module, 2MX36, 70ns, CMOS, SIP-72;
| 型号： | HB56G236SB-7L |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Fast Page DRAM Module, 2MX36, 70ns, CMOS, SIP-72 动态存储器 内存集成电路 |
| 文件： | 总25页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HB56G236 Series, HB56G136 Series
2,097,152-word × 36-bit High Density Dynamic RAM Module
1,048,576-word × 36-bit High Density Dynamic RAM Module
ADE-203-702A (Z)
Rev.1.0
Dec. 27, 1996
Description
The HB56G236 is a 2M × 36 dynamic RAM module, mounted 4 pieces of 16-Mbit DRAM (HM5118160)
sealed in SOJ package and 4 pieces of 2-Mbit DRAM (HM512200) sealed in SOJ package. The
HB56G136 is a 1M × 36 dynamic RAM module, mounted 2 pieces of 16-Mbit DRAM (HM5118160)
sealed in SOJ package and 2 pieces of 2-Mbit DRAM (HM512200) sealed in SOJ package. An outline of
the HB56G236, HB56G136 is 72-pin single in-line package. Therefore, the HB56G236, HB56G136 make
high density mounting possible without surface mount technology. The HB56G236, HB56G136 provide
common data inputs and outputs. Decoupling capacitors are mounted on the module board.
Features
•
72-pin single in-line package
Outline: 107.95 mm (Length) × 25.40 mm (Height) × 9.14/5.28 mm (Thickness)
Lead pitch: 1.27 mm
•
•
Single 5 V (±5%) supply
High speed
Access time: tRAC = 60 /70ns (max)
Low power dissipation
•
Active mode: 2.73/2.42 W (max) (HB56G236 Series)
2.63/2.31 W (max) (HB56G136 Series)
Standby mode (TTL): 84 mW (max) (HB56G236 Series)
(TTL): 42 mW (max) (HB56G136 Series)
(CMOS): 5.25 mW (max) (L-version) (HB56G236 Series)
(CMOS): 2.63 mW (max) (L-version) (HB56G136 Series)
Fast page mode capability
•
•
Refresh period
1024 refresh cycles: 16 ms
128 ms (L-version)
HB56G236 Series, HB56G136 Series
•
3 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
•
TTL compatible
Ordering Information
Type No.
Access time
Package
Contact pad
HB56G236B-6
HB56G236B-7
60 ns
70 ns
72-pin SIP socket type
Gold
HB56G236B-6L
HB56G236B-7L
60 ns
70 ns
HB56G136B-6
HB56G136B-7
60 ns
70 ns
HB56G136B-6L
HB56G136B-7L
60 ns
70 ns
HB56G236SB-6
HB56G236SB-7
60 ns
70 ns
72-pin SIP socket type
Solder
HB56G236SB-6L
HB56G236SB-7L
60 ns
70 ns
HB56G136SB-6
HB56G136SB-7
60 ns
70 ns
HB56G136SB-6L
HB56G136SB-7L
60 ns
70 ns
2
HB56G236 Series, HB56G136 Series
Pin Arrangement
1Pin
36Pin
37Pin
72Pin
Pin No.
Pin name
VSS
Pin No.
19
Pin name
Pin No.
37
Pin name
Pin No.
55
Pin name
DQ12
DQ30
DQ13
DQ31
VCC
1
NC
DQ17
DQ35
VSS
2
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
VCC
20
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
38
56
3
21
39
57
4
22
40
CAS0
CAS2
CAS3
CAS1
RAS0
58
5
23
41
59
6
24
42
60
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
7
25
43
61
8
26
44
62
9
27
45
RAS1 (NC)*2 63
10
11
12
13
14
15
16
17
18
28
46
NC
64
65
66
67
68
69
70
71
72
NC
29
NC
47
WE
A0
30
VCC
48
NC
A1
31
A8
49
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
PD1
A2
32
A9
50
PD2
A3
33
RAS3 (NC)*1 51
PD3
A4
34
RAS2
DQ26
DQ8
52
53
54
PD4
A5
35
NC
A6
36
VSS
Notes: 1. RAS3: HB56G236, NC: HB56G136
2. RAS1: HB56G236, NC: HB56G136
3
HB56G236 Series, HB56G136 Series
Pin Description
Pin name
Function
A0 to A9
Address inputs:
Row address:
A0 to A9
Column address: A0 to A9
Refresh address: A0 to A9
DQ0 to DQ35
CAS0 to CAS3
RAS0 to RAS3
WE
Data-in/Data-out
Column address strobe
Row address strobe
Read/Write enable
Power supply
VCC
VSS
Ground
PD1 to PD4
NC
Presence detect pin
No connection
Presence Detect Pin Arrangement (HB56G236)
Function
Pin No.
67
Pin name
PD1
60 ns
NC
70 ns
NC
68
PD2
NC
NC
69
PD3
NC
VSS
70
PD4
NC
NC
Presence Detect Pin Arrangement (HB56G136)
Function
Pin No.
67
Pin name
PD1
60 ns
VSS
70 ns
VSS
68
PD2
VSS
VSS
69
PD3
NC
VSS
70
PD4
NC
NC
4
HB56G236 Series, HB56G136 Series
Block Diagram (HB56G236)
RAS0
CAS0
CAS1
RAS1
LCAS UCAS RAS
LCAS UCAS RAS
DQ0
DQ1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ9
I/O
D2
I/O
D0
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
I/O
I/O
I/O
I/O
I/O
I/O
OE
OE
CAS2 CAS1 RAS
M0
CAS1 CAS2 RAS
I/O
I/O
DQ8
DQ17
I/O
I/O
M2
OE
OE
RAS2
CAS2
CAS3
RAS3
LCAS UCAS RAS
LCAS UCAS RAS
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D3
I/O
D1
I/O
I/O
I/O
I/O
I/O
I/O
OE
OE
CAS2 CAS1 RAS
M1
CAS1 CAS2 RAS
I/O
I/O
DQ26
DQ35
I/O
I/O
M3
OE
OE
A0-A9
WE
D0-D3, M0-M3
D0-D3, M0-M3
D0-D3, M0-M3
D0-D3, M0-M3
V
CC
*D0-D3 : HM5118160
M0-M3 : HM512200
C0-C7
VSS
5
HB56G236 Series, HB56G136 Series
Block Diagram (HB56G136)
RAS0
CAS0
CAS1
LCAS UCAS RAS
DQ0
DQ1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ9
D0
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
OE
CAS2 CAS1 RAS
M0
DQ8
DQ17
I/O
I/O
OE
RAS2
CAS2
CAS3
LCAS UCAS RAS
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D1
OE
CAS2 CAS1 RAS
M1
DQ26
DQ35
I/O
I/O
OE
D0-D1, M0-M1
A0-A9
WE
D0-D1, M0-M1
D0-D1, M0-M1
D0-D1, M0-M1
VCC
*D0-D1 : HM5118160
M0-M1 : HM512200
C0-C3
VSS
6
HB56G236 Series, HB56G136 Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +7.0
–1.0 to +7.0
50
VCC
V
Iout
Pt
mA
W
4
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
°C
°C
Recommended DC Operating Conditions (Ta = 0 to 70°C)
Parameter
Symbol
VSS
Min
0
Typ
0
Max
0
Unit
Note
Supply voltage
V
V
V
V
VCC
4.75
2.4
–1.0
5.0
—
5.25
5.5
0.8
1
1
1
Input high voltage
VIH
Input low voltage
VIL
—
Note: 1. All voltage referred to VSS.
7
HB56G236 Series, HB56G136 Series
DC Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 5%, VSS = 0 V) (HB56G236)
60 ns
70 ns
Parameter
Symbol Min Max Min Max Unit Test conditions
Notes
Operating current
Standby current
ICC1
ICC2
—
—
520
16
—
—
460 mA
tRC = min
1, 2
16
mA
mA
mA
TTL interface,
RAS, CAS = VIH,
Dout = High-Z
—
—
8
1
—
—
8
CMOS interface,
RAS, CAS ≥ VCC – 0.2 V,
Dout = High-Z
Standby current (L-version)
ICC2
1
CMOS interface,
RAS, CAS ≥ VCC – 0.2 V,
Dout = High-Z
RAS-only refresh current
ICC3
ICC5
—
—
520
40
—
—
460 mA
40 mA
tRC = min
2
1
Standby current
RAS = VIH, CAS = VIL,
Dout = enable
CAS-before-RAS refresh
current
ICC6
—
520
—
460 mA
tRC = min
Fast page mode current
ICC7
—
—
520
3.2
—
—
460 mA
3.2 mA
tPC = min
1, 3
4
Battery backup current
(Standby with CBR refresh)
(L-version)
ICC10
CMOS interface,
Dout = High-Z,
CBR refresh:
tRC = 125 µs,
tRAS ≤ 0.3 µs
Input leakage current
Output leakage current
ILI
–10 10
–10 10
–10 10
–10 10
µA
µA
0 V ≤ Vin ≤ 5.5 V
ILO
0 V ≤ Vout ≤ 5.5 V,
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4 VCC 2.4 VCC
0.4 0.4
V
V
High Iout = –5 mA
Low Iout = 4.2 mA
0
0
Notes: 1. ICC depends on output load condition when the device is selected, ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ V ≤ 0.2 V.
IL
8
HB56G236 Series, HB56G136 Series
DC Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 5%, VSS = 0 V) (HB56G136)
60 ns
70 ns
Parameter
Symbol Min Max Min Max Unit Test conditions
Notes
Operating current
Standby current
ICC1
ICC2
—
—
500
8
—
—
440 mA
tRC = min
1, 2
8
mA
TTL interface,
RAS, CAS = VIH,
Dout = High-Z
—
—
4
—
—
4
mA
CMOS interface,
RAS, CAS ≥ VCC – 0.2 V,
Dout = High-Z
Standby current (L-version)
ICC2
0.5
0.5 mA
440 mA
CMOS interface,
RAS, CAS ≥ VCC – 0.2 V,
Dout = High-Z
RAS-only refresh current
ICC3
ICC5
—
—
500
20
—
—
tRC = min
2
1
Standby current
20
mA
RAS = VIH, CAS = VIL,
Dout = enable
CAS-before-RAS refresh
current
ICC6
—
500
—
440 mA
tRC = min
Fast page mode current
ICC7
—
—
500
1.6
—
—
440 mA
1.6 mA
tPC = min
1, 3
4
Battery backup current
(Standby with CBR refresh)
(L-version)
ICC10
CMOS interface,
Dout = High-Z,
CBR refresh:
tRC = 125 µs,
tRAS ≤ 0.3 µs
Input leakage current
Output leakage current
ILI
–10 10
–10 10
–10 10
–10 10
µA
µA
0 V ≤ Vin ≤ 5.5 V
ILO
0 V ≤ Vout ≤ 5.5 V,
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4 VCC 2.4 VCC
0.4 0.4
V
V
High Iout = –5 mA
Low Iout = 4.2 mA
0
0
Notes: 1. ICC depends on output load condition when the device is selected, ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ V ≤ 0.2 V.
IL
9
HB56G236 Series, HB56G136 Series
Capacitance (Ta = 25°C, VCC = 5 V ± 5%) (HB56G236)
Parameter
Symbol
CI1
Typ
—
Max
60
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (WE)
Input capacitance (RAS)
Input capacitance (CAS)
I/O capacitance (DQ)
1
CI2
—
76
pF
1
CI3
—
34
pF
1
CI4
—
48
pF
1
CI/O
—
34
pF
1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
Capacitance (Ta = 25°C, VCC = 5 V ± 5%) (HB56G136)
Parameter
Symbol
CI1
Typ
—
Max
40
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (WE)
Input capacitance (RAS)
Input capacitance (CAS)
I/O capacitance (DQ)
1
CI2
—
48
pF
1
CI3
—
34
pF
1
CI4
—
34
pF
1
CI/O
—
27
pF
1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
10
HB56G236 Series, HB56G136 Series
AC Characteristics (Ta = 0 to 70˚C, VCC = 5 V ±5%, VSS = 0 V) *1, *2, *17
Test Conditions
•
•
•
•
Input rise and fall times: 5 ns
Input timing reference levels: 0.8 V, 2.4 V
Output timing reference levels: 0.4 V, 2.4 V
Output load: 2 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, and Refresh Cycles (Common parameters)
60 ns
70 ns
Min
130
50
Parameter
Symbol
tRC
Min
110
40
10
60
15
0
Max
—
Max
—
Unit
ns
Notes
Random read or write cycle time
RAS precharge time
tRP
—
—
ns
CAS precharge time
tCP
—
10
—
ns
RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tDZC
tT
10000 70
10000 20
10000 ns
10000 ns
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
—
—
—
—
45
30
—
—
—
—
50
16
128
0
—
—
—
—
50
35
—
—
—
—
50
16
128
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
10
0
10
0
15
20
15
15
60
10
0
15
20
15
20
70
10
0
3
4
CAS hold time
CAS to RAS precharge time
CAS delay time from Din
Transition time (rise and fall)
Refresh period (1,024 cycles)
3
3
5
tREF
tREF
—
—
—
—
Refresh period (1,024 cycles)
(L-version)
11
HB56G236 Series, HB56G136 Series
Read Cycle
60 ns
70 ns
Min
—
—
—
0
Parameter
Symbol
tRAC
tCAC
tAA
Min
—
—
—
0
Max
60
15
30
—
Max
70
20
35
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
6, 7
Access time from RAS
Access time from CAS
7, 8, 15
7, 9, 15
Access time from address
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Column address to RAS lead time
Column address to CAS lead time
CAS to output in low-Z
tRCS
tRCH
tRRH
tRAL
0
—
0
—
10
10
5
—
5
—
30
30
0
—
35
35
0
—
tCAL
—
—
tCLZ
—
—
Output data hold time
tOH
3
—
3
—
Output buffer turn-off time
CAS to Din delay time
tOFF
—
15
15
—
—
20
20
—
11
tCDD
Write Cycle
60 ns
Min
0
70 ns
Min
0
Parameter
Symbol
tWCS
tWCH
tWP
Max
—
Max
—
Unit
ns
Notes
Write command setup time
Write command hold time
Write command pulse width
Data-in setup time
12
15
—
15
—
ns
10
—
10
—
ns
tDS
0
—
0
—
ns
13
13
Data-in hold time
tDH
15
—
15
—
ns
Refresh Cycle
60 ns
Min
10
70 ns
Min
10
Parameter
Symbol
tCSR
Max
—
Max
—
Unit
Notes
CAS setup time (CBR refresh cycle)
CAS hold time (CBR refresh cycle)
WE setup time (CBR refresh cycle)
WE hold time (CBR refresh cycle)
RAS precharge to CAS hold time
ns
ns
ns
ns
ns
tCHR
10
—
10
—
tWRP
0
—
0
—
tWRH
10
—
10
—
tRPC
10
—
10
—
12
HB56G236 Series, HB56G136 Series
Fast Page Mode Cycle
60 ns
Min
40
70 ns
Min
45
Parameter
Symbol
tPC
Max
Max
Unit
Notes
Fast page mode cycle time
Fast page mode RAS pulse width
Access time from CAS precharge
RAS hold time from CAS precharge
—
—
ns
tRASP
tCPA
—
100000 —
100000 ns
14
—
35
—
—
40
—
ns
ns
7, 15
tCPRH
35
40
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS
refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh
cycles are required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
6. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
8. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
9. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
10. Either tRCH or tRRH must be satisfied for a read cycles.
11. tOFF (max) defines the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
12. Early write cycle only (tWCS ≥ tWCS (min)).
13. These parameters are referred to CAS leading edge in early write cycles.
14. tRASP defines RAS pulse width in Fast page mode cycles.
15. Access time is determined by the longest among tAA, tCAC and tCPA
.
16. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC / VSS line noise, which causes to degrade VIH min./ V max level.
IL
17. All the VCC and VSS pins shall be supplied with the same voltages.
18. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
13
HB56G236 Series, HB56G136 Series
Notes concerning 2CAS control
1. In one memory cycle, activate both of 2CASs (CAS0 and CAS1 (or CAS2 and CAS3)) or only one of
them or neither of them.
2. To activate both of 2CASs in an ear;y write cycle or a page mode early write cycle, please keep tSKW
(skew between CAS0 and CAS1 (or CAS2 and CAS3)) 5 ns or less.
RAS
CAS0
(CAS2)
CAS1
(CAS3)
<
tSKW 5ns
WE
3. If the different CASs are activated in the consecutive page cycles, tUL the period that both CASs are
high, should be keep tCP spec (tCP min ≤ tUL).
Example
RAS
CAS0
(CAS2)
CAS1
(CAS3)
tUL
1st cycle
2nd cycle
14
HB56G236 Series, HB56G136 Series
Timing Waveforms*18
Read Cycle
t
t
RC
t
RAS
RP
RAS
t
t
CSH
CRP
t
t
t
RCD
RSH
CAS
t
T
CAS
t
t
t
RAD
RAL
CAL
t
t
t
CAH
ASR
ASC
t
RAH
Row
Column
Address
t
RRH
t
RCH
t
RCS
WE
t
t
CDD
DZC
High-Z
Din
t
CAC
t
AA
t
OFF
t
RAC
t
t
OH
CLZ
Dout
Dout
15
HB56G236 Series, HB56G136 Series
Early Write Cycle
t
t
RC
t
RAS
RP
RAS
CAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
WP
t
t
WCH
WCS
WE
t
t
DH
DS
Din
Din
High-Z*
Dout
t
t
(min)
WCS
WCS
*
16
HB56G236 Series, HB56G136 Series
RAS-Only Refresh Cycle
t
RC
t
t
RP
RAS
RAS
t
T
t
t
t
CRP
CRP
RPC
CAS
t
t
ASR
RAH
Row
Address
Dout
t
OFF
High-Z
17
HB56G236 Series, HB56G136 Series
CAS-Before-RAS Refresh Cycle
t
t
RC
RC
t
t
t
t
t
RP
RP
RAS
RP
RAS
RAS
CAS
t
T
t
t
t
t
t
CRP
RPC
CP
RPC
CP
t
t
t
t
t
CHR
CSR
CHR
CSR
t
t
t
WRH
WRP
WRH
WRP
WE
Address
t
OFF
High-Z
Dout
18
HB56G236 Series, HB56G136 Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RAS
RP
RAS
RP
RAS
RAS
t
T
t
t
t
CRP
RSH
CHR
t
RCD
CAS
t
t
RAL
RAD
t
RAH
tASR
t
t
CAH
ASC
Address
Row
Column
t
RCH
t
t
RCS
RRH
WE
t
t
CDD
DZC
High-Z
Din
t
CAC
t
AA
t
t
t
RAC
OFF
OH
t
CLZ
Dout
Dout
19
HB56G236 Series, HB56G136 Series
Fast Page Mode Read Cycle
t
RASP
t
t
RP
CPRH
RAS
CAS
t
T
t
t
t
t
CSH
PC
RSH
t
CRP
t
t
t
t
t
RCD
CAS
CP
CAS
CAL
CP
CAS
t
t
RAL
CAL
t
t
t
RAD
CAL
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
Row
Address
Column 1
Column 2
Column N
t
t
t
t
RCS
RCS
RRH
RCH
t
t
t
t
t
t
RCS
DZC
RCH
CDD
RCH
CDD
WE
t
t
DZC
DZC
t
CDD
High-Z
High-Z
High-Z
Din
t
t
t
CPA
RAC
CPA
t
t
t
t
t
t
OH
AA
OH
AA
OH
AA
t
t
CAC
t
t
t
t
OFF
CAC
CAC
CLZ
OFF
t
OFF
t
t
CLZ
CLZ
Dout 1
Dout 2
Dout N
Dout
20
HB56G236 Series, HB56G136 Series
Fast Page Mode Early Write Cycle
t
t
RASP
RP
RAS
t
T
t
t
t
RSH
CSH
PC
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
CAS
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
WP
t
WP
t
WP
t
t
t
t
WCS
WCS
WCH
WCS
WCH
WCH
WE
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
Din 1
Din 2
Din N
Din
High-Z*
Dout
t
t
(min)
WCS
*
WCS
21
HB56G236 Series, HB56G136 Series
Physical Outline
HB56G236B/SB Series
mm
inch
Unit:
Front side
107.95
4.25
101.19
3.98
9.14 max
0.36
3.175
0.125
2-Ø
Component area
R1.57
R0.062
(Front)
6.35
0.25
1
72
A
2.03
0.08
1.27 typ.
0.05
6.35
0.25
+ 0.10
– 0.08
1.27
+ 0.004
– 0.003
0.05
6.35
0.25
44.45
1.75
44.45
1.75
R1.57
R0.062
Back side
1
7 2
Component area
(Back)
Detail A
2.54 min
0.10
0.25 max
0.01
1.04 ± 0.03
0.041 ± 0.001
22
HB56G236 Series, HB56G136 Series
HB56G136B/SB Series
mm
Unit:
inch
Front side
107.95
4.25
101.19
3.98
5.28 max
0.208
3.175
0.125
2-Ø
Component area
R1.57
R0.062
6.35
0.25
1
72
A
+ 0.10
1.27
– 0.08
2.03
0.08
1.27 typ.
0.05
6.35
0.25
+ 0.004
0.05
– 0.003
6.35
0.25
44.45
1.75
44.45
1.75
R1.57
R0.062
Back side
1
7 2
Detail A
2.54 min
0.10
0.25 max
0.01
1.04 ± 0.03
0.041 ± 0.001
23
HB56G236 Series, HB56G136 Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Tel: 415-589-8300
Fax: 535-1533
Fax: 415-583-4207
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Berkshire SL6 8YA
United Kingdom
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 0628-585000
Fax: 0628-778322
Tel: 27359218
Fax: 27306071
24
HB56G236 Series, HB56G136 Series
Revision Record
Rev. Date
Contents of Modification
Drawn by
Approved by
1.0
Dec. 27, 1996 Initial issue
25
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