HCD66002 [HITACHI]
Liquid Crystal Driver, 80-Segment, CMOS, DIE;
| 型号： | HCD66002 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Liquid Crystal Driver, 80-Segment, CMOS, DIE |
| 文件： | 总21页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD66002
(80-Channel General-purpose Driver for Middle- or Small-sized
Liquid Crystal Panel)
ADE-207-277(Z)
'99.9
Rev. 0.0
Description
The HD66002 is an 80-channel column driver, which drives a middle-or small-sized liquid crystal panel.
This product can be used to expand the display of small portable equipment when connected to LCD-II
controllers. In addition, it can be applied to middle-sized dot-matrix liquid crystal displays with sizes such
as 128 × 240 or 128 × 480 dots.
Features
•
•
•
•
•
•
•
•
Logic power supply voltage: 2.7 to 5.5V
Display duty: 1/16 (1/5 bias) to 1/128
80 liquid crystal display drive circuits
Liquid crystal display drive voltage: 6 to 17V
Data transfer speed: 2.5 MHz max
Serial/parallel conversion function
Chip enable signal automatic generation
Controllers that can be used with
HD44780U, HD66710, HD66712, HD66720, and HD66730 (LCD-II series)
HD61830B (LCDC series)
•
•
Packages
FP-100A
TFP-100B
No package (bare chip)
CMOS process
1
HD66002
Ordering information
Type name
HD66002FS
HD66002TE
HCD66002
Package
FP-100A
TFP-100B
Bare chip
2
HD66002
Pin Arrangement
Y 51
Y 52
Y 53
Y 54
Y 55
1
80
79
78
77
76
75
Y 30
Y 29
Y 28
Y 27
Y 26
2
3
4
5
6
Y 56
Y 57
Y 25
Y 24
7
8
74
73
Y 58
Y 59
Y 60
Y 23
Y 22
Y 21
9
72
71
10
11
70
69
68
Y 61
Y 62
Y 20
Y 19
12
13
Y 63
Y 64
Y 65
Y 66
Y 18
Y 17
Y 16
Y 15
14
15
16
17
67
66
65
64
63
62
61
HD66002FS
(FP-100A)
Y 67
Y 68
Y 14
Y 13
18
19
(Top view)
Y 69
Y 70
Y 71
Y 12
Y 11
Y 10
20
21
22
60
59
58
57
56
Y 72
Y 73
Y 9
Y 8
23
24
Y 74
Y 75
Y 7
Y 6
25
26
27
55
54
Y 76
Y 77
Y 5
Y 4
Y 78
Y 79
Y 80
28
29
53
52
Y 3
Y 2
Y 1
30
51
Figure 1 Pin Arrangement (HD66002FS)
3
HD66002
1
2
75
74
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
Y19
Y18
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y53
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Y71
Y72
Y73
Y74
Y75
Y76
Y77
3
4
73
72
5
6
7
71
70
69
8
9
68
67
10
11
12
66
65
64
63
HD66002TE
(TFP-100B)
13
14
62
61
15
16
17
18
60
59
58
(Top view)
19
20
57
56
Y8
Y7
Y6
Y5
Y4
Y3
21
22
23
55
54
53
52
51
24
25
Figure 2 Pin Arrangement (HD66002TE)
4
HD66002
Block Diagram
Y80Y79Y78Y77Y76
Y1
V1
V2
V3
Liquid crystal display drive circuit
V4
M
80-bit latch circuit
CL1
DIOL
DIOR
DR
80-bit bi-directional shift register
(also used as a latch circuit)
DL
S/P
Selector
Counter
FCS
Operating mode
switching circuit
E
CAR
TEST1
TEST2
Test input
CL2
SHL
Figure 3 Block Diagram
5
HD66002
Block Functions
Liquid crystal display drive circuit
Generates one of four levels V1 to V4 to the output pin to drive the liquid crystal display according to the
combination of data of the 80-bit latch circuit and the M signal.
80-bit latch circuit
Latches data of the 80-bit bi-directional shift register (also used as a latch circuit) at the falling edge of
CL1, and transmits it to the liquid crystal display drive circuit.
80-bit bi-directional shift register (also used as a latch circuit)
When FCS is low, this register functions as an 80-bit shift register. At this time, DIOL and DIOR are used
as data input/output pins. When FCS is high, this register functions as a 20 × 4-bit latch circuit. At this
time, data that is input in serial to data input pin DR or DL is converted to 4-bit data, and then is latched to
this register according to the latch signal generated by the selector.
S/P
Converts serial data into 4-bit parallel data.
Selector
Decodes output data from the counter and generates a latch signal. Functions when latching data at serial-
latch operation (when FCS is high). At this time, after 80 bits of data Y1 to Y80 are completely latched,
the operation of the selector terminates. Even if input data changes, data in the latch circuit is maintained.
Operating mode switching circuit
Switches shift register operation (when FCS is low) and serial-latch operation (when FCS is high).
6
HD66002
Pin Functions
Table 1
Pin Functions
Input/
Classification Symbol Pin No. Pin Name Output Function
Power supply
VCC
GND
VEE
41 (39) VCC
39 (37) GND
36 (34) VEE
—
V
V
CC–GND: Logic power supply
CC–VEE: Power supply for driving the liquid
crystal display.
V1
V2
V3
V4
32 (30) V1
33 (31) V2
34 (32) V3
35 (33) V4
Input
Power supply voltage for liquid crystal display
drive level.
See Figure 4.
Control signal
CL1
CL2
M
38 (36) Clock 1
Input
Input
Input
Input
Display data latch signal. Data is latched at the
falling edge of this signal.
49 (47) Clock 2
Display data latch and shift signal. This signal is
valid at its falling edge.
37 (35)
M
AC conversion signal for liquid crystal display
drive output.
SHL
40 (38) Shift left
Control signal for inverting data output
destination.
1. Operating mode: Serial-latch operation
When serial data is input in order from D1 to
D80, the relationship between data and
output Y are as shown in Table 2.
When SHL is low, data is input from the DL pin,
and the DR pin is set low.
When SHL is high, data is input from the DR
pin, and DL pin is set low.
2. Operating mode: Shift register operation
When serial data is input in order from D1 to
D80, the relationship between data and
output Y are as shown in Table 3.
When SHL is low, data is input to the DIOL pin,
and output from the DIOR pin.
When SHL is high, the relationships between
DIOL and DIOR are reverse.
E
31 (29) Enable
Input
When FCS is high, data latch starts by setting
the E signal low.
When FCS is low, set the E signal high.
The relationships between the E signal, the
FCS signal, and data latch operation are as
shown in Table 4.
7
HD66002
Pin Functions
Table 1
Pin Functions (cont)
Input/
Classification Symbol
Pin No.
Pin Name Output Function
Control signal CAR
50 (48)
Carry
Output When FCS is high, a chip enable signal is
transferred to the next IC from this pin.
Connect this pin to the next IC.
When FCS is low, open this pin.
DIOL
DIOR
48 (46)
47 (45)
Data I/O (L) Input/ In serial-latch operation, DIOL, DIOR, DR,
Data I/O (R) output and DL are display data input and open pins.
When the SHL pin is high, DL is low and DR
is input, and when it is low, DL is input and
DR is low. At this time, set the DIOL and
DIOR pins low.
DR
DL
46 (44)
45 (43)
Data (R)
Data (L)
Input
In shift register operation, DIOL, DIOR, DR,
and DL are display data input and output
pins. When the SHL pin is high, DIOL and
DIOR are output and input, respectively, and
vice versa when the SHL pin is low. At this
time, set the DR and DL pins low.
When display data is high, liquid crystal
display drive output is selection level and the
liquid crystal display is on, and when display
data is low, they are non-selection and off,
respectively.
FCS
42 (40)
Function
select
Input
Input
Control signal to select each operating mode.
When the FCS pin is low, the operating mode
is shift register, and when it is high, the
operating mode is serial latch.
TEST1
TEST2
43 (41)
44 (42)
Test 1
Test 2
Test pins. Set these pins high.
Liquid crystal Y1 to Y80 51 to 100 Y1 to Y80 Output Each Y pins outputs one of the four voltage
display drive
output
(49 to 100)
1 to 30
(1 to 28)
levels V1, V2, V3, or V4 according to the
combination of M and display data. The
combination is differently between serial latch
operation and shift register operation. See
Figure 5. In case of using at display expanse
of LCD-II family, use in shift register operation
(FCS = L).
Note: Pin numbers of the HD66002TE are enclosed in parentheses ( ).
8
HD66002
V1
V3
V1 and V2: Selection level
V3 and V4: Non-selection level
V4
V2
Figure 4 Liquid Crystal Display Drive level
Serial Latch Operation (FCS = H)
Shift Register Operation (FCS = L)
0
0
1
1
M
M
0
0
0
0
1
1
1
1
Data
Display Data
Output level
V1
V2
Output level
V3 V2 V4
V4 V1 V3
Figure 5 Liquid Crystal Display Drive Output
Table 2
Relationship between Data and Output Y in Serial-Latch Operation
SHL
Low
High
Y1
Y2
...............
...............
...............
Y79
D79
D2
Y80
D80
D1
D1
D2
D80
D79
Table 3
Relationship between Data and Output Y in Shift Register Operation
SHL
Low
High
Y1
Y2
...............
...............
...............
Y79
D2
Y80
D1
D80
D1
D79
D2
D79
D80
Table 4
Relationship between FCS, E, and Data Latch Operation
FCS
E
Data Latch Operation
High
Low
High
High
Enabled
Disabled
—
Low
9
HD66002
Application Examples
Example 1 (Shift Register Operating Mode 1)
Figure 6 shows an example when configuring the 16 × 200-dot LCD panel using the HD66002 (when using
the HD44780U as a controller).
F C S
s e g 2 0 0
T E S T 2
s e g 1 9 9
T E S T 1
s e g 1 9 8
D R , D L
M
C L 2
C L 1
V 2
V 4
V 3
V 1
F C S
T E S T 2
T E S T 1
D R , D L
M
C L 2
C L 1
V 2
V 4
V 3
V 1
s e g 3
s e g 2
s e g 1
G N D
C C
V
V 5
Figure 6 Application Example 1 (Shift Register Operating Mode 1)
10
HD66002
Example 2 (Shift Register Operating Mode 2)
Figure 7 shows an example when configuring the 228 × 25-dot LCD panel using the HD66002 (when using
the HD66730 as a controller).
F C S
s e g 2 2 8
T E S T 2
s e g 2 2 7
T E S T 1
s e g 2 2 6
D R , D L
M
C L 2
C L 1
V 2
V 4
V 3
V 1
F C S
T E S T 2
T E S T 1
D R , D L
M
C L 2
C L 1
V 2
V 4
V 3
V 1
s e g 3
s e g 2
s e g 1
G N D
C C
V
V 5
Figure 7 Application Example 2 (Shift Register Operating Mode 2)
11
HD66002
Example 3 (Serial-Latch Operating Mode)
Figure 8 shows an example when configuring the 64 × 240-dot LCD panel using the HD66002 (when using
the HD61203U as a common driver).
F C S
T E S T 2
s e g 2 4 0
T E S T 1
s e g 2 3 9
s e g 2 3 8
D I O L , D I O R
D R
M
C L 2
C L 1
V 2
V 4
V 3
V 1
F C S
T E S T 2
T E S T 1
D I O L , D I O R
D R
M
C L 2
C L 1
V 2
V 4
V 3
V 1
F C S
T E S T 2
T E S T 1
D I O L , D I O R
D R
M
C L 2
C L 1
s e g 3
s e g 2
s e g 1
V 2
V 4
V 3
V 1
G N D
C C
V
E E
V
Figure 8 Application Example (Serial-Latch Operating Mode)
12
HD66002
Absolute Maximum Ratings
Item
Symbol Ratings
Unit
V
Note
Power supply Logic circuit
voltage
VCC
VEE
–0.3 to +7.0
1
Liquid crystal
VCC – 19.0 to VCC + 0.3
V
display drive circuit
Input voltage (1)
VT1
VT2
Topr
–0.3 to VCC + 0.3
VEE – 0.3 to VCC + 0.3
–20 to +75
V
1 and 2
1 and 3
Input voltage (2)
V
Operating temperature
Storage temperature
°C
°C
Tstg
–55 to +125
Notes: 1. Measured relative to GND (0V).
2. Applies to CL1, CL2, M, SHL, E, DIOL, DIOR, DR, DL, TEST1, TEST2, and FCS pins.
3. Applies to V1 to V4 pins.
4. If the LSI is used beyond its absolute maximum rating, it may be permanently damaged. It
should always be used within the limits of its electrical characteristics in order to prevent
malfunction or unreliability.
13
HD66002
Electrical Characteristics
DC Characteristics (VCC = 2.7 to 5.5V, GND = 0V, VCC – VEE = 6 to 17V, and Ta = –20 to 75 °C,
unless otherwise stated)
Item
Symbol Applicable Pin
Min.
Typ. Max.
Unit Conditions
Note
Input high level VIH
voltage
CL1, CL2, M, SHL, E,
DIOL, DIOR, DR, DL,
FCS, TEST1, and TEST2
0.8 × VCC
—
VCC
V
VCC = 2.7 to 4.5V
0.7 × VCC
—
—
VCC = 4.5 to 5.5V
VCC = 2.7 to 4.5V
VCC = 4.5 to 5.5V
IOH = –0.4 mA
Input low level
voltage
VIL
0
0.2 × VCC
0.3 × VCC
—
Output high
level voltage
VOH
CAR, DIOL, and DIOR
CAR, DIOL, and DIOR
Y1 to Y80, and V1 to V4
VCC – 0.4
—
—
—
—
—
V
V
Output low level VOL
voltage
—
—
—
–5
0.4
20
7.5
5
IOL = 0.4 mA
Vi-Yj on
RON1
RON2
IIL1
kΩ ION = 50 µA
VCC – VEE = 6 to 8V
1
1
resistance
kΩ ION = 100 µA
VCC – VEE = 8 to 17V
Input leakage
current (1)
CL1, CL2, M, SHL, E,
DIOL, DIOR, DR, DL,
FCS, TEST1, and TEST2
µA VIN = VCC–GND
Input leakage
current (2)
IIL2
V1 to V4
–25
—
—
—
25
µA VIN = VCC–VEE
Consumption
current (1)
IGND1
—
1.0
mA fCL2 = 2.5 MHz
fCL1 = 4.48 kHz
fM = 35 Hz
2 and 3
2 and 3
VCC = 3V
Consumption
current (2)
IEE1
—
—
—
100
µA
VCC – VEE = 17V
FCS = high
Consumption
current (3)
IGND2
—
—
—
—
—
—
500
20
µA fCL2 = 400 kHz
2 and 4
2 and 4
fCL1 = 1 kHz
VCC = 3V
Consumption
current (4)
IEE2
µA
VCC – VEE = 13V
FCS = low
Notes: 1. Indicates the resistance between one pin from Y1 to Y80 and another pin from V pins V1 to V4
(Figure 9), when a load current is applied to the Y pin; defined under the following conditions:
V
CC – VEE = 6 to 8V
V1 and V3 = VCC – 2/5 (VCC – VEE)
V4 and V2 = VEE + 2/5 (VCC – VEE)
14
HD66002
VCC–VEE = 8 to 17V
V1 and V3 = VCC – 2/7 (VCC – VEE)
V4 and V2 = VEE + 2/7 (VCC – VEE)
V1 and V3 should be near the VCC level, and V4 and V2 should be near the VEE level. All these
voltage pairs should be separated by less than ∆ V, which is the range within which RON, the
LCD drive circuits’ output impedance, is stable. Note that ∆ V depends on power supply voltage
V
CC – VEE. See Figure 10.
2. Input and output currents are excluded. When a CMOS input is floating, excess current flows
from the power supply through to the input circuit. To avoid this, VIH and VIL must be held to
V
CC and GND levels, respectively.
3. Applies to serial-latch operation.
4. Applies to shift register operation.
RON
V1
V3
V4
V2
Y pins (Y1 to Y80)
One of four points is on.
Figure 9 RON Resistance
3.2
VCC
V1
2.4
∆
∆
V
V
V3
6
8
(V)
VCC – VEE
5.5
3.2
V4
V2
VEE
8
17
(V)
VCC – VEE
Figure 10 Relationship between Driver Output Waveform and Level Voltages
15
HD66002
Pin Configuration
Each pin configuration is shown below.
VCC
Applicable pin:
CL1, CL2, SHL
Applicable pin:
DR and DL
M, E, FCS
TEST1, and TEST2
PMOS
DL
DR
NMOS
Input enable
GND
Figure 11 Input Pin Configuration
V
CC
PMOS
PMOS
NMOS
NMOS
Output data
Applicable pin:
DIOL and DIOR
Output enable
DIOL
V
CC
Output data
PMOS
PMOS
NMOS
NMOS
GND
Output enable
DIOR
Input enable
GND
Figure 12 Input/Output Pin Configuration
VCC
Applicable pin:
CAR
Applicable pin:
Y1–Y80
PMOS
NMOS
PMOS
PMOS
NMOS
NMOS
V1
V3
V4
V2
VCC
VCC
VEE
VEE
Yn
GND
Figure 13 Output Pin Configuration
16
HD66002
AC Characteristics 1 (In Serial-Latch Operation, FCS = VCC) (VCC = 2.7 to 5.5V, GND = 0V,
VCC – VEE = 8 to 17V, and Ta = –20 to +75 ° C, unless otherwise stated)
Item
Symbol Applicable Pins
Min.
400
150
150
100
100
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
Clock cycle time
Clock high level width
Clock low level width
Clock setup time
Clock hold time
tCYC
tCWH
tCWL
tSCL
tHCL
tct
CL2
CL2 and CL1
CL2
—
—
CL1 and CL2
CL1 and CL2
CL1 and CL2
CL1 and CL2
DR, DL and CL2
DR, DL, and CL2
E and CL2
—
—
Clock rise and fall time
Clock phase difference
Data setup time
30
—
tCL
100
80
tDSU
tDH
—
Data hold time
100
200
—
—
Enable setup time
Output delay time
M phase difference
tESU
tDCAR
tCM
—
CAR, CL2, CL1
M and CL1
300
300
1
—
Note: Defined by connecting the load circuit shown in Figure 14.
Test point
30 pF
Figure 14 Load Circuit
17
HD66002
AC Characteristics 2 (In Shift Register Operation, FCS = GND) (VCC = 2.7 to 5.5V, GND = 0V,
VCC – VEE = 6 to 13V, and Ta = –20 to +75 ° C, unless otherwise stated)
Item
Symbol Applicable pins
Min.
2.5
Max.
—
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
Note
Clock cycle time
Clock high level width
Clock low level width
Data setup time
Data hold time
tCYC
tCWH
tCWL
tSU
tDH
tSL
CL2
CL2 and CL1
CL2
800
800
300
300
500
500
—
—
—
DIOL and DIOR
DIOL and DIOR
CL1and CL2
CL1and CL2
DIOL and DIOR
CL1and CL2
—
—
Clock setup time
Clock setup time
Output delay time
Clock rise and fall time
—
1
2
3
tLS
—
tpd
500
200
tct
—
Notes: 1. Setup time from CL2 fall to CL1 fall.
2. Setup time from CL1 fall to CL2 fall
3. Defined by connecting the load circuit shown in Figure 15.
Test point
30 pF
Figure 15 Load Circuit
18
HD66002
tct
tCWH
tct
VIH
CL1
VIL
tCYC
tCL
tSCL
tHCL
VIH
CL2
VIL
tDSU
tDH
tCWH
tCWL
tct
tct
V
IH
IL
DR, DL
V
VIH
CL1
CL2
VIL
Last
data
tDCAR
tDCAR
VOH
CAR
E
V
OL
tESU
VIL
V
IH
IL
M
V
tCM
Figure 16 Serial-Latch Operation Timing
19
HD66002
tCYC
VIH
VIH
tCWL
CL2
VIL
tCWH
tct
tct
tDH
tSU
tSL
VIH
Data in
VIL
DIOL and DIOR
tpd
Data out
DIOL and DIOR
V
OH
tLS
V
OL
tLS
tct
VIH
CL1
V
IL
tCWH
tct
Figure 17 Shift Register Operation Timing
20
HD66002
Cautions
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copyright, trademark, or other intellectual property rights for information contained in this document.
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intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
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Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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