HCD66717A03BP_技术文档

HD66717

(Low-Power Dot-Matrix Liquid Crystal Display

Controller/Driver)

Description

The HD66717 dot-matrix liquid crystal display controller and driver LSI displays alphanumerics,

katakana, hiragana, and symbols. It can be configured to drive a dot-matrix liquid crystal display under

the control of an I²C bus, a clock-synchronized serial, or a 4- or 8-bit microprocessor. A single HD66717

is capable of displaying a maximum of four 12-character lines, 40 segments, and 10 annunciators. The

HD66717 incorporates all the functions required for driving a dot-matrix liquid crystal display such as

display RAM, character generator, and liquid crystal drivers, and a booster for LCD power supply.

The HD66717 provides various functions to reduce the power consumption of an LCD system such as

low-voltage operation of 2.4V or less, a booster for generating a maximum of triple LCD drive voltage

from the supplied voltage, and voltage-followers for decreasing the direct current flow in the LCD drive

bleeder-resistors. Combining these hardware functions with software functions such as standby and sleep

modes allows a fine power control. The HD66717, with the above functions, is suitable for any portable

battery-driven product requiring long-term driving capabilities and small size.

Features

•

5 × 8-dot matrix LCD drive

Four 12-character lines, 40 segments, and 10 annunciators

Low-power operation support:

2.4 to 5.5V (low voltage)

Double or triple booster for liquid crystal drive voltage

Electron volume function and voltage-followers for decreasing the direct current flow in the LCD

drive bleeder-resistors

Standby mode and sleep mode

Displays up to 10 static annunciators

•

I²C bus or clock-synchronized serial interface; 4- or 8-bit parallel bus interface

60 × 8-bit display data RAM (60 characters max)

9,600-bit character generator ROM

240 characters (5 × 8 dots)

452

HD66717

•

32 × 5-bit character generator RAM

4 characters (5 × 8 dots)

8 × 5-bit segment RAM

40 segment-icons and marks max

60-segment × 34-common liquid crystal display driver

Programmable display sizes and duty ratios (see List1)

Vertical smooth scroll

•

Double-height display

Wide range of instruction functions:

Display clear, display on/off, icon and mark control, character blink, white-black inverting

blinking cursor, icon and mark blink, cursor home, cursor on/off, white-black inverting raster-row

•

Hardware reset

Internal oscillation with an external resistor

Wide range of LCD drive voltages

3.0V to 13.0V

•

Slim chip with/without bump (for COB) and tape carrier package (TCP)

List 1

Programmable Display Sizes and Duty Ratios

Oscillation

Frequency

Current

Consumption

Multi-plexed-Drive Static-Drive

Display Size

Duty Ratio

Segments

Annunciators

1 line × 12

characters

1/10

40 kHz

80 kHz

120 kHz

160 kHz

8 µA

40

10

2 lines × 12

characters

1/18

1/26

1/34

15 µA

23 µA

30 µA

40

10

3 lines × 12

characters

4 lines × 12

characters

Note: Current consumption excludes that for LCD power supply source; V_CC= 3V.

List 2 Ordering Information

Type Name

External Dimensin

TCP

Operation Voltage

Internal Font

HD66717A03TA0

HCD66717A03

HCD66717A03BP

HCD66717A13BP

2.4V to 5.5V

Japanese and European fonts

Bare chip

Au-bumped chip

Up-side-down pattern of A03

453

HD66717

LCD-II Family Comparison

LCD-II

Item

(HD44780U)

HD66702R

HD66710

HD66712U

Power supply voltage

2.7V to 5.5V

5V ± 10% (standard)

2.7V to 5.5V

(low voltage)

Liquid crystal drive voltage 3.0 to 11.0V

3.0V to 8.3V

3.0 to 13.0V

2.7 to 11.0V

Maximum display -

characters per chip

8 characters ×

2 lines

20 characters ×

2 lines

16 characters ×

2 lines/

24 characters ×

2 lines/

8 characters ×

4 lines

12 characters ×

4 lines

Segment display

Display duty ratio

None

40

60 (extended to 80)

1/17 and 1/33

1/8, 1/11, and

1/16

1/8, 1/11, and

1/16

1/17 and 1/33

CGROM

9,920 bits

7,200 bits

9,600 bits

(208 5-×-8 dot

characters and

32 5-×-10 dot

characters)

(160 5- -7 dot

characters and

(240 5- -8 dot

characters)

(240 5- -8 dot

characters)

×

32 5- -10 dot

×

characters)

CGRAM

64 bytes

80 bytes

None

40

64 bytes

80 bytes

None

100

64 bytes

80 bytes

8 bytes

40

64 bytes

80 bytes

16 bytes

60

DDRAM

SEGRAM

Segment signals

Common signals

16

33

34

Liquid crystal drive

waveform

A

B

Clock source

External resistor

or external clock

External resistor

or external clock

External resistor

or external clock

External resistor

or external clock

Rf oscillation frequency

270 kHz ± 30%

None

320 kHz ± 30%

None

270 kHz ± 30%

Liquid crystal voltage

booster circuit

Double or triple

booster circuit

Double or triple

booster circuit

Liquid crystal drive

operational amplifier

None

Bleeder-resistor for liquid External

crystal drive

External

None

External

None

External

None

Liquid crystal contrast

adjuster

None

Key scan circuit

None

Extension driver control

signal

Independent

control signal

Independent

control signal

Used in common

with a driver

output pin

Independent

control signal

Reset function

Internal reset

circuit

Internal reset

circuit

Internal reset

circuit

Internal reset

circuit or reset input

Horizontal smooth scroll

Vertical smooth scroll

Impossible

Dot unit

Dot unit and

line unit

Impossible

1 or 2

Impossible

1, 2, or 4

Impossible

Number of displayed lines 1 or 2

1, 2, or 4

Low power control

Bus interface

Package

None

Low power mode

4 or 8 bits

Low power mode

Serial, 4, or 8 bits

4 or 8 bits

80-pin QFP1420

80-pin TQFP1414

80-pin bare chip

144-pin FQFP2020

144-pin bare chip

100-pin QFP1420

100-pin TQFP1414

100-pin bare chip

128-pin TCP

128-pin bare chip

454

HD66717

LCD-II Family Comparison (cont)

Item

HD66720

HD66717

HD66727

Power supply voltage

2.7V to 5.5V

2.4V to 5.5V

3.0 to 13.0V

2.4V to 5.5V

3.0 to 13.0V

12 characters ×

Liquid crystal drive voltage 3.0 to 11.0V

Maximum display

characters per chip

10 characters ×

1 line/

12 characters ×

1 line/2 lines/3 lines/4 lines

8 characters ×

2 lines

Segment display

Display duty ratio

CGROM

42 (extended to 80)

1/9 and 1/17

40 (and 10 annunciators)

1/10, 1/18, 1/26, and 1/34

9,600 bits

40 (and 12 annunciators)

1/10, 1/18, 1/26, and 1/34

11,520 bits

9,600 bits

(240 5-×-8 dot

characters)

(240 5- -8 dot

characters)

(240 6- -8 dot

characters)

×

CGRAM

64 bytes

40 bytes

16 bytes

42

32 bytes

60 bytes

8 bytes

60

32 bytes

60 bytes

8 bytes

60

DDRAM

SEGRAM

Segment signals

Common signals

17

34

Liquid crystal drive

waveform

B

Clock source

External resistor

or external clock

External resistor

or external clock

External resistor

or external clock

Rf oscillation frequency

160 kHz ± 30%

1-line mode: 40 kHz ± 30%

2-line mode: 80 kHz ± 30%

3-line mode: 120 kHz ± 30%

4-line mode: 160 kHz ± 30%

1-line mode: 40 kHz ± 30%

2-line mode: 80 kHz ± 30%

3-line mode: 120 kHz ± 30%

4-line mode: 160 kHz ± 30%

Liquid crystal voltage

booster circuit

Double or triple

booster circuit

Double or triple

booster circuit

Double or triple

booster circuit

Liquid crystal drive

operational amplifier

None

Built-in for each V1 to V5

Bleeder-resistor for liquid External

crystal drive

Internal 1/4 and 1/6 bias

resistors

Internal 1/4 and 1/6 bias

resistors

Liquid crystal contrast

adjuster

None

Incorporated

Key scan circuit

5 × 6 = 30 keys

None

4 × 8 = 32 keys

Extension driver control

signal

Independent

control signal

None

Reset function

Internal reset

circuit or reset input

Reset input

Impossible

Reset input

Impossible

Horizontal smooth scroll

Vertical smooth scroll

Dot unit and

line unit

Impossible

Dot (raster-row) unit

1, 2, 3, or 4

Dot (raster-row) unit

1, 2, 3, or 4

Number of displayed lines 1 or 2

Low power control

Low power mode and sleep Standby mode and

Standby mode and

sleep mode

mode

sleep mode

I²C, serial, 4, or 8 bits

Bus interface

Package

Serial

I²C or clock-synchronized serial

100-pin QFP1420

100-pin TQFP1414

100-pin bare chip

Slim chip with/without bumps

TCP

Slim chip with/without bumps

TCP

455

HD66717

HD66717 Block Diagram

SFT

EXM AGND

OSC1 OSC2

CPG

Timing generator

RESET*

TEST

ASEG1–

ASEG10

Instruction

register

(IR)

Annunciator

driver

Instruction

decoder

7

ACOM

COM1–

COM32

Display data RAM

(DDRAM)

Common

signal

driver

34-bit

shift

register

8

60 × 8 bits

IM1/0

Address

counter

COMS1/2

7

System

RS/CS*

interface

2

• I C bus

7

E/SCL

8

• Clock-

synchro-

nized

serial

• 4 bits

• 8 bits

RW/SDA

SEG1–

SEG60

60-bit

shift

60-bit

latch

Segment

signal

driver

8

Data

register

(DR)

8

register circuit

DB7–DB6

Input/

output

buffer

5

8

DB5/ID5

5

3

7

Busy

flag

–DB0/ID0

Character

generator

RAM

(CGRAM )

32 bytes

LCD drive

voltage

selector

Cursor and

blink

controller

Segment

RAM

(SEGRAM)

8 bytes

generator

ROM

(CGROM)

9,600 bits

Vci

C1

C2

5

Booster

V5OUT2

V5OUT3

Parallel/serial converter

V_CC

GND

–

+ –

+

VR

R

2R

R

OPOFF

V1OUT

V2OUT

V3OUT

V4OUT

V5OUT

V_EE

V2

V3

456

HD66717

HD66717 Pin Arrangement

Dummy

SEG60

SEG59

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

SEG40

SEG39

SEG38

SEG37

SEG36

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG23

SEG22

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

Dummy

V_CC

V1OUT

V2OUT

V3OUT

V4OUT

V5OUT

VREFP

VREF

VREFM

V2

V3

V_EE

V5OUT3

V5OUT2

HD66717

C1

C2

Vci

(Top View)

GND

Dummy

V_CC

OSC2

OSC1

EXM

SFT

IM1

IM0

OPOFF

TEST

RESET*

RS/CS*

E/SCL

RW/SDA

Y

X

DB0/ID0

DB1/ID1

DB2/ID2

DB3/ID3

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

DB4/ID4

DB5/ID5

DB6

SEG2

SEG1

ASEG10

ASEG9

ASEG8

ASEG7

ASEG6

ASEG5

ASEG4

ASEG3

ASEG2

ASEG1

ACOM1

Dummy

DB7

GND

V_CC

AGND

Dummy

457

HD66717

458

HD66717

TCP Dimensions

Dummy

COMS1

COM32

NC

V_CC

V1OUT

V2OUT

V3OUT

V4OUT

V5OUT

VREFP

VREF

COM17

SEG60

0.50mm

pitch

VREFM

0.22 mm

pitch

V2

V3

V_EE

V5OUT3

V5OUT2

C1

C2

Vci

GND

V_CC

OSC2

OSC1

EXM

SFT

IM1

IM0

I/O, Power supply

LCD Driver Outputs

0.50P × (44–1)

= 21.50mm

0.22P × (109–1)

= 23.76 mm

OPOFF

TEST

RESET*

RS/CS*

E/SCL

RW/SDA

DB0/ID0

DB1/ID1

DB2/ID2

DB3/ID3

SEG1

ASEG10

DB4/ID4

ASEG1

ACOMS

COMS2

COM1

DB5/ID5

DB6

DB7

GND

V_CC

AGND

NC

COM16

Dummy

459

HD66717

Pin Functions

Table 1

Pin Functional Description

Number

Device

Signal

of Pins I/O

Interfaced with Function

IM1, IM0

2

I

V_CCor GND

Selects interface mode with the MPU:

IM1, IM0 = GND, GND: I²C bus mode (receive)

IM1, IM0 = GND, V_CC: Clock-synchronized serial mode

(receive)

IM1, IM0 = V_CC, GND: 8-bit bus mode

IM1, IM0 = V_CC, V_CC: 4-bit bus mode

RS/CS*

1

I

MPU

Selects the HD66717 during clock-synchronized serial

mode:

Low: HD66717 is selected and can be accessed

High: HD66717 is not selected and cannot be accessed

Selects the registers during 4- or 8-bit bus mode:

Low: Instruction register (write); busy flag and address

counter (read)

High: Data registers (write/read)

RW/SDA

E/SCL

1

I/O, I MPU

Inputs serial (receive) data and outputs the acknowledge

bit during I²C bus mode; Inputs serial (receive) data during

clock-synchronous serial mode; selects read/write during 4-

or 8-bit bus mode:

Low: Write

High: Read

Inputs serial clock pulses during I²C bus mode and clock-

synchronized serial mode; enables data read/write during

4- or 8-bit bus mode

1

4

I

MPU

DB7,

DB6,

DB5/ID5

DB4/ID4

I, I/O MPU

Inputs the HD66717's identification code (ID5, ID4) during

I²C bus mode and clock-synchronized serial mode;must be

fixed to high or low (DB7 and DB6…).

Four high-order bidirectional data bus pins for tristate data

transfer during 8-bit bus mode.

Bidirectional data bus pins during 4-bit bus mode.

DB3/ID3,

DB2/ID2,

DB1/ID1,

DB0/ID0,

4

2

I, I/O MPU

Inputs the HD66717's identification code (ID3 to ID0)

during I²C bus mode and clock-synchronized serial mode;

must be fixed to high or low.

Four low-order bidirectional data bus pins for tristate data

transfer during 8-bit bus mode.

Must be left disconnected during 4-bit bus mode since they

are not used.

COMS1,

COMS2

O

LCD

Common output signals for segment icon display.

460

HD66717

Table 1

Pin Functional Description (cont)

Number

of Pins I/O

Device

Interfaced with Function

Signal

COM1 to

COM32

32

O

LCD

Common output signals for character display: COM1 to

COM8 for the first line, COM9 to COM16 for the second

line, COM17 to COM24 for the third line, and COM25 to

COM32 for the fourth line. All the unused pins output

deselection waveforms. During sleep mode (SLP= 1) or

standby mode (STB = 1), all pins output V_CClevel.

SEG1 to

SEG60

60

1

O

I

LCD

Segment output signals for segment icon display and

character display. During sleep mode (SLP = 1) or standby

mode (STB = 1), all pins output V_CClevel.

ACOM

LCD

Common output signal for annunciator display; can drive

display statically between V_CCand AGND levels; outputs

V_CClevel while annunciator display is turned off (DA = 0).

ASEG1 to 10

ASEG10

LCD

Segment output signals for annunciator display; can drive

display statically between V_CCand AGND levels; output V_CC

level while annunciator display is turned off (DA = 0).

V2/V3

2

Open or

V2/V3 are voltage levels for the internal operational

Short-circuited amplifiers; can drive LCD with 1/4 bias when V2 and V3

are short-circuited and with 1/6 bias when they are left

disconnected.

V1OUT to

V5OUT

5

I or O —

Used for output from the internal operational amplifiers

when they are used (OPOFF = GND); when amplifiers'

driving capability is insufficient, attach a capacitor to

stabilize the output. Especially these capacitors for V1OUT

and V4OUT must be attached in 1/26 duty and 1/34 duty.

When the amplifiers are not used (OPOFF = V_CC); V1 to V5

voltages can be supplied to these pins externally.

VREFP,

VREF,

3

I

Open or

Adjusts the driving capability of the internal operational

Short-circuited amplifiers according to the LCD power supply voltage.

VREFM

LCD Power Supply

Voltage (V_CC–V_EE)

Pin Settings VREF,

VREFP, and VREFM

V_CC–V_EE: 3V–5V

V_CC–V_EE: 4V–6V

V_CC–V_EE: 5V–8V

V_CC–V_EE: 7V or more

Only VREF and VREFP shorted

All pins open

All pins shorted

Only VREF and VREFM shorted

V_EE

2

—

Power supply

GND power supply for LCD drive

V_CC–V_EE= 13V max.

V_CC/GND

AGND

10

2

—

Power supply

V_CC: +2.4V to +5.5V, GND (logic): 0V

Low level power supply for annunciator display; can adjust

contrast of annunciators; AGND ³ GND.

OSC1/

OSC2

2

—

Oscillation

resistor/clock

For R-C oscillation, connect an external resistor

For external clock supply, input clock pulses to OSC1.

461

HD66717

Table 1

Pin Functional Description (cont)

Number

of Pins I/O

Device

Interfaced with Function

Signal

Vci

2

I

Power supply

Inputs a reference voltage and supplies power to the

booster; generates the liquid crystal display drive voltage

from the operating voltage.

V5OUT2

1

O

V_EEpin/ Booster Voltage input to the Vci pin is boosted twice and output.

capacitance

When the voltage is boosted three times, the same

capacitance as that of C1–C2 should be connected here.

V5OUT3

C1/C2

1

2

O

V_EEpin

Voltage input to the Vci pin is boosted three times and

output.

—

Booster

capacitance

External capacitance should be connected here when

using the booster.

RESET*

EXM

1

I

—

Reset pin. Initializes the LSI when low.

MPU

External alternating signal used for annunciator display

during standby mode. If annunciator display is not used,

EXM must be fixed to V_CCor GND.

SFT

1

I

V_CCor GND

GND

Selects the SEG output pin arrangement: when SFT =

GND, SEG1 is connected to the far left of the LCD panel

and when SFT = V_CC, SEG60 is connected to the far left of

the LCD panel

OPOFF

TEST

Turns the internal operational amplifier off when OPOFF =

V_CC, and turns it on when OPOFF = GND. If the amplifier is

turned off (OPOFF = V_CC), V1 to V5 must be supplied to the

V1OUT to V5OUT pins.

Test pin. Must be grounded.

462

HD66717

Block Function Description

System Interface

The HD66717 has four types of system interfaces: I²C bus, clock-synchronized serial, 4-bit bus, and 8-bit

bus. The interface mode is selected by the IM1 and IM0 pins.

The HD66717 has two 8-bit registers: an instruction register (IR) and a data register (DR).

The IR stores instruction codes, such as display clear, return home, and display control, and address

information for the display data RAM (DDRAM), the character generator RAM (CGRAM), and the

segment RAM (SEGRAM). The IR can only be written to by MPU and cannot be read from.

The DR temporarily stores data to be written into DDRAM, CGRAM, SEGRAM, or annunciator. Data

written into the DR from the MPU is automatically written into DDRAM, CGRAM, SEGRAM, or

annunciator by an internal operation. The DR is also used for data storage when reading data from

DDRAM, CGRAM, or SEGRAM. When address information is written into the IR, data is read and then

stored into the DR from DDRAM, CGRAM, or SEGRAM by an internal operation. Data transfer between

the MPU is then completed when the MPU reads the DR. After the read, data in DDRAM, CGRAM, or

SEGRAM at the next address is sent to the DR for the next read from the MPU.

These two registers can be selected by the register select (RS) signal in the 4/8-bit bus interface, and by

the RS bit in I²C bus or clock-synchronized serial interface (Table 2).

Busy Flag (BF)

When the busy flag is 1, the HD66717 is in the internal operation mode, and the next instruction will not

be accepted. When RS = low and R/W = high in 4/8-bit bus mode (Table 2), the busy flag is output from

DB7. The next instruction must be written after ensuring that the busy flag is 0. The busy flag cannot be

read in I²C bus mode or clock-synchronized serial mode; data must be transferred in appropriate timing

considering instruction execution times.

Address Counter (AC)

The address counter (AC) assigns addresses to DDRAM, CGRAM, or SEGRAM. When the address set

instruction is written into the IR, the address information is sent from the IR to the AC. Selection of

DDRAM, CGRAM, and SEGRAM is also determined concurrently by the instruction.

After writing into (reading from) DDRAM, CGRAM, or SEGRAM, the AC is automatically incremented

by 1 (or decremented by 1). The AC contents are then output to DB0 to DB6 when RS = low and R/W =

high in 4/8-bit bus mode (Table 2).

463

HD66717

Table 2

Register Selection

RS

0

R/W

Operation

0

1

0

1

IR write as an internal operation (display clear, etc.)

0

Read busy flag (DB7) read and address counter (DB0 to DB6) (4/8-bit bus interface)

DR write as an internal operation (DR to DDRAM, CGRAM, SEGRAM, or annunciator)

1

DR read as an internal operation (DDRAM, CGRAM, or SEGRAM to DR)

(4/8-bit bus interface)

Display Data RAM (DDRAM)

Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its capacity is 60 ×

8 bits, or 60 characters, which is equivalent to an area of 12 characters × 5 lines. Any number of display

lines (LCD drive duty ratio) from 1 to 4 can be selected by software. Here, assignment of DDRAM

addresses is the same for all display modes (Table 3). The line to be displayed at the top of the display

(display-start line) can also be selected by register settings. See Table 4.

MSB

AC 6

LSB

Address

counter

(AC)

AC5 AC4 AC3 AC2 AC1 AC0

Example : DDRAM address 4A

1

0

1

0

1

0

Figure 1 Address Counter and DDRAM Address

DDRAM Addresses and Display Positions

Table 3

Display

Line

1st

2nd

3rd

4th

5th

6th

7th

8th

9th

10th 11th 12th

Char. Char. Char. Char. Char. Char. Char. Char. Char. Char. Char. Char.

1st

2nd

3rd

4th

5th

00

10

20

30

40

01

11

21

31

41

02

12

22

32

42

03

13

23

33

43

04

14

24

34

44

05

15

25

35

45

06

16

26

36

46

07

17

27

37

47

08

18

28

38

48

09

19

29

39

49

0A

1A

2A

3A

4A

0B

1B

2B

3B

4B

Note: Char. indicates character position.

464

HD66717

Table 4

Display-Line Modes, Display-Start Line, and DDRAM Addresses

Display-Start Lines

Display-

Duty

1st Line

2nd Line

3rd Line

4th Line

5th Line

Line Mode Ratio Common Pins (SN = 000) (SN = 001) (SN = 010) (SN = 011) (SN = 100)

1-line

(NL = 00)

1/10

1/18

1/26

COM1–COM8

00H–0BH

10H–1BH

20H–2BH

30H–3BH

40H–4BH

2-line

(NL = 01)

COM1–COM8

00H–0BH

10H–1BH

20H–2BH

30H–3BH

40H–4BH

00H–0BH

COM9–COM16 10H–1BH

COM1–COM8 00H–0BH

COM9–COM16 10H–1BH

COM17–COM24 20H–2BH

3-line

(NL = 10)

10H–1BH

20H–2BH

30H–3BH

20H–2BH

30H–3BH

40H–4BH

30H–3BH

40H–4BH

00H–0BH

40H–4BH

00H–0BH

10H–1BH

4-line

(NL = 11)

1/34

COM1–COM8

00H–0BH

10H–1BH

20H–2BH

30H–3BH

40H–4BH

20H–2BH

30H–3BH

40H–4BH

00H–0BH

30H–3BH

40H–4BH

00H–0BH

10H–1BH

40H–4BH

00H–0BH

10H–1BH

20H–2BH

COM9–COM16 10H–1BH

COM17–COM24 20H–2BH

COM25–COM32 30H–3BH

Character Generator ROM (CGROM)

The character generator ROM generates 5 × 8-dot character patterns from 8-bit character codes (Table 5).

It can generate 240 5 × 8-dot character patterns. User-defined character patterns are also available using a

mask-programmed ROM (see the Modifying Character Patterns section.)

Character Generator RAM (CGRAM)

The character generator RAM of 32 × 5 bits allows the user to redefine the character patterns for user

fonts. In the case of 5 × 8-dot characters, up to four fonts may be redefined.

Write the character codes at addresses 00H to 03H into DDRAM to display the character patterns stored

in CGRAM.

Segment RAM (SEGRAM)

The segment RAM is used to enable control of segments such as an icon and a mark by the user program.

Segments and characters are driven by a multiplexing drive method.

SEGRAM has a capacity of 8 × 5 bits, for controlling the display of a maximum of 40 icons and marks.

While COMS1 and COMS2 outputs are being selected, SEGRAM is read and segments (icons and marks)

are displayed by a multiplexing drive method (20 segments each during COMS1 and COMS2 selection).

Bits in SEGRAM corresponding to segments to be displayed are directly set by the MPU, regardless of

the contents of DDRAM and CGRAM.

465

HD66717

Timing Generation Circuit

The timing generation circuit generates timing signals for the operation of internal circuits such as

DDRAM, CGROM, CGRAM, and SEGRAM. RAM read timing for display and internal operation timing

by MPU access are generated separately to avoid interfering with each other. Therefore, when writing

data to DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas

other than the display area.

Cursor/Blink Control Circuit

The cursor/blink (or white-black inversion) control is used to produce a cursor or a flashing area on the

display at a position corresponding to the location stored in the address counter (AC).

For example (Figure 2), when the address counter is 08H, a cursor is displayed at a position

corresponding to DDRAM address (08)H.

Multiplexing Liquid Crystal Display Driver Circuit

The multiplexing liquid crystal display driver circuit consists of 34 common signal drivers (COM1 to

COM32, COMS1, COMS2) and 60 segment signal drivers (SEG1 to SEG60). When the number of lines

are selected by a program, the required common signal drivers automatically output drive waveforms,

while the other common signal drivers continue to output deselection waveforms.

Character pattern data is sent serially through a 60-bit shift register and latched when all needed data has

arrived. The latched data then enables the segment signal drivers to generate drive waveform outputs.

The shift direction of 60-bit data can be selected by the SFT pin; select the direction appropriate to the

device mounting configuration.

When multiplexing drive is not used, or during standby or sleep mode, all common and segment signal

drivers output the V_CClevel, halting display.

Annunciator Driver Circuit

The static annunciator drivers, which are specially used for displaying icons and marks, consists of 1

common signal driver (ACOM) and 10 segment signal drivers (ASEG1 to ASEG10). Since this driver

circuit operates at the logic operating voltage (V_CC–AGND), the LCD drive power supply circuit is not

necessary, and low-power consumption can be achieved. It is suitable for mark indication during system

standby because of its drive capability during standby and sleep modes. When multiplexing drive is not

used, or during standby or sleep mode, all common and segment signal drivers output the V_CClevel,

halting display.

466

HD66717

Booster

The booster doubles or triples a voltage input to the Vci pin. With this function, both the internal logic

units and LCD drivers can be controlled with a single power supply.

Oscillator

The HD66717 can provide R-C oscillation simply by adding an external oscillation resistor between the

OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size, and

frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be

supplied externally. Since R-C oscillation is halted during standby mode, current consumption can be

reduced.

V-Pin Voltage-Followers

A voltage-follower for each voltage level (V1 to V5) reduces current consumption by the LCD drive

power supply circuit. No external resistors are required because of the internal bleeder-resistor, which

generates different levels of LCD drive voltage. The voltage-followers can be turned off while

multiplexing drive is not being used.

Contrast-Adjuster

The contrast-adjuster can adjust LCD contrast by varying LCD drive voltage by software. This function is

suitable for selecting appropriate brightness of the LCD or for temperature compensation.

Display position

DDRAM address

1

2

3

4

5

6

7

8

9

10 11 12

00 01 02 03 04 05 06 07 08 09 0A 0B

Cursor position

Note: The cursor/blink or white-black inversion control is

also active when the address counter indicates the

CGRAM or SEGRAM. However, it has no effect on the

display.

Figure 2 Cursor Position and DDRAM Address

467

HD66717

Table 5

Relation between Character Codes and Character Patterns (ROM code: A03)

Upper

bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Lower

bits

CG

RAM

(1)

xxxx 0000

CG

RAM

(2)

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

CG

RAM

(3)

CG

RAM

(4)

CG

RAM

(1)

CG

RAM

(2)

CG

RAM

(3)

CG

RAM

(4)

CG

RAM

(1)

CG

RAM

(2)

CG

RAM

(3)

CG

RAM

(4)

CG

RAM

(1)

CG

RAM

(2)

CG

RAM

(3)

CG

RAM

(4)

468

HD66717

Table 6

Relation between Character Codes and Character Patterns (ROM code: A13)

Upper

Lower

bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

CG

RAM

(1)

xxxx 0000

CG

xxxx 0001 RAM

(2)

CG

xxxx 0010

xxxx 0011

RAM

(3)

CG

RAM

(4)

CG

xxxx 0100 RAM

(1)

CG

xxxx 0101

xxxx 0110

RAM

(2)

CG

RAM

(3)

CG

xxxx 0111 RAM

(4)

CG

xxxx 1000

RAM

(1)

CG

xxxx 1001 RAM

(2)

CG

xxxx 1010

xxxx 1011

RAM

(3)

CG

RAM

(4)

CG

xxxx 1100 RAM

(1)

CG

xxxx 1101

xxxx 1110

RAM

(2)

CG

RAM

(3)

CG

xxxx 1111 RAM

(4)

Note : This A13 font pattern is an upside-down pattern of A03.

470

HD66717

Modifying Character Patterns

•

Character pattern development procedure

The following operations correspond to the numbers listed in Figure 3:

a. Determine the correspondence between character codes and character patterns.

b. Create a listing indicating the correspondence between EPROM addresses and data.

c. Program the character patterns into an EPROM.

d. Send the EPROM to Hitachi.

e. Computer processing of the EPROM is performed at Hitachi to create a character pattern listing,

which is sent to the user.

f. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and

samples are sent to the user for evaluation. When it is confirmed by the user that the character

patterns are correctly written, mass production of the LSI will proceed at Hitachi.

471

HD66717

Hitachi

User

Start

Computer

processing

Determine

character patterns

1

2

3

4

Create character

pattern listing

Create EPROM

address data listing

5

Evaluate

character

patterns

Write EPROM

EPROM → Hitachi

No

OK?

Yes

Art work

M/T

Masking

Trial

Sample

evaluation

6

No

OK?

Yes

Mass

production

Figure 3 Character Pattern Development Procedure

472

HD66717

Programming Character Patterns

This section explains the correspondence between addresses and data used to program character patterns

in EPROM.

•

Programming to EPROM

The HD66717 character generator ROM can generate 240 5 × 8-dot character patterns. Table 7 shows

correspondence between the EPROM address data and the character pattern.

Handling Unused Character Patterns

1. EPROM data outside the character pattern area: This is ignored by the character generator ROM for

display operation so any data is acceptable.

2. EPROM data in CGRAM area: Always fill with zeros.

3. Treatment of unused user patterns in the HD66717 EPROM: According to the user application, these

are handled in either of two ways:

a. When unused character patterns are not programmed: If an unused character code is written into

DDRAM, all its dots are lit, because the EPROM is filled with 1s after it is erased.

b. When unused character patterns are programmed as 0s: Nothing is displayed even if unused

character codes are written into DDRAM. (This is equivalent to a space.)

Table 7

Example of Correspondence between EPROM Address Data and Character Pattern

(5 × 8 Dots)

EPROM Address

Data

O4 O3 O2 O1 O0

MSB

LSB

A3 A2 A1 A0

0

A11 A10A9 A8 A7 A6 A5 A4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Character code

Line position

“0”

Notes: 1. EPROM addresses A11 to A4 correspond to a character code.

2. EPROM addresses A2 to A0 specify the line position of the character pattern. EPROM address

A3 should be set to 0.

3. EPROM data O4 to O0 correspond to character pattern data.

4. Areas which are lit (indicated by shading) are stored as 1, and unlit areas as 0.

5. The eighth raster-row is also stored in the CGROM, and should also be programmed. If the

eighth raster-row is used for a cursor, this data should all be set to zero.

6. EPROM data bits O7 to O5 are invalid. 0 should be written in all bits.

473

HD66717

Table 8

Example of Relationships between Character Code (DDRAM) and Character Pattern

(CGRAM Data)

Character code (DDRAM data)

D7 D6 D5 D4 D3 D2 D1 D0

CGRAM address

CGRAM data

MSB

LSB

A4 A3 A2 A1 A0 O7 O6 O5 O4 O3 O2 O1 O0

0

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*

1

0

1

0

1

0

1

0

1

0

(Don't care)

Character

pattern

(1)

0

*

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*

1

0

1

0

1

0

1

0

1

0

(Don't care)

Character

pattern

(4)

Notes: 1. The lower 2 bits of the character code correspond to the upper two bits of the CGRAM address

(2 bits: 4 types).

2. CGRAM address bits 0 to 2 designate the character pattern raster-row position. The 8th raster-

row is the cursor position and its display is formed by a logical OR with the cursor.

3. The upper three bits of the CGRAM data are invalid; use the lower five bits.

4. When the upper four bits (bits 7 to 4) of the character code are 0, CGRAM is selected.

Bits 3 and 2 of the character code are invalid (*). Therefore, for example, the character codes

(00)H and (08)H correspond to the same CGRAM address.

5. A set bit in the CGRAM data corresponds to display selection, and 0 to non-selection.

* Indicates no effect.

474

HD66717

Table 9

Correspondence between Segment Display SEGRAM Addresses (ASEG) and Driver

Signals

Segment Signals

ASEG Address

Common

Signal

MSB

LSB D7

D6

D5

D4

D3

D2

D1

D0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*

SEG1,

SEG2,

SEG3,

SEG4,

SEG5,

COMS1

SEG21, SEG22, SEG23, SEG24, SEG25,

SEG41 SEG42 SEG43 SEG44 SEG45

*

SEG6,

SEG7,

SEG8,

SEG9,

SEG10, COMS1

SEG26, SEG27, SEG28, SEG29, SEG30,

SEG46 SEG47 SEG48 SEG49 SEG50

SEG11, SEG12, SEG13, SEG14, SEG15, COMS1

SEG31, SEG32, SEG33, SEG34, SEG35,

SEG51 SEG52 SEG53 SEG54 SEG55

SEG16, SEG17, SEG18, SEG19, SEG20, COMS1

SEG36, SEG37, SEG38, SEG39, SEG40,

SEG56 SEG57 SEG58 SEG59 SEG60

SEG1,

SEG2,

SEG3,

SEG4,

SEG5,

COMS2

SEG21, SEG22, SEG23, SEG24, SEG25,

SEG41 SEG42 SEG43 SEG44 SEG45

SEG6,

SEG7,

SEG8,

SEG9,

SEG10, COMS2

SEG26, SEG27, SEG28, SEG29, SEG30,

SEG46 SEG47 SEG48 SEG49 SEG50

SEG11, SEG12, SEG13, SEG14, SEG15, COMS2

SEG31, SEG32, SEG33, SEG34, SEG35,

SEG51 SEG52 SEG53 SEG54 SEG55

SEG16, SEG17, SEG18, SEG19, SEG20, COMS2

SEG36, SEG37, SEG38, SEG39, SEG40,

SEG56 SEG57 SEG58 SEG59 SEG60

Notes: 1. When the SFT pin is grounded, the SEG1 pin output is connected to the far left of the LCD

panel, and when the SFT pin is high, the SEG60 pin output is connected to the far left.

2. SEG1 to SEG20 data is identical to SEG21 to SEG40 and SEG41 to SEG60 data.

3. The lower five bits (D4 to D0) of SEGRAM data determine on or off display of each segment. A

segment is selected (turned on) when the corresponding data is 1, and is deselected (turned

off) when the corresponding data is 0. The upper three bits (D7 to D5) are invalid.

475

HD66717

Table 10

Correspondence between Annunciator Display Addresses (AAN) and Driver Signals

Annunciator Segment Signals

AAN Address

LSB D7

Common

Signal

MSB

D6

D5

D4

D3

D2

D1

D0

0

1

0

1

0

ASEG1 ASEG1 ASEG2 ASEG2 ASEG3 ASEG3 ASEG4 ASEG4 ACOM

Blink Data Blink Data Blink Data Blink Data

ASEG5 ASEG5 ASEG6 ASEG6 ASEG7 ASEG7 ASEG8 ASEG8 ACOM

Blink

ASEG9 ASEG9 ASEG10 ASEG10

Blink Data Blink Data

Data

Blink

Data

Blink

Data

Blink

Data

—

*

—

*

—

*

—

*

ACOM

Notes: 1. The annunciator is turned on when the corresponding even bit (data) is 1, and is turned off

when 0.

2. The turned-on annunciator blinks when the corresponding odd bit (blink) is 1. Blinking is

provided by repeatedly turning on the annunciator for 32 frames and then turning it off for the

next 32 frames.

476

HD66717

Instructions

Outline

Only the instruction register (IR) and the data register (DR) of the HD66717 can be controlled by the

MPU. Before starting internal operation of the HD66717, control information is temporarily stored in

these registers to allow interfacing with various peripheral control devices or MPUs which operate at

different speeds. The internal operation of the HD66717 is determined by signals sent from the MPU.

These signals, which include register selection (RS), read/write (R/W), and the data bus (DB0 to DB7),

make up the HD66717 instructions (Table 17). There are four categories of instructions that:

•

Control display

Control power management

Set internal RAM addresses

Perform data transfer with internal RAM

Normally, instructions that perform data transfer with internal RAM are used the most. However, auto-

incrementation by 1 (or auto-decrementation by 1) of internal HD66717 RAM addresses after each data

write can lighten the program load of the MPU.

While an instruction is being executed for internal operation, or during reset, no instruction other than the

busy flag/address read instruction can be executed.

Because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0

before sending another instruction from the MPU. If an instruction is sent without checking the busy flag,

the time between the first instruction issue and next instruction issue must be longer than the instruction

execution time itself. Refer to Table 16 for the list of each instruction execution cycles (clock pulses).

The execution time depends on the operating clock frequency (oscillation frequency).

477

HD66717

Instruction Description

Status Read

The status read instruction (Figure 4) reads the busy flag (BF) indicating that the system is now internally

operating on a previously received instruction. If BF is 1, the internal operation is in progress. The next

instruction will not be accepted until BF is reset to 0. Check the BF status before the next write operation.

At the same time, the value of the address counter in binary AAAAAAA is read out. This address counter

is used by both CGRAM, DDRAM, and SEGRAM addresses, and its value is determined by the previous

instruction.

Clear Display

The clear display instruction (Figure 5) writes space code (20)H (character pattern for character code

(20)H must be a blank pattern) into all DDRAM addresses. It then sets DDRAM address 0 into the

address counter. It also sets I/D to 1 (increment mode) in entry mode.

RS R/W DB7

BF

DB0

A

0

1

A

Figure 4 Status Read Instruction

RS R/W DB7

DB0

1

0

Figure 5 Clear Display Instruction

478

HD66717

Return Home

The return home instruction (Figure 6) sets DDRAM address 0 into the address counter. The DDRAM

contents do not change.The cursor or blinking goes to the top left of the display.

Start Oscillator

The start oscillator instruction (Figure 7) re-starts the oscillator from a halt state in standby mode. After

issuing this instruction, wait at least 10 ms for oscillation to become stable before issuing the next

instruction. (Refer to the Standby Mode section.)

Entry Mode

The entry mode instruction (Figure 8) includes the I/D and OSC bits.

I/D: Increments (I/D = 1) or decrements (I/D = 0) the DDRAM address by 1 when a character code is

written into or read from DDRAM.The cursor or blinking moves to the right when incremented by 1 and

to the left when decremented by 1. The same applies to writing and reading of CGRAM and SEGRAM.

OSC: Divides the external clock frequency by four (OSC = 1) using the resulting clock as an internal

operating clock. The execution time for this instruction and subsequent ones is therefore quadrupled. The

execution time of clearing this bit (OSC = 0) is also quadrupled. (For application of this instruction, refer

to the Partial-Display-Off Function section.)

RS R/W DB7

DB0

0

1

Figure 6 Return Home Instruction

RS R/W DB7

DB0

1

0

1

Figure 7 Start Oscillator Instruction

479

HD66717

Cursor Control

The cursor control (Figure 9) includes the B/W, C, and B bits.

B/W: When B/W is 1, the character at the cursor position is cyclically (every 32 frames) displayed with

black-white inversion.

C: The cursor is displayed on the 8th raster-row when C is 1. The cursor is displayed using 5 dots in the

8th raster-row for 5 × 8-dot character font.

B: The character indicated by the cursor blinks when B is 1. The blinking is displayed as switching

between all black dots and displayed characters every 32 frames. The cursor and blinking can be set to

display simultaneously. When LC and B = 1, the blinking is displayed as switching between all white

dots and displayed characters.

Figure 10 shows cursor control examples.

RS R/W DB7

DB0

0

1

I/D OSC

Figure 8 Entry Mode Instruction

RS R/W DB7

DB0

B

0

1

B/W

C

Figure 9 Cursor Control Instruction

480

HD66717

Display On/Off Control

The display on/off control instruction (Figure 11) includes DC, DS, and LC bits.

DC: The character display is on when DC is 1 and off when DC is 0. When off, the display data remains

in DDRAM, and can be displayed instantly by setting DC to 1.

DS: When DS = 1, segment display for icons and marks that is controlled by the multiplexing drive

method is turned on and when DS = 0, it is turned off.

When both DC and DS = 0, multiplexing drive is halted, setting the outputs from SEG1 to SEG60, COM1

to COM32, and COMS1 and COMS2 to V_CClevel to turn off the display. This can suppress current for

LCD charging or discharging due to LCD driving operations.

LC: When LC = 1, a cursor attribute is assigned to the line that contains the address counter (AC) value.

Cursor mode can be selected with the B/W, C, and B bits. Refer to the Line-Cursor Display section.

Alternating display

(every 32 frames)

i) White-black inverting display example

Alternating

display

ii) 8th raster-row

cursor display

ii) Blink display example

Figure 10 Cursor Control Examples

RS R/W DB7

DB0

0

1

0

DC DS LC

Figure 11 Display On/Off Instruction

481

HD66717

Power Control

The cursor control instruction (Figure 12) includes the AMP, SLP, and STB bits.

AMP: When AMP = 1, each voltage-follower for V1 to V5 pins and the booster are turned on. When

AMP = 0, current consumption can be reduced while character or segment display controlled by the

multiplexing drive method is not being used.

SLP: When SLP = 1, the HD66717 enters sleep mode, where all the internal operations are halted except

for annunciator display function and the R-C oscillator, thus reducing current consumption. Refer to the

Sleep Mode section. Only the following instructions can be executed during sleep mode.

1. Annunciator address set (AAN)

2. Annunciator data write

3. Annunciator display on or off (DA = 1 or 0)

4. Voltage-follower on or off (AMP = 1 or 0)

5. Standby mode set (STB = 1)

6. Sleep mode cancel (SLP = 0)

During sleep mode, other RAM data and instructions cannot be updated but they are retained.

STB: When STB = 1, the HD66717 enters standby mode, where the device completely stops, halting all

the internal operations including the internal R-C oscillator and no external clock pulses are supplied.

However, annunciator display alone is available when the alternating signal for annunciator-driving

signals is supplied to the EXM pin. When the annunciator display is not needed, make sure to turn off

display (DA = 0). Refer to the Standby Mode section. Only the following instructions can be executed

during standby mode.

1. Annunciator address set (AAN)

2. Annunciator data write

3. Annunciator display on or off (DA = 1 or 0)

4. Voltage-follower on or off (AMP = 1 or 0)

5. Start oscillator

6. Standby mode cancel (STB = 0)

During standby mode, RAM data and other instructions may be lost; they must be set again after standby

mode is cancelled.

RS R/W DB7

DB0

0

1

AMP SLP STB

Figure 12 Power Control Instruction

482

HD66717

Display Control

The display control instruction (Figure 13) includes the NL and DL bits.

NL1, NL0: Designates the number of display lines. This value determines the LCD drive multiplexing

duty ratio (Table 11). The address assignment is the same for all display line modes.

DL3–DL1: Doubles the height of characters on a specified line. The first, second, or third line is doubled

in height when DL1, DL2, or DL3 = 1, respectively. Two lines can be simultaneously doubled in a 4-line

display. Refer to the Double-Height Display section.

RS R/W DB7

DB0

0

1

NL1 NL0 DL3 DL2 DL1

Figure 13 Display Control Instruction

NL Bits and Display Lines

Table 11

NL1

0

NL0

0

Number of Display Lines

LCD Drive Multiplexing Duty Ratio

1

2

3

4

1/10

1/18

1/26

1/34

0

1

0

1

483

HD66717

Contrast Control

The contrast control instruction (Figure 14) includes the SN and CT bits.

SN2: Combined with the SN1 and SN0 bits described in the Scroll Control section to select the first line

to be scrolled (display-start line).

CT3–CT0: Controls the LCD drive voltage (potential difference between V_CCand V5) to adjust contrast

(Figure 15 and Table 12). Refer to the Contrast Adjuster section.

RS R/W DB7

DB0

0

1

0

SN2 CT3 CT2 CT1 CT0

Figure 14 Contrast Control Instruction

HD66717

V_CC

R

V1

+

–

R

V2

+

–

R

V3

+

–

R

V4

+

–

R

V5

+

–

VR

V_EE

Figure 15 Contrast Adjuster

484

HD66717

Scroll Control

The scroll control instruction (Figure 16) includes the SN and SL bits.

SN1, SN0: Combined with the SN2 bit described in the Contrast Control section to select the top line to

be displayed (display-start line) through the data output from the COM1 pin (Table 13). After first five

lines are displayed from the top line, the cycle is repeated and scrolling continues.

Table 12

CT Bits and Variable Resistor Value of Contrast Adjuster

CT3

0

CT2

0

CT1

0

CT0

0

Variable Resistor Value (VR)

6.4 x R

0

1

6.0 x R

0

1

0

5.6 x R

0

1

5.2 x R

0

1

0

4.8 x R

0

1

0

1

4.4 x R

0

1

0

4.0 x R

0

1

3.6 x R

1

0

3.2 x R

1

0

1

2.8 x R

1

0

1

0

2.4 x R

1

0

1

2.0 x R

1

0

1.6 x R

1

0

1

1.2 x R

1

0

0.8 x R

1

0.4 x R

RS R/W DB7

DB0

1 SN1 SN0 SL2 SL1 SL0

0

1

Figure 16 Scroll Control Instruction

485

HD66717

SL2–SL0: Selects the top raster-row to be displayed (display-start raster-row) in the display-start line

specified by SN2 to SN0. Any raster-row from the first to eighth can be selected (Table 14). This function

is used to perform vertical smooth scroll together with SN2 to SN0. Refer to the Vertical Smooth Scroll

section.

Table 13

SN Bits and Display-Start Lines

SN2

SN1

0

SN0

0

Display-Start Line

1st line

0

1

0

1

2nd line

1

0

3rd line

1

4th line

0/1

5th line

Table 14

SN Bits and Display-Start Raster-Rows

SL2

0

SN1

0

SL0

0

Display-Start Raster-Row

1st raster-row

0

1

2nd raster-row

3rd raster-row

4th raster-row

0

1

0

1

0

5th raster-row

1

0

1

6th raster-row

1

0

7th raster-row

1

8th raster-row

486

HD66717

Annunciator/SEGRAM Address Set

The annunciator/SEGRAM address set instruction (Figure 17) includes the DA and A bits.

DA: Turns annunciator display on or off. When DA = 1, annunciator display is turned on and driven

statically. When DA = 0, annunciator display is turned off with ASEG1 to ASEG10 and ACOM pins held

to V_CClevel.

The internal operating clock supply is halted during standby mode; make sure to turn off display (DA =

0) if the external alternating signal is not supplied. Refer to the Segment Display and Annunciator

Display section and the Standby Mode section.

AAAA: Used for setting the SEGRAM address in the address counter (AC) or for setting an annunciator

address. The SEGRAM addresses range from 1000H to 1111H (8 addresses), while the annunciator

addresses range from 0000H to 0010H (3 addresses).

The annunciator address is directly set without using the address counter, and consequently must be

updated for each access. The annunciator address can be set even during sleep and standby modes.

Once the SEGRAM address is set, data in the SEGRAM can be accessed consecutively since the address

counter is automatically incremented or decremented by one according to the I/D bit setting after each

access. The SEGRAM address cannot be set during sleep or standby mode.

RS R/W DB7

DB0

A

0

1

0

DA

A

Figure 17 Annunciator/SEGRAM Address Set Instruction

487

HD66717

CGRAM Address Set

The CGRAM address set instruction (Figure 18) includes the A bits.

AAAAA: Used for setting the CGRAM address in the address counter (AC). The CGRAM addresses

range from 00H to 1FH (32 addresses) (Table 15).

Once the CGRAM address is set, data in the CGRAM can be accessed consecutively since the address

counter is automatically incremented or decremented according to the I/D bit setting after each access.

The CGRAM address cannot be set during sleep or standby mode.

RS R/W DB7

DB0

A

0

1

0

1

A

Figure 18 CGRAM Address Set Instruction

CGRAM Addresses and Character Codes

Table 15

Displayed Character

1st character

CGRAM Address

00H to 07H

Character Codes

00H

01H

02H

03H

2nd character

3rd character

08H to 0FH

10H to 17H

4th character

18H to 1FH

488

HD66717

DDRAM Address Set

The DDRAM address set instruction (Figure 19) includes the A bits.

AAAAAAA: Used for setting the DDRAM address in the address counter (AC). The DDRAM addresses

range from 00H to 4BH (60 addresses) (Table 16).

Once the DDRAM address is set, data in the DDRAM can be accessed consecutively since the address

counter is automatically incremented or decremented according to the I/D bit setting after each access.

Here, invalid addresses are automatically skipped. The DDRAM address cannot be set during sleep or

standby mode.

RS R/W DB7

DB0

A

0

1

0

1

0

A

Upper bits

Lower bits

0

1

A

Figure 19 DDRAM Address Set Instruction

Table 16

DDRAM Addresses and Invalid Addresses

Displayed Line

1st line

DDRAM Address

00H to 0BH

10H to 1BH

20H to 2BH

30H to 3BH

40H to 4BH

Invalid Addresses

0CH to 0FH

2nd line

1CH to 1FH

3rd line

2CH to 2FH

4th line

3CH to 3FH

5th line

4CH and subsequent addresses

489

HD66717

Write Data to RAM

The write data to RAM instruction (Figure 20) writes 8-bit data to annunciator or DDRAM, or lower 5-bit

data to SEGRAM or CGRAM that is selected by the previous specification of the address set instruction

(annunciator/SEGRAM address set, CGRAM address set, or DDRAM address set).

After a write, the address is automatically incremented or decremented by 1 according to the I/D bit

setting in the entry mode instruction.

The annunciator address is not automatically updated; it must be specifically updated to write data to a

different address. During sleep and standby modes, DDRAM, CGRAM, or SEGRAM cannot be accessed.

Read Data from RAM

The read data from RAM instruction (Figure 21), reads 8-bit data from DDRAM, or 5-bit binary data

from CGRAM or SEGRAM that is selected by the previous specification of the address set instruction

(SEGRAM address set, CGRAM address set, or DDRAM address set). The unused upper three bits of

CGRAM or SEGRAM data are read as 000; annunciator data cannot be read. If no address is specified by

the address set instruction just before this instruction, the first data read will be invalid. When executing

serial read instructions, the next address is normally read from the next address.

After a read, the address is automatically incremented or decremented by 1 according to the I/D bit

setting in the entry mode instruction.

Table 17 lists the above instructions.

RS R/W DB7

DB0

D

1

0

D

Figure 20 Write Data to RAM Instruction

RS R/W DB7

DB0

D

1

D

Figure 21 Read Data from RAM Instruction

490

HD66717

Table 17

Instruction List

Code

Instruction No. R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description

Execution

Cycle *¹

Status

SR

1

0

BF

AC AC AC AC AC AC AC Reads busy flag (BF),

which indicates internal

0

operations are being

performed, and reads

address counter (AC).

Clear

CL

0

1

Clears entire display and

310

display

sets DDRAM address 0 in

address counter.

Return

home

CH

OS

EM

0

1

0

1

Sets DDRAM address 0 in 10

address counter.

Start

oscillator

1

Starts oscillation during

standby mode.

—

Entry

mode set

I/D

OSC Sets address update

direction after RAM access

(I/D), and system clock

division (OSC).

10

Cursor

control

CR

DO

PW

0

1

0

1

B/W

C

B

Sets black-white inverting 10

cursor (B/W), 8th raster-

row cursor (C), and blink

cursor (B).

Display

on/off

control

DC DS LC

Sets character display

on/off (DC), segment

display on/off (DS), and

line-cursor on/off (LC).

10

Power

control

AMP SLP STB Turns on voltage-follower 10

and booster (AMP), and

sets sleep mode (SLP) and

standby mode (STB).

Display

control

DC

CN

SC

0

1

0

1

0

1

0

1

0

NL1 NL0 DL3 DL2 DL1 Sets the number of display 10

lines (NL) and the line to be

doubled in height.

Contrast

control

SN2 CT3 CT2 CT1 CT0 Sets the display-start line 10

(SN2) and contrast-

adjusting value (CT).

Scroll

control

SN1 SN0 SL2 SL1 SL0 Sets the display-start line 10

(SN) and display-start

raster-row (SL).

Annunciator AS

/SEGRAM

address set

DA AAN/ AAN/ AAN/ AAN/ Turns on annunciator

A_SEG3A_SEG2A_SEG1A_SEG0display and sets

annunciator/SEGRAM

10

address.

CGRAM

address set

CA

DA

0

1

0

1

0

1

A_CG4A_CG3A_CG2A_CG1A_CG0Sets the initial CGRAM

10

address to the address

counter.

DDRAM

address set

(upper bits)

0

A_DD6A_DD5Sets the initial higher

DDRAM address to the

address counter.

DDRAM

address set

(lower bits)

A_DD4A_DD3A_DD2A_DD1A_DD0Sets the initial lower

DDRAM address to the

address counter.

491

HD66717

Table 17

Instruction List (cont)

Code

Instruction No. R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description

Execution

Cycle *¹

Write data WD

to RAM

0

1

Write data

Writes data to DDRAM,

CGRAM, SEGRAM, or

annunciator.

10

Read data RD

from RAM

1

Read data

Reads data from DDRAM, 10

CGRAM, or SEGRAM.

BF

I/D

= 1: Internally operating

= 1: Increment

AC: Address counter

I/D

= 0: Decrement

OSC = 1: System clock divided by four

B/W = 1: Black-white inverting cursor on

C

= 1: 8th raster-row cursor on

B

D

= 1: Blink cursor on

= 1: Display on

DC = 1: Character display on

LC = 1: Line containing AC given cursor attribute

DS = 1: Segment display on

SLP = 1: Sleep mode

AMP = 1: Voltage-follower and booster on

STB = 1: Standby mode

NL1,NL0:

Number of display lines [00: 1line (1/10 duty ratio), 01: 2 lines (1/18 duty ratio),

10: 3 lines (1/26 duty ratio),11:4 lines (1/34 duty ratio)]

DL3 – DL1: Double-height lines (DL1 = 1: 1st line, DL2 = 1: 2nd line, DL3 = 1: 3rd line)

CT3–CT0: Contrast adjustment

SN2 – SN0: Display-start line (000: 1st line, 001: 2nd line, 010: 3rd line, 011: 4th line, 100: 5th line)

SL2 – SL0: Display-start raster-row (000: 1st raster-row... 111: 8th raster-row)

DA = 1: Annunciator display on

AAN/A_SEG= 0000–0010: Annunciator address

AAN/A_SEG

= 1000–1111: SEGRAM address

ACG4–ACG0: CGRAM address (00000–11111)

ADD6–ADD0: DDRAM address (0000000–1001011)

Note: 1. Represented by the number of operating clock pulses; the execution time depends on the

supplied clock frequency or the internal oscillation frequency.

492

HD66717

Reset Function

Initializing by Internal Reset Circuit

The HD66717 is internally initialized by RESET input. During reset, the system executes the instructions

as described below. Here, the busy flag (BF) therefore indicates a busy state (BF = 1), accepting no

instruction or RAM data access from the MPU. Here, reset input must be held at least 10 ms.

After releasing power-on reset, clear display instruction is operated, so wait for 1,000 clock-cycles or

more.

Make sure to reset the HD66717 immediately after power-on reset in I²C bus mode.

1. Instruction set initialization

a. Clear display:

Writes 20H to DDRAM after releasing reset

b. Return home

Sets the address counter (AC) to 00H to select the DDRAM

c. Start oscillator

d. Entry mode

I/D = 1: Increment by 1

OSC = 0: Clock frequency not divided

e. Cursor control

B/W = 0: White-black inverting cursor off

C = 0: 8th raster-row cursor off

B = 0: Blink cursor off

f. Display on/off control

DC = 0: Character display off

DS = 0: Segment display off

LC = 0: Line-cursor off

g. Power control

AMP = 0: LCD power supply off

SLP = 0: Sleep mode off

STB = 0: Standby mode off

h. Display control

NL1, NL0 = 11: 4-line display (1/34 multiplexing duty ratio)

DL3–DL1 = 000: Double-height display off

i. Contrast adjust

CT = 0000: Weak contrast

j. Scroll control

SN2–SN0 = 000: First line displayed at the top

SL2–SL0 = 000: First raster-row displayed at the top of the first line

493

HD66717

k. Annunciator control

DA = 0: Annunciator display off

2. RAM data initialization

a. DDRAM

All addresses are initialized to 20H by the clear display instruction

b. CGRAM/SEGRAM

Not automatically initialized by reset input; must be initialized by software while display is off

(DC and DS = 0)

c. Annunciator data

Not automatically initialized by reset input; must be initialized by software while display is off

(DA= 0)

3. Output pin initialization

a. LCD driver output pins (SEG/COM, ASEG/ACOM): Outputs V_CClevel

b. Booster output pins (V5OUT2 and V5OUT3): Outputs GND level

c. Oscillator output pin (OSC2): Outputs oscillation signal

494

HD66717

Transferring Serial Data

I²C Bus Interface

Grounding the IM1 and IM0 pins (interface mode pins) allows serial data transfer conforming to the I²C

bus interface over the serial data line (SDA) and serial transfer clock line (SCL). Here, the HD66717

operates in an exclusive-receive slave mode.

The HD66717 initiates serial data transfer by transferring the first byte when a high SCL level at the

falling edge of the SDA input is sampled; it ends serial data transfer when a high SCL level at the rising

edge of the SDA input is sampled.

The HD66717 is selected when the higher six bits of the 7-bit slave address in the first byte transferred

from the master device match the 6-bit device identification code assigned to the HD66717. The

HD66717, when selected, receives the subsequent data strings. Any identification code can be assigned

by the DB5/ID5 to DB0/ID0 pins; select an appropriate code that is not assigned to any other slave

device. The higher four bits (ID5 to ID2) of this identification code is recommended as 0111. Two

different slave addresses must be assigned to a single HD66717 because the least significant bit (LSB) of

the slave address is used as a register select bit (RS): when RS = 0, an instruction can be issued and when

RS = 1, data can be written to a RAM. The eighth bit of the first byte (R/W bit) must be 0 since the

HD66717 exclusively receives data.

The ninth bit of the first byte is a receive-data acknowledge bit (ACK). When the received slave address

matches the device ID code, the HD66717 pulls down the ACK bit to a low level. Therefore, the ACK

output buffer is an open-drain structure, only allowing low-level output. However, the ACK bit is

undetermined immediately after power-on; make sure to initialize the LSI using the RESET* input.

After identifying the address in the first byte, the HD66717 receives the subsequent data as an HD66717

instruction or as RAM data. Having received 8-bit data normally, the HD66717 pulls down the ninth bit

(ACK) to a low level. Therefore, if the ACK is not returned, the data must be transferred again. Multiple

bytes of data can be consecutively transferred until the transfer-end condition is satisfied. Here, when the

serial data transfer rate is longer than that of the HD66717 instruction execution cycle, effective data

transfer is possible without retransmission (see Table 17, Instruction List). Note that the display-clear

instruction alone requires longer execution time than the others.

Table 18 illustrates the first bytes of I²C bus interface data and Figure 22 shows the I²C bus interface

timing sequence .

495

HD66717

Table 18

First Bytes of I²C Bus Interface Data

Transferred Bit String

First Byte

S

Bit 1

Bit 2

Bit 3

Bit 4

I²C slave address

A3 A2

Device ID code

Bit 5

Bit 6

A1

Bit 7

Bit 8

Bit 9

I²C bus system Transfer

start

R/W

ACK

A6

A5

A4

A0

HD66717

Transfer

start

RS

0

ACK

ID5

O

ID4

I

ID3

I

ID2

I

ID1

ID0

Transfer end

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Transfer start

1

2

3

4

5

6

7

8

SCL

(input)

MSB

SDA

(input)

ID5 ID4 ID3 ID2ID1ID0 RS "0"Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack

Device ID code

Slave address

RS

1st instruction

2nd instruction

Acknowledge

Instructions

Acknowledge

1st byte

a) Basic data transfer (receive) timing

1

2 3 4 5 6 7 8 9 101112 131415 161718 192021 222324 252627 282930 313233 343536

SCL

(input)

A

C

K

A

C

K

A

C

K

A

C

K

SDA

(input)

1st byte

Instruction 1

Instruction 2

Instrucation 3

S

P

Instruction 1 execution

time

Instruction 2 execution

time

Start

End

b) Consecutive data transfer timing

Note: Transfer the instruction 2 ACK after instruction 1 has been executed.

Figure 22 I²C Bus Interface Timing Sequence

496

HD66717

Clock-Synchronized Serial Interface

Setting the IM1 and IM0 pins (interface mode pins) to the GND and high levels, respectively, allows

standard clock-synchronized serial data transfer, using the chip select (CS*), SDA, and SCL lines. Here,

the HD66717 exclusively receives data.

The HD66717 initiates serial data transfer by transferring the start byte at the falling edge of the CS*

input. It ends serial data transfer at the rising edge of the CS* input.

The HD66717 is selected when the 6-bit chip address in the start byte transferred from the transmitting

device matches the 6-bit (device) identification code assigned to the HD66717. The HD66717, when

selected, receives the subsequent data strings. Any identification code can be assigned by the DB5/ID5 to

DB0/ID0 pins. Two different chip addresses must be assigned to a single HD66717 because the seventh

bit of the start byte is used as a register select bit (RS): when RS = 0, an instruction can be issued and

when RS = 1, data can be written to a RAM. The eighth bit of the start byte must be 0.

After receiving the start byte, the HD66717 receives the subsequent data as an HD66717 instruction or as

RAM data. Data is transferred with the MSB first. To transfer data consecutively, adjust the data transfer

rate so that the HD66717 can complete the current instruction before the eighth bit of the next instruction

is transferred. See Table 17, Instruction List. If the next instruction is received during execution of the

previous instruction, the next instruction will be ignored. Note that the display-clear instruction alone

requires longer execution time than the others.

Figure 23 shows the clock-synchronised serial interface timing sequence.

497

HD66717

Transfer start

Transfer end

CS*

(Input)

1

2

3

4

5

6

7

8

0

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

SCL

(Input)

MSB

SDA

ID5 ID4 ID3 ID2 ID1 ID0 RS

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

(Input)

Device

RS

1st instruction

2nd instruction

ID code

Start byte

Instruction

(a) Basic data transfer (receive) timing

CS*

(Input)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

Instruction 1

17 18 19

20 21 22 23 24

25 26 27 28 29 30 31 32

SCL

(Input)

SDA

Instruction 2

Instruction 3

1st byte

(Input)

Instruction 1 execution

time

Instruction 2 execution

time

Start

End

(b) Consecutive data transfer timing

Note: Adjust the transfer rate so that the HD66717 can complete instruction 1 before the 8th bit of

instruction 2 is transferred.

Figure 23 Clock-Synchronized Serial Interface Timing Sequence

498

HD66717

Transferring Parallel Data

Interface with an 8-Bit MPU

Eight-bit data can be transferred in parallel by setting the IM1 and IM0 pins to the V_CCand GND levels,

respectively (Figure 24). The HD66717 can interface directly with an 8-bit bus synchronized with the E

clock, or with an 8-bit MCU through an I/O port (Figure 25). When the number of I/O lines or chip

packaging size is limited, a 4-bit bus interface or even serial data transfer should be used.

RS

R/W

E

Internal operation

Internal signal

Not

Busy

DB7

Data

Busy

Instruction write

Busy flag check Busy flag check Busy flag check Instruction write

Figure 24 8-Bit Parallel Data Transfer Timing Sequence

I/O port interface

C0

C1

C2

E

RS

H8/325

^R/WHD66717

8

A0 - A7

DB0 - DB7

Figure 25 8-Bit MPU Interface

499

HD66717

Interface with a 4-Bit MPU

Four-bit data can be transferred in parallel by setting both the IM1 and IM0 pins to the V_CClevel (Figure

26). Four-bit data representing higher or lower bits of 8-bit instructions or 8-bit RAM data can be

transferred in that order.

The HD66717 can forcibly reset the counter that counts the number of higher and lower 4-bit data

transfers in a 4-bit bus interface. This function, called transfer-syncronization, can be performed by

writing a special instruction containing 0000 four consecutive times (Figure 27). For example, when a

data transfer sequence becomes disordered due to noise or some undesired factor, this function resets the

counter and thus enables resuming data transfer from the higher 4 bits. Using this function at specified

intervals prevents display-system crash.

RS

Internal operation

R/W

E

Internal signal

DB7

Not

Busy

Busy AC3

AC3

D7

D3

IR7 IR3

Instruction write

Busy flag check

Instruction write

Figure 26 4-Bit Parallel Data Transfer Timing Sequence

RS

R/W

E

Higher

Lower

0000

(1)

0000

(2)

0000

(3)

0000

(4)

DB7–

DB0

(4-bit data transfer synchronized)

Figure 27 4-Bit Data Transfer Synchronization

500

HD66717

Oscillator Circuit

The HD66717 can either be supplied with operating clock pulses externally (external clock mode) or

oscillate using an internal R-C oscillator and an external oscillator-resistor (internal oscillation mode), as

shown in Figure 28. An appropriate oscillator-resistor must be used to obtain the optimum clock

frequency according to the number of display lines (Table 18). Instruction execution times change in

proportion to the operating clock frequency or R-C oscillation frequency; MPU data transfer rate must be

appropriately adjusted (see Table 17, Instruction List). Figure 29 shows a sample LCD drive output

waveform, where 4-lines are displayed with 1/34 multiplexing duty ratio.

1) When an external clock is used

2) When an internal oscillator is used

The oscillator frequency can be

adjusted by oscillator resistance

(Rf). If Rf is increased or power

supply voltage is decreased, the

oscillator frequency decreases.

Clock

OSC1

Rf

OSC2

HD66717

Figure 28 Oscillator Circuit

Oscillation Frequency and LCD Frame Frequency

Table 19

1-Line Display 2-Line Display 3-Line Display 4-Line Display

NL1, NL0 = 00 NL1, NL0 = 01 NL1, NL0 = 10 NL1, NL0 = 11

Item

Multiplexing duty ratio

1/10

1/18

1/26

1/34

Oscillator resistance (R_f) V_CC= 3V 620 kΩ

300 kΩ

85 kHz

79 Hz

200 kΩ

120 kHz

77 Hz

150 kΩ

160 kHz

78Hz

CR oscillator frequency

Frame frequency

40 kHz

67 Hz

501

HD66717

1-line selection period

1

2

3

4

1

2

3

33

34

33

34

V_CC

V1

COM1

V4

V5

V_CC

V1

COM2

V4

V5

V_CC

V1

COMS2

COMS1

V4

V5

V_CC

V1

V4

V5

1 frame

Figure 29 LCD Drive Output Waveform Example (4-line display with 1/34 multiplexing duty

ratio)

502

HD66717

Power Supply for Liquid Crystal Display Drive

When External Power Supply and Internal Operational Amplifiers are Used

To supply LCD drive voltage directly from the external power supply without using the internal booster,

circuits should be connected as shown in Figure 30. Here, contrast can be adjusted through the CT bits of

the contrast-control instruction.

The HD66717 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce

current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal

drive voltages. Thus, potential differences between V_CCand V1 and between V_EEand V5 must be 0.4V or

greater. Note that the OPOFF pin must be grounded when using the operational amplifiers.

503

HD66717

OPOFF = GND

HD66717

V_CC

V _EE

V_CC

R

V1

V2

+

–

SEG1–SEG60

V2

V3

+

–

LCD

multiplexing

driver

V3

V4

V5

+

–

COM1–COM32

+

–

COMS1–COMS2

+

–

VR

V_EE

ASEG1–ASEG10

ACOM

LCD static

driver

AGND

GND

a) 3- or 4-line display with 1/6 bias

OPOFF = GND

HD66717

V_CC

V2

R

V1

+

SEG1–SEG60

–

V2

+

–

LCD

multiplexing

driver

Short-circuited

V3

V4

V5

+

–

COM1–COM16

+

–

COMS1–COMS2

+

–

VR

V_EE

V _EE

ASEG1–ASEG10

ACOM

LCD static

driver

AGND

GND

b) 1- or 2-line display with 1/4 bias

Note: 1. Potential differences between V_CCand V1 and between V5 and V_EEmust be 0.4V or greater,

particularly for low-duty drive such as 1-line display.

2. When the internal operational amplifiers cannot fully drive the LCD panel used, an appropriate capacitor

must be inserted between each output of V1OUT to V5OUT and V_CCto stabilize the

operational amplifier output.

Figure 30 External Power Supply Circuit Example for LCD Drive Voltage Generation

504

HD66717

When an Internal Booster and Internal Operational Amplifiers are Used

To supply LCD drive voltage using the internal booster, circuits should be connected as shown in Figure

31. Here, contrast can be adjusted through the CT bits of the contrast-control instruction. Temperature

can be compensated either through the CT bits or by controlling the reference voltage for the booster (Vci

pin) using a thermistor.

Note that Vci is both a reference voltage and power supply for the booster; the reference voltage must

therefore be adjusted using an emitter-follower or a similar element so that sufficient current can be

supplied. In this case, Vci must be equal to or smaller than the V_CClevel.

The HD66717 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce

current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal

drive voltages. Thus, potential differences between V_CCand V1 and between V_EEand V5 must be 0.4V or

greater. Note that the OPOFF pin must be grounded when using the operational amplifiers.

b) Triple boosting

a) Double boosting

OPOF = GND

OPOFF = GND

HD66717

V_CC

R

V1

+

V1

V2

+

–

R

V2

V3

V2

V3

V2

+

–

Short-circuited

for 1-or 2-line

display

Short-circuited

for 1-or 2-line

display

R

V3

V4

V5

V3

V4

V5

+

–

+

–

+

–

+

–

+

–

VR

V_EE

Vci

C1

Vci

C1

0.47 µF

to 1 µF

0.47 µF

to 1 µF

C2

+

C2

+

Booster

V5OUT2

V5OUT3

0.47 µF

to 1 µF

0.47 µF

to 1 µF

+

GND

V5OUT3

GND

+

GND

Note: 1. The reference voltage input (Vci) must be adjusted so that the output voltage after boosting will not exceed

the absolute maximum rating of the liquid-crystal power supply voltage (15V). Particularly, Vci must be

5 V or less for triple boosting.

2. Vci is both a reference voltage and power supply for the booster; connect it to V_CCdirectly or combine it with

a transistor so that sufficient current can be obtained.

3. Vci must be smaller than V_CC

4. To operate the voltage-follower correctly, potential differences between V_CCand V1 and between V5 and

_EEmust be 0.4V or greater, particularly for low-duty drive such as 1-line display.

.

V

5. Polarized capacitors must be connected correclty.

6. Circuits for temperature compensation should be designed based on the sample circuit shown in Figure 32.

Figure 31 Internal Power Supply Circuit Example for LCD Drive Voltage Generation

505

HD66717

V_CC

Vci

Tr

Thermistor

GND

Figure 32 Temperature Compensation Circuit Example

506

HD66717

The HD66717’s internal operational amplifiers have a reduced drive current to save current consumption;

when the internal operational amplifiers cannot fully drive the LCD panel used, an appropriate capacitors

must be inserted between each output of V1OUT to V5OUT and V_CCto stabilize the operational amplifier

output (Figure 33). Especially, the capacitors for V1OUT and V4OUT must be inserted when 1/26 duty

or 1/34 duty drives.

OPOFF = GND

0.1 µF to 0.5 µF*

HD66717

V_CC

+

+ + + +

R

+

–

V1

V1OUT

R

V2

V2OUT

+

–

V2

SEG1–SEG60

LCD

R

multiplexing

driver

V3

+

–

V3

V3OUT

COM1–COM32

R

+

–

COMS1–COMS2

V4

V4OUT

+

–

V5

V5OUT

V_EE

VR

Vci

C1

0.47 µF

to 1 µF

C2

+

Booster

V5OUT2

0.47 µF

to 1 µF

+

GND

V5OUT3

0.47 µF

to 1 µF

+

GND

Note : The capacitors for V1OUT and V4OUT must be inserted when 1/26 duty or 1/34 duty drives.

Figure 33 Operational Amplifier Output Stabilization Circuit Example

507

HD66717

When an Internal Booster and External Bleeder-Resistors are Used

When the internal operational amplifiers cannot fully drive the LCD panel used, V1 to V5 voltages can

be supplied through external bleeder-resistors (Figure 34). Here, the OPOFF pin must be set to the V_CC

level to turn off the internal operational amplifiers. Since the internal contrast adjuster is disabled in this

case, contrast must be adjusted externally. Double- and triple-boosters can be used as they are.

OPOFF = V_CC

HD66717

V_CC

V

CC

V_CC

+

–

R

V1

V2

V1OUT

V2OUT

+

–

2R

+

–

V3

V4

V5

V3OUT

V4OUT

V5OUT

+

–

R

+

–

VR

V_EE

Vci

C1

0.47 µF

to 1 µF

C2

+

Booster

V5OUT2

0.47 µF

to 1 µF

+

GND

V5OUT3

0.47 µF

to 1 µF

+

GND

Note: 1. Resistance of each external bleeder resistor should be 5 kΩ to 15 kΩ.

2. The bias current value for driving liquid-crystals can be varied by adjusting

the resistance (2R) between the V2OUT and V3OUT pins.

3. The internal contrast-adjuster is disabled; contrast must be adjusted either

by controlling the external variable resistor between V and V5OUT or Vci for the booster.

EE

4. Vci is both a reference voltage and power supply for the booster; connect it to V directly

CC

or combine it with a transistor so that sufficient current can be obtained.

5. Vci must be smaller than V

.

CC

Figure 34 External Bleeder-Resistor Example for LCD Drive Voltage Generation Power Supply

Circuit

508

HD66717

Contrast Adjuster

Multiplexing Drive System

Contrast for an LCD controlled by the multiplexing drive method can be adjusted by varying the liquid-

crystal drive voltage (potential difference between V_CCand V5) through the CT bits of the contrast control

instruction (electron volume function). See Figure 35 and Table 20. The value of a variable resistor (VR)

can be adjusted within the range from 0.4R through 6.4R, where R is a reference resistance obtained by

dividing the total resistance between V_CCand V5.

The HD66717 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce

current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal

drive voltages. Thus, potential differences between V_CCand V1 and between V_EEand V5 must be 0.4V or

greater. Note that the OPOFF pin must be grounded when using the operational amplifiers.

•

1/6 bias (V2 and V3 pins left open)

LCD drive voltage VLCD: 6R × (V_CC– V_EE)/(6R + VR) (VR = a value within the range from 0.4R

to 6.4R)

VLCD adjustable range: 0.484 × (V_CC– V_EE) ≤ VLCD ≤ 0.938 × (V_CC– V_EE)

Potential difference between V_CCand V1: R × (V_CC– V_EE)/(6R + VR) ≥ 0.4 (V)

Potential difference between V5 and V_EE: VR × (V_CC– V_EE)/(6R + VR) ≥ 0.4 (V)

1/4 bias (V2 and V3 pins short-circuited)

LCD drive voltage VLCD: 4R × (V_CC– V_EE)/(4R + VR) (VR = a value within the range from 0.4R

to 6.4R)

VLCD adjustable range: 0.385 × (V_CC– V_EE) ≤ VLCD ≤ 0.909 × (V_CC– V_EE)

Potential difference between V_CCand V1: R × (V_CC– V_EE)/(4R + VR) ³ 0.4 (V)

Potential difference between V5 and V_EE: VR × (V_CC– V_EE)/(4R + VR) ³ 0.4 (V)

Static Drive System

Contrast for a statically-driven LCD, that is, annunciator display, can be adjusted through the AGND pin.

The annunciators are driven statically by the potential difference between V_CCand AGND. The AGND

pin level must be equal to or greater than the GND level.

509

HD66717

V_CC

R

+

–

V1

V2

V3

+

–

+

–

V3

V4

V5

+

–

+

–

VR

V_EE

CT

Figure 35 Contrast Adjuster

Table 20

Contrast-Adjust Bits (CT) and Variable Resistor Values

CT Register

CT3

0

CT2

0

CT1

0

CT0

0

Variable Resistor Value (VR)

6.4 R

6.0 R

5.6 R

5.2 R

4.8 R

4.4 R

4.0 R

3.6 R

3.2 R

2.8 R

2.4 R

2.0 R

1.6 R

1.2 R

0.8 R

0.4 R

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

510

HD66717

LCD Module Interface

Segment data output pins SEG1 to SEG60 can be connected either from left to right or right to left of an

LCD panel according to the SFT pin level. When the SFT pin is grounded, SEG1 is connected to the far

left of the panel, and when it is at the V_CClevel, SEG60 is connected to the far left. Either connection

mode can be selected according to the LCD module layout and routing on a printed-circuit board. Figures

36 shows two examples.

511

HD66717

a) 12-character x 3-line display (SEG line above the panel : SFT = GND)

SEG60

SEG59–2

SEG1

COMS1

COM1

–

COM8

SFT

GND

COM9

–

COM16

COM17

–

COM24

COMS2

ACOM

MODE 2ndF Clock DATE TIME

KEY

ON

ASEG1–

ASEG10

b) 12-character x 4-line display (SEG line below the panel : SFT = V_CC

)

ASEG1–

ASEG10

ACOM

V_CC

ON

MODE 2ndF Clock DATE TIME

KEY

COMS1

SFT

COM1

–

COM8

COM9

–

COM16

COM17

–

COM24

COM25

–

COM32

COMS2

SEG60

SEG59–2

SEG1

Figure 36 LCD Module Interface Examples

512

HD66717

Segment Display and Annunciator Display

The HD66717 provides both segment display, which is driven by the multiplexing method, and

annunciator display, which is driven statically. Annunciator display is driven at a logic operating voltage

(V_CC– AGND) and is thus also available while the LCD drive power supply is turned off. Accordingly,

annunciator display is suitable for displaying marks during system standby, when it is desirable to reduce

current consumption. It is available in sleep mode, where internal multiplexing operations for character or

segment display are halted. If an alternating signal is supplied to the EXM pin, it is also available in

standby mode, where the internal R-C oscillator is halted. Here, AGND must be equal to or above the

GND level.

Note that annunciator display cannot share character display drivers SEG and COM but require special

drivers ASEG and ACOM that require long routing.

Tables 21 to 23 illustrates segment display and annunciator display.

Table 21

Comparison between Segment Display and Annunciator Display

Segment Display Annunciator Display

Item

Number of driven elements 20 each by COMS1 and COMS2

10

Blinking

Impossible

Possible

Segment drivers

SEG1–SEG60

ASEG1–ASEG10

(shared with character display)

(independent of character display)

Common drivers

COMS1, COMS2

ACOM

LCD power supply

V_CC– V5

V_CC– AGND

(LCD power supply necessary)

(LCD power supply unnecessary)

Normal mode display

Sleep mode display

Display possible together with

character display by multiplexing drive

Display possible by static drive

Impossible

Possible by static drive

(SEG and COM output V_CC)

Standby mode display

(without oscillation)

Impossible

(SEG and COM output V_CC)

Possible by supplying alternating

signal to the EXM pin

513

HD66717

Table 22

Correspondence between Segment Display SEGRAM Addresses (ASEG) and Driver

Signals

ASEG Address

Segment Signals

Common

Signal

MSB

LSB

0

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

0

1

0

1

0

1

COMS1 SEG1/21/41

COMS1 SEG6/26/46

SEG2/22/42

SEG7/27/47

SEG3/23/43

SEG8/28/48

SEG4/24/44

SEG9/29/49

SEG5/25/45

SEG10/30/50

1

0

COMS1 SEG11/31/51 SEG12/32/52 SEG13/33/53 SEG14/34/54 SEG15/35/55

COMS1 SEG16/36/56 SEG17/37/57 SEG18/38/58 SEG19/39/59 SEG20/40/60

1

0

COMS2 SEG1/21/41

COMS2 SEG6/26/46

SEG2/22/42

SEG7/27/47

SEG3/23/43

SEG8/28/48

SEG4/24/44

SEG9/29/49

SEG5/25/45

1

SEG10/30/50

0

COMS2 SEG11/31/51 SEG12/32/52 SEG13/33/53 SEG14/34/54 SEG15/35/55

COMS2 SEG16/36/56 SEG17/37/57 SEG18/38/58 SEG19/39/59 SEG20/40/60

1

Table 23

Correspondence between Annunciator Display Addresses (AAN) and Driver Signals

AAN Address

Segment Signals

Common

Signal

MSB

LSB

Bits 7, 6

ASEG1

ASEG5

ASEG9

Bits 5, 4

Bits 3, 2

ASEG3

ASEG7

—

Bits 1, 0

ASEG4

ASEG8

—

0

1

0

1

0

ACOM

ASEG2

ASEG6

ASEG10

Note: The annunciator is turned on when the corresponding even bit (bit 6, 4, 2, or 0) is 1, and the

turned-on annunciator blinks when the corresponding odd bit (bit 7, 5, 3, or 1) is 1.

514

HD66717

Annunciator Drive

Figure 37 shows annunciator drive output waveforms in two modes.

i) Normal mode and sleep mode

V_CClevel

ACOM

AGND level

V_CClevel

ASEG1

Display off

Display on

V_CClevel

V

_CClevel

ASEG2

AGND level

1 frame

ii) Standby mode (without oscillation)

1 frame

V

_CClevel

V_CClevel

EXM

(Input)

AGND level

V

V_CClevel

ACOM

ASEG1

ASEG2

V

_CClevel

V_CClevel

Display off

Display on

AGND level

V

_CClevel

AGND level

Note: If annunciator display is unnecessary during standby mode, make sure to fix the EXM pin to the V_CCor GND level

and set the annunciator display ON bit (DA) to 0. This will prevent dark display and liquid-cell deterioration due to

DC bias application on liquid crystal cells.

Figure 37 Annunciator Drive Output Waveforms

515

HD66717

Vertical Smooth Scroll

The HD66717 can scroll in the vertical direction in units of raster-rows. This function is achieved by

writing character codes into the DDRAM area that is not being used for display. In other words, since the

DDRAM corresponds to a 5-line × 12-character display, one of the lines can be used to achieve

continuous smooth vertical scroll even in a 4-line display. Here, after the fifth line is displayed, the first

line is displayed again. Specifically, this function is controlled by incrementing or decrementing the

value in the scroll-start line bits (SL2 to SL0) and scroll-start raster-row bits (SN2 to SN0) by 1. For

example, to smoothly scroll up, first set SN2 to SN0 to 000, and increment SL2 to SL0 by 1 from 000 to

111 to scroll seven raster-rows. Then increment SN2 to SN0 to 001, and again increment SL2 to SL0 by 1

from 000 to 111. To start displaying and scrolling from the first raster-row of the second line, update the

first line of DDRAM data as desired during its non-display period.

Figure 38 shows an example of vertical smooth scrolling and Figure 39 shows an example of setting

instructions for vertically scrolling upward in a 4-line display (NL1 and NL0 = 11).

516

HD66717

9) 8 raster-row scrolled

up

· SN2–0 = 001

· SL2–0 = 000

Set initial data to all DDRAM addresses

1) Not scrolled

· SN2–0 = 000

· SL2–0 = 000

Update the first line of DDRAM data

2) 1 raster-row scrolled

up

10) 9 raster-row scrolled

up

· SL2–0 = 001

3) 2 raster-row scrolled

up

11) 10 raster-row scrolled

up

· SL2–0 = 010

4) 3 raster-row scrolled

up

12) 11 raster-row scrolled

up

· SL2–0 = 011

5) 4 raster-row scrolled

up

13) 12 raster-row scrolled

up

· SL2–0 = 100

6) 5 raster-row scrolled

up

14) 13 raster-row scrolled

up

· SL2–0 = 101

7) 6 raster-row scrolled

up

15) 14 raster-row scrolled

up

· SL2–0 = 110

8) 7 raster-row scrolled

up

16) 15 raster-row scrolled

up

· SL2–0 = 111

Figure 38 Example of Vertical Smooth Scrolling

517

HD66717

9) 8 raster-row scrolled

up

Set initial data to all DDRAM addresses

· SN2–0 = 001

· SL2–0 = 000

1) Not scrolled

· SN2–0 = 000

· SL2–0 = 000

Update the first line of DDRAM data

10) 9 raster-row scrolled

up

2) 1 raster-row scrolled

up

· SL2–0 = 001

11) 10 raster-row scrolled

up

3) 2 raster-row scrolled

up

· SL2–0 = 010

4) 3 raster-row scrolled

up

12) 11 raster-row scrolled

up

· SL2–0 = 011

5) 4 raster-row scrolled

up

13) 12 raster-row scrolled

up

· SL2–0 = 100

6) 5 raster-row scrolled

up

14) 13 raster-row scrolled

up

· SL2–0 = 101

7) 6 raster-row scrolled

up

15) 14 raster-row scrolled

up

· SL2–0 = 110

8) 7 raster-row scrolled

up

16) 15 raster-row scrolled

up

· SL2–0 = 111

Figure 39 Example of Setting Instructions for Vertical Smooth Scroll

(4-line display (NL1 and NL0 = 11))

518

HD66717

Line-Cursor Display

The HD66717 can assign a cursor attribute to an entire line corresponding to the address counter value by

setting the LC bit to 1 (Table 24). One of three line-cursor modes can be selected: a black-white inverting

blink cursor (B/W = 1), an underline cursor (C = 1), and a blink cursor (B = 1). The blink cycle for a

black-white inverting blink cursor and for a blink cursor is 32 frames. These line-cursors are suitable for

highlighting an index and/or marker, and for indicating an item in a menu with a cursor or an underline.

Figures 40 to 42 show three line-cursor examples.

Table 24

Address Counter Value and Line-Cursor

Address Counter Value (AC)

00H to 0BH

Selected Line for Line-Cursor

Entire 1st line (12 digits)

Entire 2nd line (12 digits)

Entire 3rd line (12 digits)

Entire 4th line (12 digits)

Entire 5th line (12 digits)

10H to 1BH

20H to 2BH

30H to 3BH

40H to 4BH

519

HD66717

Alternates every 32 frames

Figure 40 Example of Black-White Inverting Blink Cursor (LC = 1; B/W = 1)

520

HD66717

Figure 41 Example of Underline Cursor (LC = 1; C = 1)

521

HD66717

Alternates every 32 frames

Figure 42 Example of Blink Cursor (LC = 1; B = 1)

522

HD66717

Double-Height Display

The HD66717 can double the height of any desired line from the first to third lines. A line can be selected

by the DL3 to DL1 bits as listed in Table 25. All the standard font characters stored in the CGROM and

CGRAM can be doubled in height, providing an easy-to-see display. Note that there should be no space

between lines for double-height display (Figure 43).

Table 25

Double-Height Display Specifications

2-Line Display

DL3 DL2 DL1 (NL1, NL0 = 01)

3-Line Display

(NL1, NL0 = 10)

4-Line Display

(NL1, NL0 = 11)

0

1

1st & 2nd lines: normal

1st line: double-height

1st to 3rd lines: normal

1st to 4th lines: normal

1st line: double-height

2nd line: normal

1st line: double-height

2nd & 3rd lines: normal

0

1

0

Disabled

2nd line: double-height

1st line: normal

2nd line: double-height

1st & 3rd lines: normal

0

1

0

1

0

1st line: double-height

1st & 2nd lines: normal

Disabled

1st & 2nd lines: double-height

3rd line: double-height

1st & 2nd lines: normal

1

0

1

0

1

1st line: double-height

Disabled

1st line: double-height

2nd line: normal

Disabled

2nd line: double-height

1st line: normal

Disabled

1st line: double-height

Disabled

1st & 2nd lines: double-height

523

HD66717

i) 3-line display example (DL1 = 0, DL2 = 1)

1st line:

normal display

2nd line:

double-height

display

ii) 4-line display example (DL = 1, DL2 = 0, DL3 = 0)

1st line:

double-height

display

2nd line:

normal display

3rd line:

normal display

Figure 43 Double-Height Display Examples

524

HD66717

Partial-Display-Off Function

The HD66717 can program the number of display lines (NL1 and NL0 bits), divide the internal operating

frequency by four (OSC bit), and adjust the display contrast (CT bit). Combining these functions, the

HD66717 can turn off the second and/or subsequent lines, displaying only the characters in the first line

to reduce internal current consumption (partial-display-off function). This function is suitable for

calendar or time display, which needs to be continuous during system standby with minimal current

consumption. Here, the second to fourth non-displayed lines are constantly driven by the deselection level

voltage, thus turning off the LCD for the lines.

Note that internal clock frequency is reduced to a quarter, quadrupling execution time of each instruction;

MPU data transfer rate must be appropriately adjusted.

Table 26 lists partial-display-off function specifications and Figure 44 shows a sample display using the

partial-display-off function.

Table 26

Partial Display Off Function

Function Item

Normal 4-Line Display

1st to 4th lines displayed

Possible

Partially-Off Display

Only 1st line displayed

Possible

Character display

Segment display

Annunciator display

R-C oscillation frequency

Internal operating frequency

LCD single-line drive frequency

Frame frequency

Possible

160 kHz

160 kHz (OSC = 0)

2.7 kHz (1/34 duty ratio)

78 Hz

40 kHz (OSC = 1)

0.7 kHz (1/10 duty ratio)

66 Hz

Note: Select an optimum LCD drive voltage (between V_CCand V5) for the multiplexing duty ratio used,

using a reference voltage input pin (Vci) for the booster or the contrast-adjust bits (CT) .

525

HD66717

Display available

(driven with selection

level)

Display available

(driven with selection

level)

Display unavailable

(driven with

deselection level)

Figure 44 Example of Partially-Off Display (date and time indicated)

526

HD66717

Sleep Mode

Setting the sleep mode bit (SLP) to 1 puts the HD66717 in sleep mode, where the device halts all the

internal display operations except for annunciator display operations, thus reducing current consumption.

Specifically, character and segment displays, which are controlled by the multiplexing drive method, are

completely halted. Here, all the SEG (SEG1 to SEG60) and COM (COM1 to COM34) pins output the V_CC

level, resulting in no display. If the AMP bit is set to 0 in sleep mode, the LCD drive power supply can be

turned off, reducing the total current consumption of the LCD module.

Annunciators can be normally displayed in sleep mode. Since they are driven at logic operating power

supply voltage (V_CC– AGND), they are available even if the LCD power supply is turned off (AMP = 0).

This function allows time and alarm marker indication during system standby with reduced current

consumption.

During sleep mode, no instructions can be accepted for character/segment display and neither DDRAM,

CGRAM, nor SEGRAM can be accessed.

Table 27 compares the functions of sleep mode and standby mode.

Table 27

Comparison of Sleep Mode and Standby Mode

Function Item

Sleep Mode (SLP = 1)

Turned off

Standby Mode (STB = 1)

Turned off

Character display

Segment display

Annunciator display

Turned off

Can be turned on

Can be turned on when an alternating

signal is supplied to the EXM pin

R-C oscillation

Normally operates

Halted

527

HD66717

Standby Mode

Setting the standby mode bit (STB) to 1 puts the HD66717 in standby mode, where the device stops

completely, halting all internal operations including the R-C oscillator, thus further reducing current

consumption compared to that in sleep mode. Specifically, character and segment displays, which are

controlled by the multiplexing drive method, are completely halted. Here, all the SEG (SEG1 to SEG60)

and COM (COM4 to COM34) pins output the V_CClevel, resulting in no display. If the AMP bit is set to 0

in standby mode, the LCD drive power supply can be turned off.

Annunciators can be displayed simply by supplying an approximately 40-Hz alternating signal for the

LCD drive signals to the EXM pin externally. If annunciator display is unnecessary during standby mode,

the EXM pin must be fixed to the V_CCor GND level and the annunciator display-on bit (DA) set to 0.

During standby mode, no instructions can be accepted other than those for annunciator display and the

start-oscillator instruction. To cancel standby mode, issue the start-oscillator instruction to stabilize R-C

oscillation before setting the STB bit to 0.

Figure 45 shows the procedure for setting and cancelling standby mode.

Turn off the LCD power supply: AMP = 0

Set standby mode: STB = 1

Supply an external alternating signal to the EXM pin

Only for annunciator display;

set the DA bit to 0 when

Standby mode (only annunciator display is available)

annunciator display is not necessary.

Issue the start-oscillator instruction

Wait at least 10 ms

Cancel standby mode: STB = 0

Turn on the LCD drive power supply: AMP = 1

Figure 45 Procedure for Setting and Cancelling Standby Mode

528

HD66717

Absolute Maximum Ratings*

Item

Symbol

V_CC

Unit

V

Value

Notes

Power supply voltage (1)

Power supply voltage (2)

Input voltage

–0.3 to +7.0

–0.3 to +15.0

–0.3 to V_CC+ 0.3

–20 to +75

–40 to +125

1

V_CC–V_EE

Vt

V

1, 2

1

V

Operating temperature

Storage temperature

T_opr

°C

T_stg

4

Note:

*

If the LSI is used above these absolute maximum ratings, it may become permanently

damaged. Using the LSI within the following electrical characteristic limits is strongly

recommended for normal operation. If these electrical characteristic conditions are also

exceeded, the LSI will malfunction and cause poor reliability.

529

HD66717

DC Characteristics (V_CC= 2.4V to 5.5V, T_a= –20 to +75°C*³)

Item

Symbol Min

Typ

—

Max

V_CC

Unit

V

Test Condition

Notes*

Input high voltage

Input low voltage

VIH

VIL

0.7V_CC

6

–0.3

—

0.15V_CC

0.6

V

V_CC= 2.4 to 3.0V

V_CC= 3.0 to 5.5V

I_OH= –0.1 mA

–0.3

—

V

Output high voltage

(1) (DB0–DB7 pins)

VOH1

0.75V_CC

—

V

Output low voltage (1) VOL1

(DB0–DB7 pins)

—

2

0.2V_CC

0.4

V

I_OL= 0.1 mA

Output low voltage (2) VOL2

(SDA pin)

V

V_CC= 2.4 to 4.5V

I_OL= 0.4 mA

7

V

V_CC= 4.5 to 5.5V

I_OL= 1.0 mA

Driver ON resistance R_COM

(COM pins)

20

kΩ

±Id = 0.05 mA (COM)

VLCD = 4V

8

9

Driver ON resistance R_SEG

(SEG pins)

2

30

±Id = 0.05 mA (SEG)

VLCD= 4V

I/O leakage current

I_LI

–1

10

—

1

µA

V_IN= 0 to V_CC

Pull-up MOS current

(RESET* pin)

–Ip

50

120

V_CC= 3V

Vin = 0V

Current consumption I_OP

during normal

operation (V_CC–GND)

—

30

60

µA

R_foscillation,

10, 11

external clock,

V_CC= 3V, f_OSC= 160 kHz,

1/34 duty

Current consumption I_SL

during sleep mode

(V_CC–GND)

—

25

0.1

25

—

5

µA

R_foscillation,

external clock,

V_CC= 3V, f_OSC= 160 kHz

10, 11

Current consumption I_ST

during standby mode

(V_CC–GND)

No R_foscillation,

V_CC= 3V, Ta = 25°C

LCD power supply

current (V_CC–V_EE)

I_EE

60

V_CC–V_EE= 8V,

f_OSC= 160 kHz

VREF–VREFM: short-

circuited

LCD voltage with

1/4 bias (V_CC–V_EE)

VLCD1 3.0

VLCD2 3.0

—

13.0

V

V2–V3 short-circuited

12

LCD voltage with

1/6 bias (V_CC–V_EE)

V2–V3 open

Note:

*

Refer to the Electrical Characteristics Notes section following these tables.

530

HD66717

Booster Characteristics

Item

Symbol Min

Typ

Max

Unit

Test Condition

_CC= Vci = 4.5V,

I₀= 0.1 mA, C = 1 µF,

f_OSC= 160 kHz, T_a= 25°C

Notes*

Output voltage

(V5OUT2 pin)

VUP2

VUP3

VCi

8.0

7.0

1.0

8.8

—

V

15

Output voltage

(V5OUT3 pin)

7.9

—

V

V_CC= Vci = 2.7V,

I₀= 0.1 mA, C = 1 µF,

f_OSC= 160 kHz, T_a= 25°C

15

Input voltage

5.0

Vci ² V_CC

Note:

*

Refer to the Electrical Characteristics Notes section following these tables.

531

HD66717

AC Characteristics (V = 2.4V to 5.5V, T_a= –20 to +75°C*³)

CC

Clock Characteristics (V_CC= 2.4V to 5.5V)

Item

Symbol Min

Typ

160

50

Max

350

55

Unit

kHz

%

Test Condition Notes*

External External clock frequency

clock

operation

f_cp

20

45

—

13

External clock duty ratio

Duty

t_rcp

External clock rise time

—

0.2

200

µs

External clock fall time

t_fcp

—

µs

R_f

Clock oscillation frequency f_OSC

120

160

kHz

R_f= 150 kΩ,

V_CC= 3V

14

oscillation

Note:

*

Refer to the Electrical Characteristics Notes section following these tables.

Read & Write Bus Interface Timing Characteristics with Read Operation (V_CC= 2.4V to 4.5V)

Item

Symbol Min

Typ

—

Max

—

Unit

Test Condition

Enable cycle time

t_cycE

PW_EH

t_Er, t_Ef

t_AS

1000

450

—

ns

Figures 52

and 53

Enable pulse width (high level)

Enable rise/fall time

Address set-up time (RS, R/W to E)

Address hold time

—

25

—

60

t_AH

20

—

Data set-up time

t_DSW

t_H

t_DDR

t_DHR

195

30

—

Data hold time

—

Read data delay time

Read data hold time

—

400

—

ns

Figure 53

5

Read & Write Bus Interface Timing Characteristics with Read Operation (V_CC= 4.5V to 5.5V)

Item

Symbol Min

Typ

Max

Unit

Test Condition

Enable cycle time

t_CYCE

500

—

ns

Figures 52

and 53

Enable pulse width (high level)

Enable rise/fall time

PW_EH

t_Er, t_Ef

t_AS

230

—

40

30

80

30

—

5

—

20

—

200

—

Address set-up time (RS, R/W to E)

Address hold time

t_AH

Data set-up time

t_DSW

t_H

t_DDR

t_DHR

Data hold time

Read data delay time

Read data hold time

ns

Figure 53

532

HD66717

Write Bus Interface Timing Characteristics without Read Operation (V_CC= 2.4V to 5.5V)

Item

Symbol Min

Typ

—

Max

—

Unit

Test Condition

Enable cycle time

t_CYCE

500

200

150

—

ns

Figure 52

Enable pulse width

(“High” level)

V_CC= 2.4 to 3.0V P_WEH

—

V

_CC= 3.0 to 5.5V P_WEH

—

Enable rise/fall time

t_Er, t_Ef

20

—

Address set-up time (RS, R/W to E)

Address hold time

t_AS

t_AH

t_DSW

t_H

60

20

—

Data set-up time

140

30

—

Data hold time

—

Clock-Synchronized Serial Interface Operation (V_CC= 2.4V to 5.5V)

Item

Symbol Min

Typ

—

Max

20

—

Unit

µs

Test Condition

Serial clock cycle time

Serial clock high-level width

Serial clock low-level width

Serial clock rise/fall time

Chip select set-up time

Chip select hold time

Serial input data set-up time

Serial input data hold time

t_SCYC

t_SCH

1

Figure 54

400

—

ns

t_SCL

—

t_SCr, t_SCf

t_CSU

50

—

60

t_CH

200

—

t_SISU

t_SIH

—

I²C bus Interface Operation (V_CC= 2.4V to 4.5V)

Item

Symbol Min

Typ

—

Max

20

—

Unit

µs

Test Condition

SCL clock cycle time

SCL clock high-level width

SCL clock low-level width

SCL/SDA rise/fall time

Bus free time

t_SCL

2

Figure 55

t_SCLH

t_SCLL

t_Sr, t_Sf

t_BUF

500

1000

—

ns

—

300

—

100

500

140

0

Start hold time

t_STAH

t_STAS

t_STOS

t_SDAS

t_SDAH

—

Retransmit start set-up time

Stop set-up time

—

SDA data set-up time

SDA data hold time

—

533

HD66717

I2C bus Interface Operation (V_CC= 4.5V to 5.5V)

Item

Symbol Min

Typ

—

Max

20

—

Unit

µs

Test Condition

SCL clock cycle time

SCL clock high-level width

SCL clock low-level width

SCL/SDA rise/fall time

Bus free time

t_SCL

2

Figure 55

t_SCLH

t_SCLL

t_Sr, t_Sf

t_BUF

500

1000

—

ns

—

300

—

100

500

100

0

Start hold time

t_STAH

t_STAS

t_STOS

t_SDAS

t_SDAH

—

Retransmit start set-up time

Stop set-up time

—

SDA data set-up time

SDA data hold time

—

Reset Timing (V_CC= 2.4 V to 5.5 V)

Item

Symbol Min

t_RES10

Typ

Max

Unit

Test Condition

Reset low-level width

—

ms

Figure 56

534

HD66717

Electrical Characteristics Notes

1. All voltage values are referred to GND = 0V. If the LSI is used above the absolute maximum ratings,

it may become permanently damaged. Using the LSI within the given electrical characteristic is

strongly recommended to ensure normal operation. If these electrical characteristic are exceeded, the

LSI may malfunction or exhibit poor reliability.

2. V_CC≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 > V_EEmust be maintained.

3. For die products, specified up to 75°C.

4. For die products, specified by the common die shipment specification.

5. The following four circuits are I/O pin configurations except for liquid crystal display output (Figure

46).

Pins: E/SCL, RS/CS*,

OSC1, IM1/0, SFT, TEST

OPOFF

Pins: RESET*

Pins: RW/SDA

V_CC

PMOS

(pull-down MOS)

NMOS

PMOS

NMOS

PMOS

NMOS

PMOS

NMOS

(pull-up MOS)

ACK

GND

Pins: DB7–DB0/ID0

V_CC

(Input circuit)

PMOS

(pull-up MOS)

PMOS

Input enable

NMOS

V_CC

(Tri-state output circuit)

Output enable

Output data

PMOS

GND

NMOS

GND

Figure 46 I/O Pin Configurations

535

HD66717

6. The TEST pin must be grounded and the ID5 to ID0, IM1, IM0, SFT, EXM, and OPOFF pins must

be grounded or connected to V_CC.

7. Applies to the ACK bit for I²C bus interface.

8. Applies to resistor values (RCOM) between power supply pins V_CC, V1OUT, V4OUT, V5OUT and

common signal pins (COM1 to COM32, COMS1, and COMS2), and resistor values (RSEG) between

power supply pins V_CC, V2OUT, V3OUT, V5OUT and segment signal pins (SEG1 to SEG60).

9. This excludes the current flowing through pull-up MOSs and output drive MOSs.

10. This excludes the current flowing through the input/output units. The input level must be fixed high or

low because through current increases if the CMOS input is left floating.

11. The following shows the relationship between the operation frequency (f_OSC) and current consumption

(I_CC) (Figure 47).

V

= 3V

V

= 3V

CC

1/34

duty

Display on (typ.)

Sleep (typ.)

VREF=VREFP Short-circuited

40

30

20

10

0

80

60

40

20

0

VREF left disconnected

1/26

duty

VREF=VREFP=VRERM

Short-circuited

1/18

duty

1/10

duty

VREF–VREFM

Short-circuited

Standby (typ.)

0

50 100 150 200 250

3

4

5

6

7

8

9

10 11

CR oscillator frequency

Liquid crystal drive voltage : VLCD (V)

Figure 47 Relationship between the Operation Frequency and Current Consumption

12. Each COM and SEG output voltage is within ±0.15V of the LCD voltage (V_CC, V1, V2, V3, V4, V5)

when there is no load.

13. Applies to the external clock input (Figure 48).

Th

Tl

0.7V

0.5V

0.3V

CC

OSC1

OSC2

Oscillator

Open

Th

Duty =

100%

X

Th+Tl

t

rcp

fcp

Figure 48 External Clock Supply

536

HD66717

14. Applies to the internal oscillator operations using oscillation resistor R_f(Figure 49).

OSC1

OSC2

Since the oscillation frequency varies depending on the OSC1 and

OSC2 pin capacitance, the wiring length to these pins should be

minimized.

R

f

Referential data

200

160

150

100

50

V

5V (typ.)

CC=

V

=3V (typ.)

300

CC

0

100

150

200

400

500

600

700

800

R (kΩ)

f

Figure 49 Internal Oscillation

15. Booster characteristics test circuits are shown in Figure 50.

( Triple boosting )

( Double boosting )

V_CC

Vci

C1

Vci

C1

C2

1 µF

+

C2

+

V5OUT2

1 µF

+

1 µF

+

V5OUT3

V_EE

GND

Figure 50 Booster

537

HD66717

Referential data

VUP2 = V – V5OUT2

VUP3 = V – V5OUT3

CC

(i) Relationship between the obtained voltage and input voltage

Double boosting

Triple boosting

15

14

13

12

11

10

9

11

typ.

10

9

8

7

6

8

5

4

7

6

2.0

3.0

4.0

Vci (V)

5.0

2.0

3.0

4.0

Vci (V)

5.0

Vci = V_CC, fcp = 160kHz, Ta = 25°C

(ii) Relationship between the obtained voltage and temperature

Triple boosting

Double boosting

9.5

8.5

9.0

8.0

7.5

7.0

6.5

typ.

8.5

8.0

7.5

-60

-20

0

20

60

100

-60

-20

0

20

60

100

Ta ( °C )

Vci = V_CC= 4.5V, R_f= 180kΩ,

_O= 0.1mA

Vci = V_CC= 2.7V, R_f= 150kΩ,

I

_O= 0.1mA

(iii) Relationship between the obtained voltage and capacitance

Double boosting

Triple boosting

9.0

typ.

8.0

8.5

8.0

7.5

7.0

7.5

7.0

6.5

6.0

0.5

1.0

1.5

0.5

1.0

1.5

C (µF)

Vci = V_CC= 2.7V, R_f= 150kΩ,

_O= 0.1mA

Vci = V_CC= 4.5V, R_f= 180kΩ,

_O= 0.1mA

I

Figure 50 Booster (cont)

538

HD66717

(iv) Relationship between the obtained voltage and the load current.

Double boosting

9.0

Triple boosting

8.0

7.0

6.0

5.0

4.0

3.0

2.0

8.5

8.0

typ.

2.0

7.5

typ.

7.0

6.5

6.0

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

I_O(mA)

Vci = V_CC= 2.7V, Rf = 150 kΩ

Ta = 25°C

Vci = V_CC= 4.5V, Rf = 180 kΩ

Ta = 25°C

Figure 50 Booster (cont)

Load Circuits

AC Characteristics Test Load Circuits

Data bus : SDA

Test Point

50 pF

Figure 51 Load Circuit

539

HD66717

Timing Characteristics

VIH

VIL

VIH

VIL

RS

t_AH

t_AS

R/W

VIL

PW_EH

t_AH

VIH

t_Er

VIH

t_Ef

E

VIL

t_DSW

t_H

VIH

VIL

VIH

VIL

DB0

Valid data

t_CYCE

– DB7

Figure 52 Bus Write Operation

VIH

VIL

RS

VIL

t_AS

t_AH

VIH

R/W

E

t_AH

PW_EH

VIH

t_Er

VIH

t_Ef

VIL

t_DDR

t_DHR

DB0

VOH1

VOL1

VOH1

VOL1

Valid data

t_CYCE

– DB7

Figure 53 Bus Read Operation

540

HD66717

Start : S

VIL

End : P

CS*

VIL

t_SCYC

t_SCHt_scft_CWL

t_CSU

t_scr

t_CH

VIH

VIH VIH

VIL

VIH

SCL

SDA

VIL

t_SISU

t_SIH

VIH

VIL

VIH

VIL

Valid data

Figure 54 Clock-Synchronized Serial Interface Timing

Start :S

Restart : Sr

VIH

Stop : P

VIH

VIL

VIH

VIL

VIH

VIL

SDA

VIL

t_SDAH

t_SDAS

t_BUP

t_STAH

t_SCL

t_SCLH

t_STOPS

t_STAS

VIH

VIL

VIH

SCL

VIL

t_sf

t_SCLL

t_sr

Figure 55 I²C Bus Interface Timing

541

HD66717

t_RES

RESET*

VIL

Figure 56 Reset Timing

542


型号：	HCD66717A03BP
厂家：	HITACHI SEMICONDUCTOR
描述：	(Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver) （低功耗点阵液晶显示控制器/驱动器）驱动器显示控制器微控制器和处理器外围集成电路 CD
文件：	总90页 (文件大小：713K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HCD66717A03BP [HITACHI]

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