HD151011_技术文档

HD151011

Dual BCD Programmable Counter

with Synchronous Preset Enable

ADE-205-100(Z)

Rev 0

April 1995

The HD151011 has BCD decimal two digits down counter and D-type Flip Flop. The counter can set up to

max 99 counts and synchronous preset (SPE) input can preset the data. When the count value is 0, the next

clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse,

whose data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid

crystal and general-use divider.

Features

•

High speed operation

tpd (CLK or CLK to Q) = 35 ns (typ)

High output current

Fanout of 10 LS TTL Loads

Wide operating voltage

Vcc = 2 to 6 V

Low supply current (Ta = 25°C)

Icc (Static) = 4 µA (max)

HD151011

Function Table

Control Inputs

CLR

PR

SPE

C/T

Mode

Operation Description

H

X

Generally count

Down count at the rise edge of clock (CLK),

Down count at the fall edge of clock (CLK)

X

L

X

Synchronous preset

Jn data is preset at the rise of clock (CLK),

the fall of clock (CLK)

—

L

—

H

—

H

—

Clock inputs (CLK, CLK) is CMOS level

Clock inputs (CLK, CLK) is TTL level

Initialize of Q = "L"

L

—

Initialize of Q output

H

L

Initialize of Q = "H"

H: High level

L: Low level

Z: Immaterial

—: Irrespective of condition

1. Synchronous preset (SPE) input can set max 99 down counts.

2. When the count value is 0, the next clock pulse presets the data to invert the output.

3. CLR and PR inputs initialize output state.

4. Clock inputs (CLK, CLK) is selectable CMOS level (V_CC= 2.0 to 6.0 V) and TTL level (V_CC= 4.5 to 5.5V)

(Jn, C/T, PR, CLR and SPE inputs are CMOS level)

Note: Don't set data exceeding 99 to Jn. (J0: LSB, J7: MSB)

2

HD151011

Pin Arrangement

V_CC

1

2

3

4

5

6

7

8

9

20

CO

J 0

J 1

J 2

J 3

J 4

J 5

J 6

19 (Test 1)*

(Test 2)*

C / T

18

17

16 CLK

CLK

15

Q

14

13

PR

12 SPE

11

J 7

GND 10

CLR

(Top view)

* Pins 18 and 19 are for function test only and should be open.

Pin Description

Pin Name

Pin Description

Input pins

J0 to J7

C/T

Count data input for option

Level change input for CLK, CLK (CMOS level or TTL level)

Clock inputs CLK : Rise edge trigger

CLK : Fall edge trigger

Preset input for Jn data

CLK, CLK

SPE

PR

Preset input for D-type Flip Flop (Initialize "L" at Q output)

Clear input for D-type Flip Flop (Initialize "H" at Q output)

Output for BCD decimal counter

CLR

CO

Q

Output pins

Output for D-type Flip Flop

3

HD151011

Absolute Maximum Ratings

Item

Symbol

Ratings

–0.5 to 7.0

–0.5 to V_CC+0.5

±50

Unit

V

Supply voltage

V_CC

Input / output voltage

VCC, GND current

Output current / pin

Power dissipation

Storage temperature

Input diode current

Output diode current

V_IN/ V_OUT

I_CC, I_GND

I_OUT

V

mA

mW

°C

±25

P_T

757

Tstg

I_IK

–65 to 150

±20

mA

I_OK

±20

Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and

furthermore, no two of which may be realized at the same time.

2. All voltage values except for differential input voltage are with respect to network ground

terminal.

Recommended Operating Conditions

Item

Symbol

Min

2

Typ

—

Max

6

Unit

V

Supply voltage

V_CC

Input / output voltage

Operating temperature

Input rise / fall time ^*1

V_IN/

0

—

V_CC

+85

1000

500

400

V

OUT

Topr

tr, tf

–40

0

—

°C

ns

V_CC= 2.5 V

V_CC= 4.5 V

V_CC= 5.5 V

—

0

—

0

—

Note: 1. This item guarantees maximum limit when one input switches.

4

HD151011

Logic Diagram

C/T

CLK

J0

J1

J2

J3

J4

J5

J6

J7

J0

J1

J2

J3

J4

J5

J6

J7

CLK

CO

PR

D

Q

CO

CK

Q

CLR

SPE

CLR

5

HD151011

Electrical Characteristics

Ta = 25°C

Ta = –40 to 85°C

Max Min Max Unit Test Conditions

Item

Symbol V_CC

Min

1.5

Typ

High level input

voltage

V_IH

2.0

4.5

6.0

2.0

4.5

6.0

—

1.5

—

V

J0 to J7

3.15

4.2

3.15

4.2

C/T, SPE

PR, CLR

1.5

CLK, CLK C/T = V_IH

3.15

4.2

3.15

4.2

4.5 to 2.0

5.5

2.0

C/T = V_IL

Low level input

voltage

V_IL

2.0

4.5

6.0

2.0

4.5

6.0

—

0.5

—

0.5

V

J0 to J7

1.35

1.8

1.35

1.8

C/T, SPE

PR, CLR

0.5

CLK, CLK C/T = V_IH

1.35

1.8

1.35

1.8

4.5 to

5.5

0.8

C/T = V_IL

High level output V_OH

voltage

2.0

1.9

2.0

—

1.9

—

V

V_IN=

V_IHor V_IL

I_OH= –20 µA

4.5

6.0

4.5

6.0

2.0

4.4

5.9

4.5

6.0

—

0.1

4.4

—

0.1

5.9

4.18 4.31

5.68 5.80

4.13

5.63

—

I_OH= –4 mA

I_OH= –5.2 mA

I_OL= 20 µA

Low level output

voltage

V_OL

—

0.0

V

V_IN=

V_IHor V_IL

4.5

6.0

4.5

6.0

—

0.0

0.1

—

0.1

0.17 0.26

0.18 0.26

0.33

I_OL= 4 mA

I_OL= 5.2 mA

Input capacitance IIN

Supply current I_CC

—

±0.1

±1.0 mA

V_IN= V_CCor GND

4.0

40.0 mA

6

HD151011

Switching Characteristics (C_L= 50 pF, tr = tf = 6 ns)

Ta = 25°C

Ta = –40 to 85°C

Item

Symbol V_CC

Min Typ Max Min

Max

Unit Test Conditions

Maximum clock

frequency

fmax

2.0

—

4

—

3

MHz

4.5

6.0

2.0

4.5

6.0

2.0

—

36

—

30

8

20

24

75

15

13

250

—

16

19

95

19

16

318

Output rise / fall time t_TLH

t_THL

ns

7

Propagation delay

time

t_PLH

t_PHL

—

ns

CLK or CLK to CO

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

—

80

16

14

100

20

17

15

10

5

30

—

35

—

18

—

5

50

45

300

60

53

150

30

25

—

100

20

17

125

25

21

15

10

5

63

53

380

75

65

185

38

32

—

t_PLH

t_PHL

CLK or CLK to Q

t_PLH

t_PHL

PR or CLR to Q

Pulse width

tw

ts

ns

(CLK, CLK, PR, CLR)

—

Setup time

—

(Jn - CLK, CLK)

(SPE, CLK, CLK)

Hold time

—

th

—

(Jn - CLK, CLK)

(SPE, CLK, CLK)

Input capacitance

—

C_IN

—

10

—

10

—

pF

Power dissipation

capacitance

C_PD

—

48

Note: 1. CPD is equivalent capacitance inside of the IC calculated from the operating current without load

(see test circuit). The average operating current without load is calculated according to the

expression below.

I

_CC(opr) = C_PDV_CC• f_IN+ I_CC

7

HD151011

• Test Circuit

V_CC

Input

J0

J1

Output

Pulse generator

Q

Z_out= 50 Ω

Output

CO

J7

Input

C/T

CLK

SPE

PR

Pulse generator

Z_out= 50 Ω

C_L

CLR

Note: 1. C_Lincludes probe and jig capacitance.

• Waveforms – 1

t

w

6 ns

*1

V

CLK

IH

90 % 90 %

*1 *1

V

ref

10 %

GND

V_OH

V_OL

t_PLH

t_PHL

90 %

50 %

90 %

50 %

Q

10 %

t_THL

t_TLH

t_PLH

t_PHL

V_OH

90 %

50 %

CO

10 %

t_THL

V_OL

t_TLH

Note:

1. In case of C/T = "L", CLK, CLK is V_IH= 3 V, Vref is 1.3 V

In case of C/T = "H", CLK, CLK is V_IH= V_CC, Vref is V_CC× 50%

8

HD151011

• Waveforms – 2

6 ns

V_CC

90 %

10 %

90 %

50 %

10 %

Jn

GND

t

s

*1

CLK

V

IH

90 %

*1

ref

V

10 %

6 ns

GND

V_OH

*2

50 %

F/F Output

V_OL

Internal delay

Notes:

1. In case of C/T = "L", CLK, CLK is V_IH= 3 V, Vref is 1.3 V

In case of C/T = "H", CLK, CLK is V_IH= V_CC, Vref is V_CC× 50%

2. F/F output is internal signal of IC.

• Waveforms – 3

6 ns

V_CC

90 %

50 %

10 %

Jn

10 %

h

GND

t

*1

CLK

V

IH

90 %

*1

ref

V

10 %

6 ns

GND

V_OH

*2

50 %

F/F Output

V_OL

Internal delay

Notes:

1. In case of C/T = "L", CLK, CLK is V_IH= 3 V, Vref is 1.3 V

In case of C/T = "H", CLK, CLK is V_IH= V_CC, Vref is V_CC× 50%

2. F/F output is internal signal of IC.

9

HD151011

• Waveforms – 4

6 ns

V_CC

90 %

10 %

90 %

50 %

10 %

SPE

GND

t

s

*1

CLK

V

IH

90 %

*1

ref

V

10 %

6 ns

GND

V_OH

*2

50 %

F/F Output

V_OL

Internal delay

Notes:

1. In case of C/T = "L", CLK, CLK is V_IH= 3 V, Vref is 1.3 V

In case of C/T = "H", CLK, CLK is V_IH= V_CC, Vref is V_CC× 50%

2. F/F output is internal signal of IC.

• Waveforms – 5

6 ns

V_CC

90 %

50 %

10 %

SPE

10 %

h

GND

t

*1

CLK

V

IH

90 %

*1

ref

V

10 %

6 ns

GND

V_OH

*2

50 %

F/F Output

V_OL

Internal delay

Notes:

1. In case of C/T = "L", CLK, CLK is V_IH= 3 V, Vref is 1.3 V

In case of C/T = "H", CLK, CLK is V_IH= V_CC, Vref is V_CC× 50%

2. F/F output is internal signal of IC.

10

HD151011

• Waveforms – 6

t

r

f

V_CC

90 %

50 %

10 %

90 %

50 %

10 %

CLR

GND

t

w

t

r

f

V_CC

90 %

50 %

10 %

90 %

50 %

10 %

PR

GND

t

w

t

PLH

PHL

V_OH

Q

50 %

V_OL

11

HD151011

Timing Chart

CLK

SPE

J0

J1

J2

J3

J4

J5

J6

J7

(CO=SPE)

CLR

(Initialize of CLR)

Q

PR

(Initialize of PR)

Q

Count

5

4

3

2

1

0

3

2

1

0

23

22

12

HD151011

Example of Application Circuit

• AC Signal Generator for STN Type Liquid Crystal Panel

CLK (CLK) :

Initialize counter :

CMOS level input

32

V_CC

(Test 1)

(Test 2)

CO

J 0

J 1

J 2

J 3

J 4

J 5

J 6

J 7

GND

NC

C/T

CLK

Q

PR

*

SPE

CLR

*

*When initializing output D-F/F apply "L"

13

HD151011

Timing Chart

• Example of AC Signal Generator

1

2

3

31

32

33

34

35

65

66

67

68

CLK

SPE

J0

J1

J2

J3

J4

J5

J6

J7

1digit=2

2digits=3

(CO=SPE)

CLR

Q

PR

Q

32

31

30

2

1

0

32

31

1

0

32

31

Count

14

HD151011

Package Dimensions

Unit : mm

Unit: mm

6.50

6.80 Max

20

1

11

10

0.65

1.0

+0.08

–0.07

0.22

0.13

M

0.20 ± 0.06

6.40 ± 0.20

0.65 Max

0° – 8°

0.50 ± 0.10

0.10

Hitachi Code

TTP-20DA

JEDEC

EIAJ

—

Dimension including the plating thickness

Base material dimension

Weight (reference value) 0.07 g

15

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,

copyright, trademark, or other intellectual property rights for information contained in this document.

Hitachi bears no responsibility for problems that may arise with third party’s rights, including

intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high

quality and reliability or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,

traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation

conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used

beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable

failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-

safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other

consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

Hitachi, Ltd.

Semiconductor & Integrated Circuits.

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

URL

NorthAmerica

Europe

: http:semiconductor.hitachi.com/

: http://www.hitachi-eu.com/hel/ecg

Asia (Singapore)

Asia (Taiwan)

: http://www.has.hitachi.com.sg/grp3/sicd/index.htm

: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm

Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm

Japan

: http://www.hitachi.co.jp/Sicd/indx.htm

For further information write to:

Hitachi Semiconductor

(America) Inc.

Hitachi Europe GmbH

Hitachi Asia (Hong Kong) Ltd.

Group III (Electronic Components)

7/F., North Tower, World Finance Centre,

Harbour City, Canton Road, Tsim Sha Tsui,

Kowloon, Hong Kong

Tel: <852> (2) 735 9218

Fax: <852> (2) 730 0281

Hitachi Asia Pte. Ltd.

16 Collyer Quay #20-00

Hitachi Tower

Singapore 049318

Tel: 535-2100

Electronic components Group

Dornacher Stra§e 3

D-85622 Feldkirchen, Munich

Germany

Tel: <49> (89) 9 9180-0

Fax: <49> (89) 9 29 30 00

179 East Tasman Drive,

San Jose,CA 95134

Tel: <1> (408) 433-1990

Fax: <1>(408) 433-0223

Fax: 535-1533

Hitachi Asia Ltd.

Taipei Branch Office

3F, Hung Kuo Building. No.167,

Tun-Hwa North Road, Taipei (105)

Tel: <886> (2) 2718-3666

Fax: <886> (2) 2718-8180

Telex: 40815 HITEC HX

Hitachi Europe Ltd.

Electronic Components Group.

Whitebrook Park

Lower Cookham Road

Maidenhead

Berkshire SL6 8YA, United Kingdom

Tel: <44> (1628) 585000

Fax: <44> (1628) 778322


型号：	HD151011
厂家：	HITACHI SEMICONDUCTOR
描述：	Dual BCD Programmable Counter with Synchronous Preset Enable 双BCD可编程计数器，同步预设启用计数器 CD
文件：	总16页 (文件大小：76K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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