HD153510F50 [HITACHI]
D/A Converter, PQFP56, PLASTIC, QFP-56;
| 型号： | HD153510F50 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | D/A Converter, PQFP56, PLASTIC, QFP-56 转换器 |
| 文件： | 总11页 (文件大小：5733K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD153510
Three Channel 8-Bit D/A Converter for High Resolution Color Graphics
Description
Features
The HD153510 is an integrated circuit that per-
forms D/A conversion for the generation of analog
signals appropriate for use as CRT analog video
input signals. It provides three channels of high-
speed high-precision 8-bit D/A conversion, and can
be used with systems that display images of up to
16.77 million colors by outputting 8 bits of red,
green, and blue data.
• Provides 3 channels of 8-bit D/A conversion on-
chip
• Maximum operating frequencies of 50 or 135
MHz
• TTL compatible data input levels
• Composite or non-composite versions of the
BLANK and SYNC signals required for CRT
screen control can be selected
• Power consumption of 400 mW (at 50 MHz) or
550 mW (at 135 MHz) (typical values)
• Provided in a 56-pin QFP package that is opti-
mal for miniature surface mounting
Ordering Information
Maximum Operating
Product Number
HD153510F50
HD153510F135
Frequency
Package
50 MHz
56-pin plastic QFP (FP-56)
135 MHz
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HD153510
HD153510
Pin Arrangement
DGND
DC6
43
44
45
46
47
48
49
50
51
52
53
54
55
56
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DGND
DGND
IOC
DC5
DC4
IOA
DVCC
DVCC
DGND
DGND
DGND
DC0
IOB
ISYNC
VCC
VCC
DGND
AGND
DGND
REXT
VREF
DGND
DC1
DC2
DC3
DGND
Top view
2
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HD153510
HD153510
Pin Description
Pin
Pin No.
I/O
Functional Overview
DOTCK
3
I
The reference clock signal input pin. Data is read in and analog
signals are output on the rising edge of this signal.
DA0 to DA7
DB0 to DB7
DC0 to DC7
BLANK
4 to 7, 39 to 36
8 to 11, 35 to 32
I
I
I
I
The A channel D/A converter input pins. DA7 is the MSB, and
DA0 is the LSB.
The B channel D/A converter input pins. DB7 is the MSB, and
DB0 is the LSB.
52 to 55,
46, 45, 44, 40
The C channel D/A converter input pins. DC7 is the MSB, and
DC0 is the LSB.
31
30
12
The input pin for the signal that sets the D/A converter outputs to
the blank level. When BLANK is 0, the outputs go to the blank
level.
SYNC
BSEL
I
I
The input pin for the signal that sets the D/A converter outputs to
the sync level. When SYNC is 0, the analog output shorted to
ISYNC goes to the sync level.
The input pin for selecting the D/A converter blank level. When
BSEL is 0, the blank level is 7.5 IRE, and when 1, 0 IRE.
IOA
25
24
26
23
O
O
O
O
The A channel D/A converter analog signal output pin.
The B channel D/A converter analog signal output pin.
The C channel D/A converter analog signal output pin.
IOB
IOC
ISYNC
The sync level output pin. When composite sync is used,
connect one of IOA, IOB, or IOC to this pin.
REXT
VREF
COMP
17
16
13
—
—
—
Connect the external resistance (REXT = 542 Ω) that sets the D/A
converter output level between this pin and ground.
The pin for supplying the D/A converter reference voltage. Apply
a voltage of VREF = 1.200 V from an external circuit.
The phase compensation capacitor pin. Connect a 0.1 µF
ceramic capacitor and a 4.7 to 10 µF electrolytic capacitor to this
pin.
DVCC
AVCC
DGND
22, 47, 48
21
—
—
—
The digital power supply voltage pin.
The analog power supply voltage pin.
The digital ground pin.
1, 2, 14, 15, 18,
20, 27 to 29,
41 to 43,
49 to 51, 56
AGND
19
—
The analog ground pin.
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HD153510
HD153510
Block Diagram
VCC
GND
VREF
REXT
+
–
COMP
DOTCK
8
DAC
IOA
DA0 to DA7
8
8
DAC
DAC
DB0 to DB7
DC0 to DC7
IOB
IOC
Register
BLANK
SYNC
SYNC
output
ISYNC
BSEL
4
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HD153510
HD153510
Functional Description
BLANK and SYNC Control Signal Inputs: The
outputs of channels A, B, and C can be set to the
blank level by pulling the BLANK signal input
low. The BLANK signal input is latched into an
internal register on the rise of the DOTCK signal.
The outputs will be fixed at the blank level without
regard for the DA0 to DA7, DB0 to DB7, and DC0
to DC7 inputs during intervals when the BLANK
input is 0. (See figure 1.)
D/A Converter Data Input: There are three 8-bit
D/A converters built-in; channels A, B, and C.
These channels take their data inputs from pins
DA0 to DA7, DB0 to DB7, and DC0 to DC7
respectively. Taking channel A as an example, the
input pin to data correspondence is as follows:
DA7 is the high order bit, and DA0 is the low
order bit. To output a white level, set all bits DA7
through DA0 to the high level, and to output a
black level, set all bits DA7 through DA0 to the
low level. Data is latched into an internal register
on the rise of the DOTCK signal. The D/A
converter output switches to the next value with
the rise of the DOTCK signal as the reference. (See
figure 1.)
When the SYNC signal is combined with the D/A
converter output, the ISYNC pin must be
connected to one of the IOA, IOB, and IOC pins.
The SYNC input signal must only go low when the
BLANK signal is already low. The SYNC signal is
also latched on the rise of the DOTCK signal.
Video Output Waveforms: (See figure 2.)
DOTCK
DA0 to DA7,
DB0 to DB7,
DC0 to DC7
N – 1
N
N + 1
N + 2
N + 3
BLANK
tpd
Blank level
N – 2
N – 1
N
N + 1
IOA, IOB, IOC
Figure 1 Data I/O Timing
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HD153510
HD153510
1. Pedestal level on, SYNC non-composite (BSEL = 0, ISYNC: not connected)
White level
714 mV
Grey scale
92.5 IRE
Full
scale
Black level
Blank level
54 mV
0 mV
7.5 IRE
2. Pedestal level off, SYNC non-composite (BSEL = 1, ISYNC: not connected)
White level
660 mV
Grey scale
100 IRE
Full
scale
Black/Blank level
0 mV
3. Pedestal level on, SYNC composite (BSEL = 0, ISYNC: connected)
White level
1000 mV
Grey scale
92.5 IRE
Full
scale
Black level
Blank level
Sync level
340 mV
286 mV
0 mV
7.5 IRE
40 IRE
4. Pedestal level off, SYNC composite (BSEL = 1, ISYNC: connected)
White level
946 mV
Grey scale
100 IRE
Full
scale
Black/Blank level
Sync level
286 mV
0 mV
43 IRE
Figure 2 Video Output Waveforms (R = 37.5 Ω, R
= 542 Ω, V
= 1.200 V)
L
EXT
REF
6
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HD153510
HD153510
Absolute Maximum Ratings
Item
Symbol
VCC
VIN
Rated Value
7.0
Unit
V
Power supply voltage
Input voltage
–0.3 to VCC
0 to –28
V
D/A converter output current
Operating temperature
Storage temperature
IOA
mA
°C
°C
Topr
0 to +70
Tstg
–55 to +150
Recommended Operating Conditions
Item
Symbol
Min
Typ
5.00
—
Max
Unit
V
Power supply voltage
Input high voltage
VCC
VIH
4.75
2.0
0
5.25
VCC
0.8
70
V
Input low voltage
VIL
—
V
Operating temperature
D/A converter output load resistance
D/A converter output load capacitance
Reference voltage
Topr
RL
0
25
°C
Ω
—
—
—
—
37.5
15
—
CL
—
pF
V
VREF
REXT
1.200
542
—
Resistance connected to REXT
—
Ω
Caution: ESD sensitive devices. So, be carefull of using them.
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HD153510
HD153510
Electrical Characteristics
DC Characteristics (Ta = 25°C, VCC = 5.0 V)
HD153510F50
HD153510F135
Test
Item
Symbol Min
Typ
—
Max
VCC
0.8
1
Min
2.0
–0.3
—
Typ
—
Max
VCC
0.8
1
Unit
V
Conditions*
Input high voltage
Input low voltage
Input current
VIH
VIL
II
2.0
–0.3
—
0.
—
—
V
—
—
mA
VCC = 5.25 V,
VI = 5.5 V
Input high current
Input low current
IIH
IIL
—
—
—
—
20
—
—
—
—
20
µA
µA
VCC = 5.25 V,
VI = 2.7 V
–400
–400
VCC = 5.25 V,
VI = 0.4 V
VREF input current
Resolution
IREF
—
—
8
–60
8
—
8
—
8
–60
8
—
8
µA
bits
Analog output voltage
error (full scale)
VA (Full) –7
—
+7
–7
—
+7
% of
FSR
Analog output voltage
error (zero scale)
VA (Zero) –2
—
+2
–2
—
+2
Differential linearity error DLE
–1
–2
—
—
—
80
+1.5
+2
–1
–2
—
—
+1.5
+2
LSB
mA
Integral linearity error
Current dissipation
ILE
ICC
—
130
110
150
VCC = 5.25 V
Note: * Unless specified otherwise, RL = 37.5 Ω, REXT = 542 Ω, VREF = 1.200 V
8
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HD153510
HD153510
AC Characteristics (Ta = 25°C, VCC = 5.0 V)
HD153510F50
HD153510F135
Test
Item
Symbol
Min
20.0
8.0
8.0
1
Typ
—
—
—
1
Max
—
—
—
1
Min
7.4
3.2
3.2
1
Typ
—
—
—
1
Max
—
—
—
1
Unit Conditions*1
Clock cycle
tcyc
ns
ns
Figure 3
Clock low level period tCLKL
Clock high level period tCLKH
ns
Pipeline delay
—
clock
ns
Data setup time
Data hold time
tsu1
th1
tsu2
th2
6.0
2.0
6.0
2.0
6.0
2.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
4.0
1.0
5.0
1.0
5.0
1.0
—
—
—
Figure 3
ns
BLANK setup time
BLANK hold time
SYNC setup time
SYNC hold time
—
—
—
—
—
—
—
—
—
5
ns
ns
tsu3
th3
ns
ns
Video output rise time*2 tr
ns
Figure 3
CL = 15 pF
Video output fall time*2 tf
—
—
—
8
—
—
—
5
ns
ns
Settling time*3
Glitch energy
ts
12
—
7.4
—
Figure 3
CL = 15 pF
Eg
tpd
—
—
90
—
—
—
—
90
—
—
pVs
ns
Video output delay
time
20
20
Figure 3
CL = 15 pF
Notes: 1. Unless specified otherwise, RL = 37.5 Ω, REXT = 542 Ω, VREF = 1.200 V
2. A transition time of 20 to 80% of the output waveform
3. The time until stabilized to within ±5% of FSR from 50% of the output waveform.
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HD153510
HD153510
AC Characteristics Measurement Timing
tcyc
tCLKH
tCLKL
≤ 2 ns
≤ 2 ns
3 V
90%
10%
90%
1.5 V
DOTCK
10%
0 V
≤ 2 ns
tsu1
th1
3 V
DA0 to DA7,
DB0 to DB7,
DC0 to DC7
90%
1.5 V
1.5 V
1.5 V
1.5 V
10%
0 V
tsu2
th2
≤ 2 ns
3 V
90%
BLANK
SYNC
1.5 V
10%
0 V
≤ 2 ns
tsu3
th3
3 V
90%
1.5 V
10%
0 V
tf
tr
80%
50%
20%
80%
50%
20%
IOA, IOB, IOC
tpd
ts
tpd
ts
Figure 3 AC Characteristics Measurement Timing
10
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HD153510
HD153510
Circuit Example
HD153510
System ground
(GND)
COMP
VCC
0.1 µF
–
+
10 µF
+5 V
0.1 µF
+
–
0.1 µF
4.7 µF
1 kΩ
VREF
REXT
1.2 V
542 Ω
CRT
75 Ω coaxial cable
75 Ω coaxial cable
75 Ω coaxial cable
IOA
IOC
75 Ω
75 Ω
75 Ω
75 Ω
75 Ω
75 Ω
IOB
ISYNC
GND
In this example, the IOB pin is used with SYNC composite.
Note: The recommended circuit is shown in the example.
Decide each capacitor capacity after a mount evaluation.
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