HD40C4342RFP [HITACHI]
4-bit microcomputers; 4位微型计算机
| 型号： | HD40C4342RFP |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 4-bit microcomputers |
| 文件： | 总100页 (文件大小：610K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD404344R Series/HD404394 Series
Rev. 7.0
Sept. 1999
Description
The HD404344R series and HD404394 series 4-bit microcomputers are products of the HMCS400 series,
which is designed to make application systems compact while realizing higher performance and increasing
program productivity.
Each microcomputer has an A/D converter, two timers and a serial interface. The HD404344R series
includes the HD404344R with on-chip 4-kword ROM, HD404342R with 2-kword ROM, and HD404341R
with 1-kword ROM. The HD404394 series includes the HD404394 with on-chip 4-kword ROM,
HD404392 with 2-kword ROM, and HD404391 with 1-kword ROM.
The HD4074344 and HD4074394 are the PROM version ZTAT microcomputers. Programs can be
written to the PROM by a PROM writer, which can dramatically shorten system development periods and
smooth the process from debugging to mass production. (The PROM program specifications are the same
as for the 27256.)
ZTAT : Zero Turn Around Time ZTAT is a Trademark of Hitachi Ltd.
Features
•
Input/output pins
HD404344R series, HD4074344: 22 pins
(10pins: Large-current I/O pins)
HD404394 series: 21 pins
(3 pins: intermediate-voltage NMOS open drain I/O; 5 pins: NMOS open drain I/O with 15-mA
high-current driver)
•
Two timer/counters
One timer output
One event counter input (with programmable edge detection)
8-bit clock-synchronous serial interface (1 channel)
On-chip A/D converter
•
•
HD404344R series, HD4074344: 8 bit × 4 channel
HD404394 series: 8 bit × 3 channel (with Vref pin)
Built-in oscillator
•
HD404344R Series/HD404394 Series
HD404344R Series
Ceramic oscillator, CR oscillation, External clock drive is also possible.
HD404394 Series, HD4074344
Ceramic oscillator, External clock drive is also possible.
•
Five interrupt sources
One by external source (with programmable edge detection)
Four by internal sources
•
•
Subroutine stack
Maximum 16 levels including interrupts
Two low-power dissipation modes
Standby mode
Stop mode
•
•
One input signal to return from stop mode
Instruction cycle time
1 µs (fOSC = 4 MHz)
2
HD404344R Series/HD404394 Series
Type of Products
Product Name
HD404344R
Series*1
HD404394
Series
Type
ROM (words)
RAM (digit)
Package
Mask ROM
HD404341RS
HD404391S
HD404392S
HD404394S
HD404391FP
HD404392FP
HD404394FP
HD404391FT
HD404392FT
HD404394FT
——
1,024
256
DP-28S
HD40C4341RS
HD404342RS
2,048
4,096
1,024
2,048
4,096
1,024
2,048
4,096
4,096
4,096
HD40C4342RS
HD404344RS
HD40C4344RS
HD404341RFP
HD40C4341RFP
HD404342RFP
HD40C4342RFP
HD404344RFP
HD40C4344RFP
HD404341RFT
HD40C4341RFT
HD404342RFT
HD40C4342RFT
HD404344RFT
HD40C4344RFT
HCD404344R
HCD40C4344R
HD4074344S
FP-28DA
FP-30D
Chip*3 *4
ZTAT
HD4074394S
HD4074394FP
HD4074394FT
DP-28S
FP-28DA
FP-30D
HD4074344FP
HD4074344FT
Note: 1. The HD404344R Series is available in a mask ROM version only.
2. ZTAT chip shipment is not supprted.
3. The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details.
3
HD404344R Series/HD404394 Series
List of Functions
Mask ROM
item
HD404341R HD404342R HD404344R HCD404344R HD40C4341R HD40C4342R HD40C4344R
Operating voltage (V)
2.5 to 5.5
2.5 to 5.5
2.5 to 5.5
2.5 to 5.5
2.5 to 5.5
2.5 to 5.5
2.5 to 5.5
Instruction cycle time (typ.) 1 µs
(fosc = 4.0
1 µs
1 µs
1 µs
2 µs
2 µs
2 µs
(fosc = 4.0
MHz)
(fosc = 4.0
MHz)
(fosc = 4.0
MHz)
(Rf = 20 kΩ)
(Rf = 20 kΩ)
(Rf = 20 kΩ)
MHz)
1,024
256
22
ROM (Words)
RAM (Digits)
I/O
2.048
256
22
4,096
256
22
4,096
256
22
1,024
256
22
2,048
256
22
4,096
256
22
High-current
I/O pins (Sink
15 mA max)
10
10
10
10
10
10
10
Timer
Free running
timer
2
2
2
2
2
2
2
functions
Reload timer
Event counter
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
Watchdog
timer
Serial interface
A/D converter
1
1
1
1
1
1
1
8bit × 4ch
8bit × 4ch
8bit × 4ch
8bit × 4ch
8bit × 4ch
8bit × 4ch
8bit × 4ch
Interrupt
External
Internal
Low-power modes
Stop mode
1
1
1
1
1
1
1
4
4
4
4
4
4
4
2
2
2
2
2
2
2
●
●
●
●
●
●
●
●
●
●
●
●
●
●
—
●
●
—
●
●
—
Standby mode
Oscillator
Package
Ceramic
oscillation
RC oscillation
—
—
—
—
●
●
●
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
Chip
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
Guaranteed operation
–20 to +75
–20 to +75
–20 to +75
+75
–20 to +75
–20 to +75
–20 to +75
temperature (°C)
4
HD404344R Series/HD404394 Series
List of Functions (cont)
Mask ROM
ZTAT
item
HCD40C4344R HD4074344
Operating voltage (V)
2.7 to 5.5
2.7 to 5.5
Instruction cycle time (typ.) 2 µs
(Rf = 20 kΩ)
1 µs
(fosc = 4.0 MHz)
ROM (Words)
RAM (Digits)
I/O
4,096
4,096 PROM
256
22
256
22
High-current
I/O pins (Sink
15 mA max)
10
10
Timer
Free running
timer
2
2
functions
Reload timer
Event counter
2
1
1
2
1
1
Watchdog
timer
Serial interface
A/D converter
1
1
8bit × 4ch
8bit × 4ch
Interrupt
External
Internal
Low-power modes
Stop mode
1
1
4
4
2
2
●
●
—
●
●
●
Standby mode
Oscillator
Package
Ceramic
oscillation
RC oscillation
●
—
Chip
DP-28S
FP-28DA
FP-30D
Guaranteed operation
+75
–20 to +75
temperature (°C)
5
HD404344R Series/HD404394 Series
List of Functions (cont)
Mask ROM
ZTAT
item
HD404391
HD404392
HD404394
HD4074394
2.7 to 5.5
Operating voltage (V)
2.7 to 5.5
2.7 to 5.5
2.7 to 5.5
Instruction cycle time (typ.) 1 µs
(fosc = 4.0
1 µs
1 µs
1 µs
(fosc = 4.0
MHz)
(fosc = 4.0
MHz)
(fosc = 4.0
MHz)
MHz)
1,024
256
21
ROM (Words)
RAM (Digits)
I/O
2.048
256
21
4,096
256
21
4,096 PROM
256
21
3
intermediate-
voltage NMOS
open drain I/O
3
3
3
NMOS open
drain I/O (15
mA High
5
5
5
5
current driver)
Timer
Free running
timer
2
2
2
2
functions
Reload timer
Event counter
2
1
1
2
1
1
2
1
1
2
1
1
Watchdog
timer
Serial interface
A/D converter
1
1
1
2
8bit × 3ch
8bit × 3ch
8bit × 3ch
8bit × 3ch
Interrupt
External
Internal
Low-power modes
Stop mode
1
1
1
1
4
4
4
4
2
2
2
2
●
●
●
●
●
●
●
●
●
●
●
●
Standby mode
Oscillator
Package
Ceramic
oscillation
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
Guaranteed operation
–20 to +75
–20 to +75
–20 to +75
–20 to +75
temperature (°C)
6
HD404344R Series/HD404394 Series
Pin Arrangement
HD404344R Series, HD4074344
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R10
R11
R12
R13
R20
R21
R22
R23
D5
R10
R11
R12
R13
R20
R21
R22
R23
D5
2
2
D4/STOPC
D3
D2
D4/STOPC
D3
D2
3
3
4
4
5
5
D1
D1
6
6
D0/INT0/EVNB
R03/TOC
R02/SO
R01/SI
R00/SCK
RESET
TEST/VPP
VCC
D0/INT0/EVNB
R03/TOC
R02/SO
R01/SI
R00/SCK
RESET
TEST/VPP
VCC
7
7
DP-28S
FP-28DA
FP-30D
8
8
9
9
OSC1
OSC2
GND
R30/AN0
R31/AN1
R32/AN2
OSC1
OSC2
GND
NC
R30/AN0
R31/AN1
R32/AN2
10
10
11
12
13
14
15
11
12
13
14
R33/AN3
NC
R33/AN3
Top view
HD404394 Series
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R10
R11
R12
R13
R20
R21
R22
R23
D5
R10
R11
R12
R13
R20
R21
R22
R23
D5
2
2
D4/STOPC
D3
D2
D4/STOPC
D3
D2
3
3
4
4
5
5
D1
D1
6
6
D0/INT0/EVNB
R03/TOC
R02/SO
R01/SI
R00/SCK
RESET
TEST/VPP
VCC
D0/INT0/EVNB
R03/TOC
R02/SO
R01/SI
R00/SCK
RESET
TEST/VPP
VCC
7
7
DP-28S
FP-28DA
FP-30D
8
8
9
9
OSC1
OSC2
GND
Vref
R31/AN1
R32/AN2
OSC1
OSC2
GND
NC
Vref
R31/AN1
R32/AN2
10
10
11
12
13
14
15
11
12
13
14
R33/AN3
NC
R33/AN3
Top view
7
HD404344R Series/HD404394 Series
Pad Arrangement
HCD404344R, HCD40C4344R
30
29
28
27
26
25
1
2
3
4
5
6
24
23
22
21
20
19
18
17
7
8
9
Type Code
10
11
12
13
14
15
16
Type Code: HD404344R (HCD404344R)
HD40C4344R (HCD40C4344R)
8
HD404344R Series/HD404394 Series
Bonding Pad Coordinates
HCD404344R, HCD40C4344R
Chip size (X × Y): 3.23 × 3.65 (mm)
Coordinates: Pad center
Home point position: Chip center
Pad size (X × Y): 90 × 90 (µm)
Chip thickness: 400 (µm)
Chip center
(X=0, Y=0)
Type Code
Coordinates
X (µm)
–1425
–1425
–1425
–1425
–1425
–1425
–1425
–1425
–1425
–1257
–891
Coordinates
Pad
Pad
No.
Pad Name
R13
Y (µm) No.
1370 16
1050 17
732 18
Pad Name
TEST
RESET
R00
R01
R02
R03
D0
X (µm)
1360
1418
1418
1418
1418
1418
1418
1418
1418
1075
693
Y (µm)
–1627
–1456
–1072
–690
–306
312
1
2
3
4
5
6
7
8
9
R20
R21
R22
455 19
R23
165 20
OSC1
OSC2
GND
GND
–115 21
–732 22
–997 23
–1244 24
–1627 25
–1627 26
–1627 27
–1627 28
–1627 29
–1627 30
694
D1
1098
1501
1627
1627
1627
1627
1627
1627
D2
10 R30
11 R31
12 R32
13 R33
14 VCC
15 VCC
D3
D4
–526
D5
309
–162
R10
R11
R12
–329
–732
–1135
420
804
9
HD404344R Series/HD404394 Series
Pin Description
HD404344R Series, HD4074344
Pin Number
DP-28S/
Item
Symbol
VCC
FP-28DA FP-30D Chip
I/O Function
Applies power voltage
Power supply
16
11
17
18
11
19
14, 15
8, 9
GND
Connects to ground
Test
TEST
16
I
Cannot be used in user applications.
Connect this pin to GND.
Reset
RESET
18
9
20
9
17
6
I
I
Resets the MCU
Oscillator
OSC1
Input/output pins for the internal
oscillator. Connect these pins to the
ceramic oscillator, or OSC1 to an external
oscillator circuit.
OSC2
D0–D5
10
10
7
O
Port
23–28
25–30 22–27 I/O Input/output pins addressed individually
by bits; pins D1 and D2 can sink 15 mA
max.
R00–R03, 1–8,
R10–R13, 12–15
R20–R23, 19–22
R30–R33
1–8,
18–21, I/O Four-bit input/output pins.
13–16, 28–30,
21–24 1–5,
10–13
Pins R10–R23 can sink 15 mA max.
Interrupt
INT0
23
27
25
29
22
26
I
I
Input pin for external interrupts
Stop clear
STOPC
Input pin for transition from stop mode to
active mode
Serial interface
SCK
SI
19
20
21
22
23
21
22
23
24
25
18
19
20
21
22
I/O Serial interface clock input/output pin
I
Serial interface receive data input pin
Serial interface transmit data output pin
Timer output pin
SO
O
O
I
Timer
TOC
EVNB
Event count input pin
A/D converter
AN0–AN3 12–15
13–16 10–13
I
Analog input pins for the A/D converter
10
HD404344R Series/HD404394 Series
HD404394 Series
Pin Number
DP-28S/
Item
Symbol FP-28DA FP-30D I/O Function
Power supply
VCC
16
11
17
18
11
19
Applies power voltage
Connects to ground
GND
TEST
Test
I
Cannot be used in user applications. Connect
this pin to GND.
Reset
RESET
18
9
20
9
I
I
Resets the MCU
Oscillator
OSC1
Input/output pin for the internal oscillator.
Connect these pins to the ceramic oscillator, or
OSC1 to an external oscillator circuit
OSC2
D0–D5
10
10
O
Port
23–28
25–30
I/O Input/output pins addressed individually by bits;
pins D1 and D2 can sink 15 mA max.
R00–R03, 1–8,
R10–R13, 13–15
R20–R23, 19–22
R31–R33
1–8,
I/O Four-bit input/output pins. Pins R10–R12 are
NMOS intermediate-voltage open drain pins.
Pins R13–R23 are NMOS standard-voltage open
drain pins which can sink 15 mA max.
14–16,
21–24
Interrupt
INT0
23
27
25
29
I
I
Input pin for external interrupts
Stop clear
STOPC
Input pin for transition from stop mode to active
mode
Serial interface
SCK
SI
19
20
21
22
23
12
21
22
23
24
25
13
I/O Serial interface clock input/output pin
I
Serial interface receive data input pin
Serial interface transmit data output pin
Timer output pin
SO
O
O
I
Timer
TOC
EVNB
Vref
Event count input pin
A/D converter
Power supply for the internal ladder resistor in
the A/D converter
AN1–AN3 13–15
14–16
I
Analog input pins for the A/D converter
11
HD404344R Series/HD404394 Series
HD404344R Series, HD4074344 Block Diagram
System control
Interrupt
control
D
D
D
D
D
D
0
1
2
3
4
5
INT
0
RAM
(256 × 4 bits)
W
(2 bits)
Timer B
Timer C
EVNB
TOC
X
(4 bits)
R0
R0
R0
R0
0
1
2
3
SPX
(4 bits)
Y
(4 bits)
SI
SO
Serial
interface
R1
R1
R1
R1
0
1
2
3
SCK
SPY
(4 bits)
AN
AN
0
1
A/D
converter
R2
R2
R2
R2
0
1
2
3
AN
AN
2
3
ALU
CA
ST
R3
R3
R3
R3
(1 bit)
(1 bit)
0
1
2
3
A
(4 bits)
B
(4 bits)
SP
(10 bits)
Data bus
Instruction
decoder
PC
(14 bits)
Large-current
pin
ROM
(1,024 × 10 bits)
(2,048 × 10 bits)
(4,096 × 10 bits)
Bidirectional
signal line
12
HD404344R Series/HD404394 Series
HD404394 Series Block Diagram
System control
D
D
D
D
D
D
0
1
2
3
4
5
Interrupt
control
INT
0
RAM
(256 × 4 bits)
W
(2 bits)
Timer B
Timer C
EVNB
X
(4 bits)
R0
R0
R0
R0
0
1
2
3
SPX
TOC
(4 bits)
Y
(4 bits)
SI
SO
R1
R1
R1
R1
0
1
2
3
Serial
interface
SPY
(4 bits)
SCK
AN
AN
1
2
R2
R2
R2
R2
0
1
2
3
A/D
converter
AN
3
ALU
CA
V
ref
ST
Data bus
(1 bit)
(1 bit)
R3
R3
R3
1
2
3
A
Large-current
pin
(4 bits)
B
(4 bits)
Intermediate-
voltage
NMOS open
drain pins
SP
(10 bits)
Instruction
decoder
PC
(14 bits)
Standard-
voltage
NMOS open
drain pins
ROM
(1,024 × 10 bits)
(2,048 × 10 bits)
(4,096 × 10 bits)
Bidirectional
signal line
13
HD404344R Series/HD404394 Series
Memory Map
ROM Memory Map
The ROM memory map for the MCU is shown in figure 1 and explained as follows.
0
$0000
0
1
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
JMPL instruction
(jump to RESET, STOPC routine)
Vector address
2
JMPL instruction
(jump to INT0 routine)
15
16
$000F
$0010
3
4
Zero-page subroutine
(64 words)
5
Not used
6
63
64
$003F
$0040
7
HD404341R, HD40C4341R, HD404391
program/pattern
8
JMPL instruction
(jump to timer B routine)
9
(1,024 words)
1023
1024
10
11
12
13
14
15
$03FF
$0400
JMPL instruction
(jump to timer C routine)
HD404342R, HD40C4342R, HD404392
program/pattern
JMPL instruction
(jump to A/D converter routine)
(2,048 words)
$07FF
$0800
2047
2048
HD404344R, HD40C4344R, HCD404344R,
HCD40C4344R,HD404394, HD4074344, HD4074394
program/pattern
JMPL instruction
(jump to serial routine)
(4,096 words)
4095
4096
$0FFF
$1000
Not used
16383
$3FFF
Figure 1 ROM Memory Map
14
HD404344R Series/HD404394 Series
Vector Address Area ($0000 to $000F): When an MCU reset or an interrupt process is executed, the
program will begin executing from a vector address. The JMPL instructions which branch to the reset
routine and interrupt routine should be programmed at these top addresses.
Zero-Page Subroutine Area ($0000–$003F): This area is reserved for subroutines. The program branches
to a subroutine in this area in response to a CAL instruction.
Pattern Area:
HD404341R, HD40C4341R, HD404391—$0000 to $03FF
HD404342R, HD40C4342R, HD404392—$0000 to $07FF
HD404344R, HD40C4344R, HCD404344R, HCD40C4344R, HD404394, HD4074344, HD4074394—
$0000 to $0FFF
This area contains ROM data which can be referenced with the P instruction.
Program Area:
HD404341R, HD40C4341R, HD404391—$0000 to $03FF
HD404342R, HD40C4342R, HD404392—$0000 to $07FF
HD404344R, HD40C4344R, HCD404344R, HCD40C4344R, HD404394, HD4074344, HD4074394—
$0000 to $0FFF
15
HD404344R Series/HD404394 Series
RAM Memory Map
The MCU RAM contains 256 digits × 4 bits which is used for the memory registers, and the data and stack
areas. The interrupt control bits area, special register area, and the register flag area are mapped into the
RAM memory. The RAM memory area is shown in figure 2 and explained as follows.
$000
$000
$003
$004
$005
Interrupt control bits area
RAM-mapped registers
Memory registers (MR)
Port mode register A
Serial mode register
(PMRA)
(SMR)
W
$040
$050
W
$006
Serial data register lower (SRL)
R/W
R/W
$007 Serial data register upper (SRU)
Data (176 digits)
$008
$009
$00A
$00B
Not used
Timer mode register B1 (TMB1)
W
R/W
R/W
*
$100
Timer B
(TRBL/TWBL)
(TRBU/TWBU)
$00C Miscellaneous register
(MIS)
W
$00D
W
Timer mode register C
(TMC)
$00E
$00F
R/W
R/W
Not used
Timer C
(TRCL/TWCL)
(TRCU/TWCU)
Not used
$3C0
$3FF
Stack (64 digits)
A/D channel register
(ACR)
$016
$017
$018
W
R
A/D data register lower (ADRL)
A/D data register upper (ADRU)
R
$019 A/D mode register 1
(AMR1)
(AMR2)
W
W
$01A
A/D mode register 2
Not used
$020
$023
$024
$025
Register flag area
Port mode register B
Port mode register C
(PMRB)
(PMRC)
(TMB2)
W
W
W
$026 Timer mode register B2
Not used
Port D0–D3 DCR
$02D Port D4, D5 DCR
Not used
$02C
(DCD0)
(DCD1)
W
W
Note: * Two registers are mapped
on the same area ($00A,
$00B, $00E, $00F).
$030
$031
$032
$033
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
(DCR0)
(DCR1)
(DCR2)
(DCR3)
W
W
W
W
R: Read only
W: Write only
R/W: Read/write
Not used
$03F
Timer read register B lower (TRBL)
Timer read register B upper (TRBU)
Timer write register B lower (TWBL)
Timer write register B upper (TWBU)
$00A
R
R
W
W
$00B
Timer read register C lower (TRCL)
Timer read register C upper (TRCU)
R
R
$00E
$00F
Timer write register C lower (TWCL)
Timer write register C upper (TWCU)
W
W
Figure 2 RAM Memory Map
16
HD404344R Series/HD404394 Series
RAM Map Register Area ($000 to $03F):
•
Interrupt control bits area: $000 to $003
This area is made up of bits used for interrupt control as shown in figure 3. Each bit can be accessed
only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). Some bits
however, have limitations along with certain instructions as shown in figure 4.
•
Special register area: $004 to $01F, $024 to $03F
This area is made up of mode registers and data registers, such as for external interrupt, serial interface,
timers, A/D converter, and data control for the I/O ports. Its configurations are shown in figures 2 and 5.
These registers are categorized as write-only, read-only, and write/read. They can not be accessed by
RAM bit manipulation instructions.
•
Register flag area: $020 to $023
This area is used for the WDON flag and other interrupt control flags. Its configuration is shown in
figure 3. Each bit can be accessed only by the SEM/SEMD, REM/REMD, and TM/TMD instructions.
Some bits however, have limitations along with certain instructions as shown in figure 4.
Data Area ($040 to $0FF): Sixteen of the 176 digits in this area, from $040 to $04F, are memory registers.
These registers can be accessed by the LAMR and XMRA instructions. Its configuration is shown in figure
6.
Stack Area ($3C0 to $3FF): This area is used to hold the program counter (PC), the status flag (ST), and
the carry flag (CA) for subroutine calls (CAL and CALL instructions) and interrupts. Since four digits are
used for each level, this area can be used for stacking up to 16 subroutines. The stacking order of saved
data and the storing of bits are shown in figure 6. The program counter is recovered by the RTN and RTNI
instructions. The status and carry flags are recovered only by the RTNI instruction.
Any area not used in the stack area is available for data storage.
17
HD404344R Series/HD404394 Series
RAM Address
$0000
Bit 3
Bit 2
Bit 1
Bit 0
IE
IM0
(IM of INT0)
IF0
(IF of INT0)
RSP
(Reset SP bit)
(Interrupt
enable flag)
$0001
$0002
$0003
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
IMS
(IM of serial)
IFS
(IF of serial)
IMAD
(IM of A/D)
IFAD
(IF of A/D)
Interrupt control bits area
Bit 3
Bit 2
Bit 1
Bit 0
WDON
(Watchdog
on flag)
ADSF
(A/D start flag)
$020
: Not used
RAME
(RAM enable
flag)
IAOF
(IAD off flag)
$021
$022
$023
IF: Interrupt
request flag
IE: Interrupt
mask
IM: Interrupt
enable flag
SP: Stack pointer
Register flag area
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
SEM/SEMD
REM/REMD
TM/TMD
IE
IM
Can be used
Can be used
Can be used
IAOF
IF
Not processed
Can be used
Can be used
RAME
RSP
WDON
ADSF
Not used
Not processed
Can be used
Can be used
Not processed
Can be used
Not processed
Inhibited to access
Not processed
Inhibited to access
Inhibited to access
Can be used
Inhibited to access
• The WDON bit can be reset by an MCU reset or by stop mode release with STOPC.
• Do not use REM/REMD for the ADSF bit during A/D conversion.
• If the TM or TMD instruction is excuted for the inhibited or non-existing bits, the value in
ST becomes invaild.
Figure 4 Limitations for RAM Bit Manipulation Instructions
18
HD404344R Series/HD404394 Series
Bit 2
IF0
Bit 1
RSP
Bit 0
IE
Register name
Bit 3
IM0
$000
$001
$002
$003
IFTC
IFS
IMTB
IMAD
IFTB
IFAD
IMTC
IMS
PMRA $004
SMR $005
SRL $006
SRU $007
$008
R03/TOC
R01/SI
Serial data transfer speed
R02/SO
R00/SCK
Serial data register (lower)
Serial data register (upper)
Timer B clock source
TMB1 $009
TRBL/TWBL $00A
TRBU/TWBU $00B
MIS $00C
TMC $00D
TRCL/TWCL $00E
TRCU/TWCU $00F
$010
Reload control
Timer B register (lower)
Timer B register (upper)
Pull-up control
Reload control
SO PMOS control
Timer C clock source
Timer C register (lower)
Timer C register (upper)
$011
$012
$013
$014
$015
A/D channel selection
A/D data register (lower)
A/D data register (upper)
ACR $016
ADRL $017
ADRU $018
AMR1 $019
AMR2 $01A
$01B
R33
/AN3
R32/AN2
R31/AN1
R30/AN0*
A/D conversion speed
$01C
$01D
$01E
$01F
$020
$021
ADSF
IAOF
WDON
RAME
$022
$023
D4/STOPC
D0/INT0/EVNB
Transmit clock
EVNB edge detection
PMRB $024
PMRC $025
TMB2 $026
$027
SO idle level
$028
$029
$02A
$02B
D3 DCR
D2 DCR
D1 DCR
D5 DCR
D0 DCR
D4 DCR
DCD0 $02C
DCD1 $02D
$02E
$02F
R00 DCR
R10 DCR
R20 DCR
R30 DCR*
R03 DCR
R13 DCR
R23 DCR
R33 DCR
R02 DCR
R12 DCR
R22 DCR
R32 DCR
R01 DCR
R11 DCR
R21 DCR
R31 DCR
DCR0 $030
DCR1 $031
DCR2 $032
DCR3 $033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
: Not used
Note: * Applies to the HD404344R series and HD4074344. Does not apply to the HD404394 series.
Figure 5 Special Register Area
19
HD404344R Series/HD404394 Series
Memory registers
$040 MR(0)
MR(1)
$041
Stack area
$3C0
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
MR(2)
$042
MR(3)
$043
MR(4)
$044
MR(5)
MR(6)
MR(7)
MR(8)
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F
Bit 3
ST
Bit 2
Bit 1
Bit 0
$3FC
$3FD
$3FE
$3FF
PC13
PC12
PC11
MR(9)
MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)
PC10
CA
PC9
PC6
PC2
PC8
PC5
PC1
PC7
PC4
PC0
PC3
$3FF
PC13–PC0 : Program counter
ST: Status flag
CA: Carry flag
Note: Since HD404344R series, HD4074344 and HD404394 series have a 4-kword ROM, PC12 and
PC13 are ignored.
Figure 6 Configuration of Memory Registers, Stack Area, and Stack Position
20
HD404344R Series/HD404394 Series
Functional Description
Registers and Flags
The CPU has nine registers and two flags. Their configurations are shown in figure 7 and explained as
follows.
3
3
0
0
0
(A)
(B)
Accumulator
Initial value: Undefined, R/W
B register
W register
Initial value: Undefined, R/W
Initial value: Undefined, R/W
1
(W)
3
3
3
3
0
0
0
0
X register
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
(X)
(Y)
Y register
SPX register
(SPX)
(SPY)
SPY register
Carry
0
(CA)
0
Status
Initial value: 1, no R/W
13
(ST)
0
0
Program counter
Initial value: 0,
no R/W
(PC)
1
9
1
5
Stack pointer
Initial value: $3FF, no R/W
1
1
(SP)
Figure 7 Registers and Flags
21
HD404344R Series/HD404394 Series
Accumulator (A), B Register (B): The accumulator and B register are 4-bit registers used for storing ALU
operation results and data that is transferred between memory and I/O ports or between other registers.
W Register (W), X Register (X), Y Register (Y): The W register is a 2-bit register and the X and Y
registers are 4-bit registers.
These are used for indirect addressing to RAM. The Y register is also used for addressing the D port.
SPX Register (SPX), SPY Register (SPY): The SPX and SPY registers are 4-bit registers that supplement
the X and Y registers, respectively.
Carry Flag (CA): The carry flag latches the ALU overflow during an arithmetic instruction execution. It is
controlled by the SEC, REC, ROTL, and ROTR instructions. The carry flag is stored during interrupt
processing, then recovered from the stack by a RTNI instruction. (It is not affected by the RTN instruction.)
Status Flag (ST): The status flag latches the overflow of ALU arithmetic instructions and compara tive
instructions, and also the results of ALU non-zero and bit test instructions. It is then used for branch
conditions of the BR, BRL, CAL, and CALL instructions. The status flag remains unchanged until the next
arithmetic instruction, comparative instruction, or bit test is executed. After a BR, BRL, CAL, or CALL
instruction is executed, the status flag will be set to 1 regardless if the instruction is executed or skipped.
The contents of the status flag is stored on the stack during interrupt processing, then recovered from the
stack by a RTNI instruction.
Program Counter (PC): This 14-bit binary counter maintains ROM address information.
Stack Pointer (SP): The stack pointer is a 10-bit register which contains the address of the next stack
space to be used. It is initialized as $3FF by an MCU reset. When data is stored onto the stack, the SP is
decremented by 4, and when data is pulled from the stack, it is incremented by 4. The top four bits of the
stack pointer are fixed at 1111, so it can be used for a maximum of 16 levels. There are two ways of
initializing the stack pointer to $3FF. One is by MCU reset and the other is by resetting the RSP bit with a
REM or a REMD instruction.
Reset
An MCU reset is executed by setting RESET low. The RESET input must be more than tRC so as to keep
the oscillator steady during power on or when stop mode is cancelled. For other cases, the MCU can be
reset by a RESET input for a minimum of two instruction cycle times.
Initialized values by MCU reset are listed in table 1.
Certain bits in the interrupt control bits area and the register flag area can be set or reset by the SEM/SEMD or
REM/REMD instructions. Also these can be tested by the TM/TMD instruction. The following specifies the limitations
for each bit.
22
HD404344R Series/HD404394 Series
Table 1
Initial Values After MCU Reset
Item
Abbr.
Initial Value
Contents
Program counter
(PC)
$0000
Indicates program execution
point from start address of ROM
area
Status flag
(ST)
(SP)
(IE)
1
Enables conditional branching
Stack level 0
Stack pointer
$3FF
0
Interrupt
flags/mask
Interrupt enable flag
Interrupt request flag
Interrupt mask
Inhibits all interrupts
(IF)
0
Indicates there is no interrupt
request
(IM)
1
Prevents (masks) interrupt
requests
I/O
Port data register
(PDR)
All bits 1
Enables output at level 1
Data control register
(DCD0, DCD1) All bits 0
Turns output buffer off (to high
impedance)
(DCR0,- DCR3) All bits 0
Port mode register A
Port mode register B
Port mode register C
(PMRA)
(PMRB)
(PMRC)
- 000
0 - - 0
- - - 0
0000
Refer to description of port mode
register A
Refer to description of port mode
register B
Refer to description of port mode
register C
Timer/
counters, serial
interface
Timer mode register B1 (TMB1)
Refer to description of timer
mode register B1
Timer mode register B2 (TMB2)
Timer mode register C (TMC)
- - 00
0000
0000
Refer to description of timer
mode register B2
Refer to description of timer
mode register C
Serial mode register
(SMR)
Refer to description of serial
mode register
Prescaler S
(PSS)
(TCB)
(TCC)
$000
$00
—
—
—
—
—
—
Timer counter B
Timer counter C
Timer write register B
Timer write register C
Octal counter
$00
(TWBU, TWBL) $X0
(TWCU, TWCL) $X0
000
23
HD404344R Series/HD404394 Series
Table 1
Initial Values After MCU Reset (cont)
Item
Abbr.
Initial Value
Contents
A/D
A/D mode register 1
A/D mode register 2
(AMR1)
0000
Refer to description of A/D mode
register
(AMR2)
- - - 0
Refer to description of A/D mode
register
Bit register
Watchdog timer on flag (WDON)
0
0
Refer to description of timer C
A/D start flag
(ADSF)
Refer to description of A/D
converter
IAD off flag
(IAOF)
0
Refer to description of A/D
converter
Others
Miscellaneous register (MIS)
00 - -
Refer to description of I/O, and
serial interface
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.
2. X indicates invalid value. – indicates that the bit does not exist.
Table 1
Initial Values After MCU Reset (cont)
After Stop Mode
Release by STOPC
Input
After Stop Mode
Release by RESET of MCU Reset
Input
After Other Types
Carry
(CA)
Program needs to initialize these registers.
Program needs to
initialize these
registers.
Accumulator
B register
(A)
(B)
W register
(W)
X/SPX register
Y/SPY register
Serial data register
A/D data register
RAM
(X/SPX)
(Y/SPY)
(SRU, SRL)
(ADRU, ADRL)
Data before entering stop mode are kept.
RAM enable flag
(RAME)
1
0
0
0
0
Port mode register B (PMRB3)
bit 3
Data before entering
stop mode are kept.
24
HD404344R Series/HD404394 Series
Interrupts
There are five kinds of interrupts: external INT0, timer B, timer C, serial interface, and A/D converter.
An interrupt request flag or an interrupt mask and vector address are used for each type of interrupt. They
are used for storing interrupt requests and interrupt controls. An interrupt enable flag is also used for total
interrupt control.
Interrupt Control Bits and Interrupt Processing: The interrupt control bits are mapped from $000 to
$003 of RAM and can be accessed by RAM bit manipulation instructions. However, the interrupt request
flag (IF) cannot be set by software. An MCU reset initializes the interrupt enable flag (IE) and the interrupt
request flag (IF) to 0, and the interrupt mask (IM) to 1.
A block diagram of the interrupt control circuit is shown in figure 8. The interrupt priority order and vector
addresses are listed in a table in the figure, along with the conditions for executing the interrupt processing
of the five types of interrupt requests (table 2). An interrupt request occurs when the interrupt request flag
is set to 1 and the interrupt mask to 0. If the interrupt enable flag is 1, interrupt processing has occurred.
The vector address which corresponds to the interrupt source is generated from the priority PLA.
The interrupt processing sequence is shown in figure 9 and the interrupt processing flowchart is shown in
figure 10. After receiving an interrupt, the previous instruction is completed in the first cycle. The interrupt
enable flag (IE) is reset after two cycles. The contents of the carry flag, status flag, and program counter are
stored onto the stack at the second and third cycles. Instruction execution is restarted by jumping to the
vector address during the third cycle. The JMPL instructions, which branch to the start addresses of the
interrupt routines, should be programmed at each vector address area. The interrupt request which initiated
the interrupt processing should be reset by software instructions in the interrupt routine.
25
HD404344R Series/HD404394 Series
$000,0
IE
Interrupt
request
*
(RESET, STOPC )
Priority Controller
$000,2
Priority Order
Vector Address
$0000
INT interrupt
IF0
$000,3
IM0
0
1
2
3
4
5
$0002
$0008
$000A
$000C
$002,0
IFTB
$000E
Timer B interrupt
Timer C interrupt
A/D interrupt
$002,1
IMTB
$002,2
IFTC
$002,3
IMTC
$003,0
IFAD
$003,1
IMAD
$003,2
IFS
Serial interrupt
$003,3
IMS
Note: * STOPC interrupt request is enabled only when the MCU is in stop mode.
Figure 8 Interrupt Control Circuit, Vector Addresses, and Interrupt Priorities
26
HD404344R Series/HD404394 Series
Table 2
Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt Control Bit
IE
INT0
Timer B
Timer C
A/D
1
Serial
1
1
*
*
*
*
1
0
1
*
*
*
1
0
0
1
*
*
1
0
0
0
0
1
IF0 · IM0
0
IFTB · IMTB
IFTC · IMTC
IFAD · IMAD
IFS · IMS
0
0
1
*
Note: * Can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Stacking;
Vector address
generation
Interrupt
acceptance
Stacking;
IE reset
Execution of JMPL
instruction at vector address
Execution of
instruction at
start address
of interrupt
routine
Note:
* The stack is accessed and the interrupt enable flag is reset after the instruction is executed, even
if it is a two-cycle instruction.
Figure 9 Interrupt Processing Sequence
27
HD404344R Series/HD404394 Series
Power on
No
RESET = 0?
Yes
Yes
Interrupt
request?
No
No
IE = 1?
Yes
Accept interrupt
Execute instruction
Reset MCU
←
←
←
←
IE
Stack
Stack
Stack
0
(PC)
(CA)
(ST)
PC ← (PC) + 1
Yes
Yes
INT0
PC ← $0002
PC ← $0008
interrupt?
No
Timer B
interrupt?
No
Yes
Yes
Timer C
interrupt?
PC ← $000A
PC ← $000C
No
A/D
interrupt?
No
PC ← $000E
(serial interrupt)
Figure 10 Interrupt Processing Flowchart
28
HD404344R Series/HD404394 Series
Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag executes interrupt enable/disable for all
interrupt requests as listed in table 3. It is reset by interrupt processing and set by the RTNI instruction.
Table 3
Interrupt Enable Flag (IE: $000, Bit 0)
IE
0
Interrupt Enabled/Disabled
Disabled
1
Enabled
External Interrupt (INT0): INT0 input should be selected by using port mode register B (PMRB: $024), so
that the external interrupt request flag (IF0) is set at the falling edge of the INT0 input.
External Interrupt Request Flag (IF0: $000, Bit 2): The external interrupt request flag is set by the INT0
input edge, as listed in table 4.
Table 4
External Interrupt Request Flag (IF0: $000, Bit 2)
IF0
0
Interrupt Request
No
1
Yes
External Interrupt Mask (IM0: $000, Bit 3): IM0 is a bit which masks the interrupt request caused by an
external interrupt request flag, as listed in table 5.
Table 5
External Interrupt Mask (IM0: $000, Bit 3)
IM0
0
Interrupt Request
Enabled
1
Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag is set by the
overflow output of timer B, as listed in table 6.
Table 6
Timer B Interrupt Request Flag (IFTB: $002, Bit 0)
IFTB
Interrupt Request
0
1
No
Yes
29
HD404344R Series/HD404394 Series
Timer B Interrupt Mask (IMTB: $002, Bit 1): IMTB is a bit which masks the interrupt request caused by
the timer B interrupt request flag, as listed in table 7.
Table 7
Timer B Interrupt Mask (IMTB: $002, Bit 1)
IMTB
Interrupt Request
Enabled
0
1
Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): The timer C interrupt request flag is set by the
overflow output of timer C, as listed in table 8.
Table 8
Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
IFTC
Interrupt Request
0
1
No
Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): IMTC is a bit which masks the interrupt request caused
by the timer C interrupt request flag, as listed in table 9.
Table 9
Timer C Interrupt Mask (IMTC: $002, Bit 3)
IMTC
Interrupt Request
Enabled
0
1
Disabled (masked)
Serial Interrupt Request Flag (IFS: $003, Bit 2): A serial interrupt request flag is set when the serial data
transfer is completed or when the data transfer is suspended, as listed in table 10.
Table 10
Serial Interrupt Request Flag (IFS: $003 Bit 2)
IFS
0
Interrupt Request
No
1
Yes
30
HD404344R Series/HD404394 Series
Serial Interrupt Mask (IMS1: $003, Bit 3): IMS1 is a bit which masks the interrupt request caused by the
serial interrupt request flag, as listed in table 11.
Table 11
Serial Interrupt Mask (IMS: $003, Bit 3)
IMS
0
Interrupt Request
Enabled
1
Disabled (masked)
A/D Interrupt Request Flag (IFAD: $003, Bit 0): The A/D interrupt request flag is set after the A/D
conversion is completed, as listed in table 12.
Table 12
A/D Interrupt Request Flag (IFAD: $003, Bit 0)
IFAD
Interrupt Request
0
1
No
Yes
A/D Interrupt Mask (IMAD: $003, Bit 1): IMAD is a bit which masks the interrupt request caused by the
A/D interrupt request flag, as listed in table 13.
Table 13
A/D Interrupt Mask (IMAD: $003, Bit 1)
IMAD
Interrupt Request
Enabled
0
1
Disabled (masked)
31
HD404344R Series/HD404394 Series
Operating Modes
The MCU has three operating modes as shown in table 14. The transitions between the operating modes are
shown in figure 11.
Table 14
Operations in Each Operating Mode
Function
Active Mode
Standby Mode
OP
Stop Mode
Stopped
Reset
System oscillator
OP
OP
OP
OP
OP
OP
OP
CPU
Retained
Retained
OP
RAM
Retained
Reset
Timers B, C
Serial
A/D
OP
Reset
OP
Reset
I/O
Retained*
Reset
Notes: OP implies in operation.
* Since input/output circuits are in operation, the current will flow in/out depending on the pin status
in standby mode. Note that this current is in addition to the standby mode dissipation current.
Active
mode
SBY
instruction
STOP
instruction
Interrupt
request
Standby
mode
Stop
mode
RESET = 0
RESET = 1
RESET = 0
RESET = 0
MCU
reset
Figure 11 MCU Status Transition
32
HD404344R Series/HD404394 Series
Active Mode: All functions operate in active mode. In active mode, the MCU is controlled by the
oscillating circuit of OSC1 and OSC2.
Standby Mode: The MCU switches to standby mode when an SBY instruction is executed.
In standby mode, the oscillator continues operating, but the clocks related to instruction execution stops
running. This causes the CPU to stop operating. However, the contents of RAM are retained. Also, the D
and R ports, which are set as output, maintain their status before entering standby mode. The peripheral
functions, such as interrupt, timers, serial interface, and A/D converter, continue operating.
Power dissipation in standby mode is less than in active mode because of the CPU not operating.
The MCU enters standby mode when the SBY instruction is executed in active mode.
To terminate standby mode, provide a RESET input or an interrupt request. If a reset input is given, the
MCU will be reset. If an interrupt request is given, the MCU will change to active mode and the next
instruction will be executed. After the instruction execution, if the interrupt enable flag is 1, the interrupt
operation is executed. If the interrupt enable flag is 0, normal instruction execution continues and the
interrupt request is left pending.
The standby mode flowchart is shown in figure 13.
Stop Mode: The MCU enters stop mode when a STOP instruction is received.
In stop mode, all MCU functions stop, except for maintaining RAM data. Power dissipation in this mode is
therefore the lowest of all operating modes.
In stop mode, the OSC1 and OSC2 oscillator is stopped.
To terminate stop mode provide either a RESET or STOPC input as shown in figure 12.
When terminating stop mode, it is important to ensure a proper oscillation stabilization period of at least tRC
for the RESET or STOPC input. (Refer to the AC characteristics tables.)
After clearing stop mode, the RAM maintains its data kept before entering stop mode. However, the
contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and the
serial data register are not maintained.
Clearing Stop Mode Using STOPC: The MCU is transition from stop mode to active mode by either a
RESET or STOPC input. The MCU starts instruction execution from the start of the program at address 0.
Then the RAM enable flag (RAME: $021, 3) is set accordingly, RAME = 0 for RESET input and RAME =
1 for STOPC input. A RESET input is effective when the MCU is in any mode. A STOPC input however,
is effective only in stop mode and is ignored in other modes.
So, when clearing stop mode with a STOPC input the program needs to identify the RAME status. (For
example, when the RAM contents before entering stop mode is used after transition to active mode.) A
TEST instruction for the RAM enable flag (RAME) should be executed at the beginning of the program.
33
HD404344R Series/HD404394 Series
Table 15
Operating Modes and Transition Conditions
Mode
Conditions to Enter Mode
Conditions to Exit Mode
Active mode
•
•
•
RESET release
•
•
RESET input
STOP/SBY instruction
Interrupt request
STOPC release in stop mode
Standby mode
Stop mode
•
SBY instruction
•
•
RESET input
Interrupt request
•
STOP instruction
•
•
RESET input
STOPC input in stop mode
Stop mode
Oscillator
Internal
clock
RESET
or
STOPC
tres
res ≥ tRC (stabilization period)
t
STOP instruction execution
Figure 12 Timing of Stop Mode Cancellation
34
HD404344R Series/HD404394 Series
Standby
Stop
Oscillator: Stop
Oscillator: Active
Peripheral clocks: Stop
All other clocks: Stop
Peripheral clocks: Active
All other clocks: Stop
No
No
RESET = 0?
RESET = 0?
Yes
Yes
No
IF0 • IM0 = 1?
No
STOPC = 0?
Yes
No
IFTB • IMTB =
1?
Yes
Yes
No
IFTC • IMTC =
1?
Yes
No
IFAD • IMAD =
1?
RAME = 1
RAME = 0
Yes
No
IFS • IMS =
1?
Yes
Restart
processor clocks
Restart
processor clocks
Execute
next instruction
IF = 1,
IM = 0, and
IE = 1?
No
Yes
Execute
next instruction
Interrupt accept
Reset MCU
Figure 13 MCU Process Flowchart
35
HD404344R Series/HD404394 Series
MCU Operation Sequence: The MCU operates according to the flowcharts shown in figures 14 to 16.
Since RESET is asynchronous input, the MCU will be reset in any mode that the MCU is operating in.
The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.
Power on
No
RESET = 0?
Yes
MCU
operation
cycle
RAME = 0
Reset MCU
Figure 14 MCU Operation Sequence (Power On)
36
HD404344R Series/HD404394 Series
MCU operation
cycle
Yes
IF = 1?
No
No
IM = 0 and
IE = 1?
Yes
Instruction
execution
←
IE
Stack
0
←
Yes
(PC),
(CA),
(ST)
SBY/STOP
instruction?
No
Low-power mode
operation cycle
←
←
location
PC Next
PC Vector
address
IF: Interrupt request flag
IM: Interrupt mask
IE: Interrupt enable flag
PC: Program counter
CA: Carry flag
ST: Status flag
Figure 15 MCU Operation Sequence (MCU Operation Cycle)
37
HD404344R Series/HD404394 Series
Low-power mode
operation cycle
No
IF = 1 and
IM = 0?
Yes
Standby mode
(SBY)
Stop mode
*
No
No
IF = 1 and
IM = 0?
STOPC = 0?
Yes
Yes
Hardware NOP
execution
Hardware NOP
execution
RAME = 1
←
Iocation
←
Iocation
PC Next
PC Next
Reset MCU
Instruction
execution
MCU operation
cycle
Note: * For IF and IM operation, refer to figure 13.
Figure 16 MCU Operation Sequence (Low Power Mode Operation)
38
HD404344R Series/HD404394 Series
Oscillator Circuit
Figure 17 shows a block diagram of the clock generation circuit. Ceramic oscillator can be connected to
OSC1 and OSC2 as listed in table 16. An external clock can also be connected. In addition, the system
oscillator of the HD404344R Series is capable of CR oscillation.
CPU with ROM,
RAM, registers,
flags, and I/O
fOSC
fcyc
tcyc
1/4
division
circuit
øCPU
System
clock
generation
Timing
generator
circuit
OSC2
OSC1
System
oscillator
Peripheral
function
øPER
interrupt
Figure 17 Clock Generation Circuit
R23
OSC1
OSC2
GND
: GND
Figure 18 Typical Layout of Ceramic Oscillator
39
HD404344R Series/HD404394 Series
Table 16
Oscillator Circuit Examples
Circuit Configuration
Circuit Constants
External clock operation
External
oscillator
OSC1
OSC2
Open
C1
Ceramic oscillator
(OSC1, OSC2)
Ceramic oscillator : CSA4.00MG (Murata)
Rf = 1 MΩ ±20%
OSC1
OSC2
C1 = C2 = 30 pF ±20%
Ceramic
oscillator
Rf
Ceramic oscillator: KBR-4.0MSA (Kyocera)
Rf = 1 MΩ ±20%
C2
C1 = C2 = 33 pF ±20%
GND
CR oscillation
Rf = 20 kΩ ±1%
OSC1
OSC2
(OSC1, OSC2)
HD404344R series
Rf
Notes: 1. Since the circuit constants change depending on the ceramic oscillator and stray capacitance of
the board, the user should consult with the ceramic oscillator manufacturer to determine the
circuit parameters.
2. Wiring among OSC1, OSC2, and elements should be as short as possible, and must not cross
other wiring (see figure 18).
40
HD404344R Series/HD404394 Series
Input/Output
The HD404344R series and HD4074344 MCU has 22 input/output pins (D0–D5, R00–R33) and the
HD404394 MCU has 21 input/output pins (D0–D5, R00–R23, R31–R33). These input/output pins have the
following features:
•
All 22 pins for the HD404344R series and HD4074344 have a CMOS output circuit. Ten pins D1, D2,
and R10–R23 are large current input/output pins.
•
Three input/output pins of the 21 pins on the HD404394 series, R10–R12, have intermediate-voltage
NMOS open drain output circuits. Five other input/output pins, R13 and R20–R23, have standard-voltage
NMOS open drain output circuits. The remaining 13 input/output pins, D0–D5, R00–R03 and R31–R33,
have CMOS output circuits.
Ten pins D1, D2, and R10–R23 are high-current input/output pins.
•
Some input/output pins are multiplexed with peripheral functions, such as for the timers and serial
interface. For these pins, the settings for peripheral functions are done prior to the D or R ports settings.
If these pins are set as peripheral functions, the pin functions and input/output selections automatically
switch according to the settings.
•
•
Program control of input/output port selection, as well as peripheral function selection.
All peripheral function output pins are CMOS output pins. However, the R02/SO pin can be
programmed to be NMOS open drain output.
•
•
In stop mode, all peripheral function selections are cleared because of the MCU being reset. Also, the
input/output pins go into a high-impedance state.
All input/output pins for both the HD404344R series, HD4074344 and the HD404394 series except for
pins R10–R23, have built-in pull-up MOS. Therefore they can be individually turned on or off by
software.
•
When pin functions are set as peripheral functions after selecting the pins as pull-up MOS, the pins are
maintained as pull-up MOS from the time of selection. Also, pull-up MOS can be selected by software
after setting the pin functions as peripheral functions. The control of the input/output pins are shown in
table 17 and the circuit configuration of each input/output pin is shown in table 18.
Table 17
Programmable Control of Standard I/O Pins
MIS3 (bit 3 of MIS)
DCD, DCR
PDR
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CMOS buffer
PMOS
NMOS
—
—
—
—
—
—
—
On
—
On
—
—
—
—
—
—
—
On
—
On
—
On
—
On
Pull-up MOS
Note: — indicates off.
41
HD404344R Series/HD404394 Series
Table 18
Circuit Configurations of I/O Pins
Pins
HD404344R HD404394
Series,
Series
I/O Pin Type
Circuit
HD4074344
Input/output
pins
D0–D5,
R00, R01
R03,
D0–D5,
R00, R01
R03,
HLT
MIS3
VCC
Pull-up control signal
Buffer control signal
VCC
DCD, DCR
PDR
R10–R33
R31–R33
Output data
Input data
Input control signal
VCC
VCC
None
R13,
HLT
Buffer control signal
R20–R23
DCR
(standard
voltage pins)
Output data
PDR
Input data
Input control signal
R02
R02
HLT
MIS3
VCC
Pull-up control signal
Buffer control signal
VCC
DCR
MIS2
PDR
Output data
Input data
Input control signal
None
R10–R12
HLT
(middle
voltage pins)
DCR
PDR
Input data
Input control signal
42
HD404344R Series/HD404394 Series
Table 18
Circuit Configurations of I/O Pins (cont)
Pins
HD404344R HD404394
Series,
Series
I/O Pin Type
Circuit
HD4074344
HLT
MIS3
Peripheral
function pins output
pins
Input/
SCK
SCK
VCC
Pull-up control signal
VCC
Output data
SCK
Input data
SCK
HLT
MIS3
Output
pins
SO
SO
VCC
Pull-up control signal
VCC
PMOS control signal
Output data
MIS2
SO
HLT
MIS3
TOC
TOC
VCC
Pull-up control signal
VCC
Output data
TOC
HLT
MIS3
PDR
Input
pins
SI, INT0,
EVNB,
SI, INT0,
EVNB,
VCC
STOPC
STOPC
Input data
SI, INT0,
EVNB, STOPC
HLT
MIS3
PDR
AN0–AN3
AN1–AN3
VCC
A/D input
Input control
Note: In stop mode, the MCU is reset and the peripheral function selection is cancelled. Also, the HLT
signal goes low, and input/output pins enter a high-impedance state.
43
HD404344R Series/HD404394 Series
D Port
The D port consists of six input/output pins each addressed by one bit.
The D ports can be set and reset by SED/RED and SEDD/REDD instructions. Output data is stored in the
port data register (PDR) for each pin. Also, all D ports can tested by the TD/TDD instructions.
The on/off status of the output buffers is controlled by the D-port data control registers (DCD0, DCD1:
$02C and $02D), which are mapped to memory addresses (figure 19).
Pins D0 and D4 are multiplexed with peripheral function pins INT0/EVNB, and STOPC. Setting of the
peripheral functions for these pins is executed by bits 3 and 0 (PMRB3, PMRB0) of port mode register B
(PMRB: $024) (figure 20).
Data control register
DCD0, DCD1
(DCD0, DCD1: $02C, $02D)
DCR0 to DCR3
(DCR0 to DCR3: $030 to $033)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
Bits 0 to 3 CMOS Buffer Control
W
W
W
W
0
CMOS buffer off
(high impedance)
DCD03 DCD02 DCD01 DCD00
to to
DCD11 DCD10
1
CMOS buffer on
DCR03 DCR02 DCR01 DCR00
to
to
to
to
DCR33 DCR32 DCR31 DCR30
Correspondence between ports and DCR bits
Register
DCD0
DCD1
DCR0
DCR1
DCR2
DCR3
Bit 3
D3
Bit 2
D2
Bit 1
D1
Bit 0
D0
—
—
D5
D4
R03
R13
R23
R33
R02
R12
R22
R32
R01
R11
R21
R31
R00
R10
R20
R30*
Note: * Available for the HD404344R series and HD4074344, but not available for the HD404394 series.
Figure 19 Data Control Register (DCR)
44
HD404344R Series/HD404394 Series
Port mode register B (PMRB: $024)
Bit
3
0
2
1
0
0
Initial value
Read/Write
Bit name
—
—
—
—
W
W
PMRB3 Not used Not used PMRB0
PMRB3 D4/STOPC Mode Selection
PMRB0
D0/INT0 /EVNB Mode Selection
0
1
D4
0
1
D0
STOPC
INT0 /EVNB
Figure 20 Port Mode Register B (PMRB)
45
HD404344R Series/HD404394 Series
R Port
The R port consists of input/output pins each addressed by 4 bits. Input/output is controlled by the LAR and
LBR instructions and the LRA and LRB instructions. The output data is stored in the port data register
(PDR) of each pin. The on/off status of the output buffers is controlled by the R-port data control registers
(DCR0–DCR3: $030–$033), which are mapped to memory addresses (figure 19).
The R10–R12 ports of the HD404394 series are n-channel middle-voltage open drain input/output pins.
The R00–R03 pins are also used as peripheral function pins: SCK, SI, SO, and TOC. Setting of the
peripheral functions for these pins is executed by bit 3 (SMR3) of the serial mode register (SMR:$005) and
by bits 2 to 0 (PMRA2–PMRA0) of port mode register A (PMRA: $004), as shown in figures 21 and 22.
The R30–R33 pins of the HD404344R series and HD4074344 are also used as AN0–AN3 peripheral function
pins. Pins R31–R33 of the HD404394 series are also used as AN1–AN3 peripheral function pins. The setting
of peripheral functions for these pins is executed by bits 3 to 0 (AMR13–AMR10) of A/D mode register 1
(AMR1: $019). For the HD404394 series, the use of AMR10 is prohibited (figure 23).
Port mode register A (PMRA: $004)
Bit
3
2
0
1
0
0
0
Initial value
Read/Write
Bit name
—
—
W
W
W
Not used PMRA2 PMRA1 PMRA0
PMRA0
R02/SO Mode Selection
0
1
R02
SO
PMRA2
R03/TOC Mode Selection
0
1
R03
TOC
PMRA1
R01/SI Mode Selection
0
1
R01
SI
Figure 21 Port Mode Register A (PMRA)
46
HD404344R Series/HD404394 Series
Serial mode register (SMR: $005)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
SMR3
SMR2
SMR1
SMR0
Prescaler
Clock Source Division Ratio
R00/SCK
Mode Selection
SMR3
SMR2
SMR1
SMR0
SCK
0
1
Prescaler
Output
R00
0
1
0
1
0
1
0
1
See table 22.
0
0
SCK
1
0
1
System clock
—
Output
Input
1
External clock
—
Figure 22 Serial Mode Register (SMR)
A/D mode register 1 (AMR1: $019)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
AMR13 AMR12 AMR11 AMR10
AMR10* R30/AN0 Mode Selection
0
1
R30
AN0
AMR12
R32/AN2 Mode Selection
0
1
R32
AN2
AMR11
R31/AN1 Mode Selection
0
1
R31
AN1
AMR13
R33/AN3 Mode Selection
0
1
R33
AN3
Note: * Available for the HD404344R series and HD4074344, but not available for the HD404394 series.
Figure 23 A/D Mode Register 1 (AMR1)
47
HD404344R Series/HD404394 Series
Pull-Up MOS Transistor Control
Pull-up MOS, which can be controlled by software, is built into all input/output pins except R10–R23 of the
HD404394 series.
The on/off status of all pull-up MOS pins is controlled by bit 3 (MIS3) of the miscellaneous register (MIS:
$00C) and the port data registers (PDR) of each pin. Each pin can therefore independently switch between
with or without pull-up MOS (table 17 and figure 24).
The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
Miscellaneous register (MIS: $00C)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
MIS3
MIS2
MIS1
MIS0
Pull-Up MOS
On/Off Selection
PMOS On/Off
Selection for Pin R02/SO
MIS3
MIS2
Pull-up MOS off
Pull-up MOS on
On
Off
0
1
0
1
Programming MIS1 and MIS0 to 1 is prohibited.
Figure 24 Miscellaneous Register
How to Deal with Unused I/O Pins
When input/output pins are not being used and are left floating, it is necessary to set these pins to VCC to
reduce the possibility of LSI malfunctions due to noise. This can be done by selecting pull-up MOS for the
pins or by connecting an external pull-up resistor of about 100 kΩ at each unused pin.
48
HD404344R Series/HD404394 Series
Prescaler
The MCU has one built-in prescaler, S (PSS). This divides the system clock and outputs the divided clock
to the peripheral function modules as shown in figure 25.
Clocks for timers B and C except for external events, and clocks for serial interface except for the external
clock are all selected from the prescaler output by programming each mode register.
Prescaler S is an 11-bit counter which inputs the system clock. After an MCU reset clears the prescaler to
$000, it begins dividing the system clock. Prescaler S stops operating due to either an MCU reset or stop
mode. It cannot be stopped by any other mode.
Timer B
Timer C
System
clock
Prescaler S
Serial
Figure 25 Prescaler Output Supply
49
HD404344R Series/HD404394 Series
Timers
The MCU has two built-in timers, B and C. The functions of each timer are listed in table 19.
Table 19
Timer Functions
Functions
Timer B
Available
Available
Available
Available
Available
—
Timer C
Available
—
Clock source
Prescaler S
External event
Free-running
Event counter
Reload
Timer functions
Available
—
Available
Available
Available
Watchdog
PWM
Timer output
—
Timer B
Timer B is an 8-bit multifunction timer that includes free-running, reload, and event counter features. These
are described as follows.
•
•
•
•
By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler
S can be selected, or timer B can be used as an external event counter.
By setting timer mode register B2 (TMB2: $026), timer B can be incremented by each edge detector of
input signals at pin EVNB.
By setting timer write register BL, BU (TWBL, TWBU: $00A, $00B), timer counter B (TCB) can be
written to during reload timer operation.
By setting timer read register BL, BU (TRBL, TRBU: $00A, $00B), the contents of timer counter B can
be read out.
Timer B Operation
•
Free-running/reload timer operation: The selection of the free-running/reload timer, input clock source,
and prescaler division ratio is done by timer mode register B1 (TMB1: $009).
Timer B is initialized to the data which is written to timer write register B (TWBL: $00A, TWBU:
$00B) by software. The data is then incremented in steps of 1 by using the input clock. If the clock
input is continued after timer B is set to $FF, an overflow occurs. Timer B then begins counting again,
setting the timer to the value in timer write register B (TWBL: $00A, TWBU: $00B) when the reload
timer is selected, or reset to $00 when the free-running timer is selected.
50
HD404344R Series/HD404394 Series
The timer B interrupt request flag is set by an overflow. Resetting the timer B interrupt request flag
(IFTB: $002, bit 0) is executed by either software or by an MCU reset.
•
External event counter operation: By setting the external event input as an input clock source, timer B
can operate as an external event counter. The D /INT /EVNB pins are set to be INT /EVNB pins by
0
0
0
port mode register B (PMRB: $024).
The detection edge of the external event counter for timer B is selected as rising edge, falling edge, or
rising/falling edge by timer mode register B2 (TMB2: $026). When the rising/falling edge is selected,
the period must be set to more than 2t between the falling edge and the rising edge.
cyc
Timer B is incremented by 1 using the edge selection in timer mode register B2 (TMB2: $026). Other
functions are based on the free-running/reload timer.
Interrupt request
flag of timer B
(IFTB)
Timer read
register BU
Timer read
(TRBU)
register B lower
(TRBL)
Clock
Timer counter B
(TCB)
Overflow
Free-running
timer control
Timer write
register B upper
(TWBU)
Timer write
register B lower
(TWBL)
Selector
EVNB
Edge
detector
3
Timer mode
register B1
(TMB1)
øPER
System
clock
Prescaler S (PSS)
Edge detection control
2
Timer mode
register B2
(TMB2)
Figure 26 Timer B Free-Running and Reload Operation Block Diagram
51
HD404344R Series/HD404394 Series
Using Timer B Registers
Timer B sets the operation and the read/write data according to the following registers.
Timer mode register B1 (TMB1: $009)
Timer mode register B2 (TMB2: $026)
Timer write register B
(TWBL: $00A, TWBU: $00B)
Timer read register B
(TRBL: $00A, TRBU: $00B)
Port mode register B (PMRB: $024)
•
Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload
timer, input clock, and prescaler division ratio, as shown in figure 27. It is reset to $0 by an MCU reset.
Data written to timer mode register B1 is valid after two instruction cycles. The initial setting of timer
B, which is set by writing to timer write register B (TWBL: $00A, TWBU: $00B), should be
programmed only after a mode change has been effective.
Timer mode register B1 (TMB1: $009)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
TMB13 TMB12 TMB11 TMB10
Free-Running/Reload
TMB13 Timer Selection
Input Clock Period and Input
Clock Source
TMB12 TMB11 TMB10
0
1
Free-running timer
Reload timer
0
1
0
1
0
1
0
1
2048tcyc
512tcyc
128tcyc
32tcyc
8tcyc
0
0
1
1
0
1
4tcyc
2tcyc
D0/INT0/EVNB (external event
input)
Figure 27 Timer Mode Register B1 (TMB1)
52
HD404344R Series/HD404394 Series
•
Timer mode register B2 (TMB2: $026): Two-bit write-only register that sets the input edge detection of
pin EVNB, as shown in figure 28. It is reset to $0 by an MCU reset.
Timer mode register B2 (TMB2: $026)
Bit
3
2
1
0
0
0
Initial value
Read/Write
Bit name
—
—
—
—
W
W
Not used Not used TMB21 TMB20
TMB21 TMB20
EVNB Edge Detection Selection
No detection
0
1
0
1
0
1
Falling-edge detection
Rising-edge detection
Rising- and falling-edge detection
Figure 28 Timer Mode Register B2 (TMB2)
•
Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit
(TWBL) and the upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit
value cannot be guaranteed. See figures 29 and 30.
Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case,
the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the
timer B value. Timer B is initialized to the value in timer write register B at the same time the upper
digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value
needs no change, writing only to the upper digit initializes timer B.
Timer write register B (lower) (TWBL: $00A)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
TWBL3 TWBL2 TWBL1 TWBL0
Figure 29 Timer Write Register B (lower) (TWBL)
Timer write register B (upper) (TWBU: $00B)
Bit
3
2
1
0
Initial value
Read/Write
Bit name
Undefined Undefined Undefined Undefined
W
W
W
W
TWBU3 TWBU2 TWBU1 TWBU0
Figure 30 Timer Write Register B (upper) (TWBU)
53
HD404344R Series/HD404394 Series
•
Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit
(TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit. See figures 31 and
32.
The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is
obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by
reading TRBL, the count of timer B when TRBU is read can be obtained.
Timer read register B (lower) (TRBL: $00A)
Bit
3
2
1
0
Initial value
Read/Write
Bit name
Undefined Undefined Undefined Undefined
R
R
R
R
TRBL3 TRBL2 TRBL1 TRBL0
Figure 31 Timer Read Register B (lower) (TRBL)
Timer read register B (upper) (TRBU: $00B)
Bit
3
2
1
0
Initial value
Read/Write
Bit name
Undefined Undefined Undefined Undefined
R
R
R
R
TRBU3 TRBU2 TRBU1 TRBU0
Figure 32 Timer Read Register B (upper) (TRBU)
•
Port mode register B (PMRB: $024): Write-only register that selects the D /INT /EVNB pin as shown
0
0
in figure 20. It is reset to $0 by an MCU reset.
54
HD404344R Series/HD404394 Series
Timer C
Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features,
which are selected and described as follows.
•
•
•
•
By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S
can be selected.
By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output
(PWM output) is enabled.
By setting timer write register CL, CU (TWCL, TWCU: $00E, $00F), timer counter C (TCC) can be
written to.
By setting timer read register CL, CU (TRCL, TRCU: $00E, $00F), the contents of timer counter C can
be read out.
•
•
An interrupt can be requested when timer counter C overflows.
Timer counter C can be used as a watchdog timer for detecting runaway programs.
55
HD404344R Series/HD404394 Series
System reset signal
Interrupt request
flag of timer C
(IFTC)
Watchdog on
flag (WDON)
Watchdog timer
controller
Timer read register CU (TRCU)
TOC
Timer output
controller
Timer read
register C lower
(TRCL)
Clock
Timer counter C
(TCC)
Overflow
Timer
output
control
Timer write
register C upper
(TWCU)
Timer write
register C lower
(TWCL)
Selector
Free-running/
reload timer
control
3
Timer mode
register C (TMC)
øPER
System
clock
Prescaler S (PSS)
Port mode
register A (PMRA)
Figure 33 Timer C Block Diagram
Timer C Operation
•
Free-running/reload timer operation: The selection of the free-running/reload timer, input clock source,
and prescaler division ratio is done by timer mode register C (TMC: $00D).
Timer C is initialized to the data, which is written to timer write register C (TWCL: $00E, TWCU:
$00F) by software. The data is then incremented in steps of 1 by using the input clock. If the clock input
is continued after timer C is set to $FF, an overflow occurs. Timer C then begins counting again, setting
the timer to the value in timer write register C (TWCL: $00E, TWCU: $00F) when the reload timer is
selected, or reset to $00 when the free-running timer is selected.
The timer C interrupt request flag is set by an overflow. Resetting the timer C interrupt request flag
(IFTC: $002, bit 2) is executed by either software or by an MCU reset.
56
HD404344R Series/HD404394 Series
•
Watchdog timer operation: Timer C can be used as a watchdog timer for programs that may run out of
control. A watchdog timer is enabled when the setting on the watchdog on flag (WDON: $020, bit 1) is
1. When timer C overflows, an MCU reset occurs. This usually controls programs running out of
control by initializing timer C through software before timer C counts up to $FF (figure 34).
$FF + 1
Overflow
Timer C
count value
$00
Time
CPU
operation
Normal
operation
Normal
operation
Timer C
clear
Normal
operation
Timer C
clear
Program
runaway
Reset
Figure 34 Watchdog Timer Operation Flowchart
•
Timer output operation: Timer C can select the timer output mode by selecting the TOC pin after setting
bit 2 (PMRA2) of port mode register A (PMRA: $004) to 1. The output of the TOC pin is initialized to
0 by an MCU reset. PWM output is a pulse output function of variable duty. The output wave differs by
the contents of timer mode register C and timer write register C, as shown in figure 35.
×
T
(N + 1)
TMC3 = 0
(free-running
timer)
×
T
256
T
TMC3 = 1
(reload timer)
T × (256 – N)
Notes: T: Input clock period supplied to counter. (The clock input source and system clock division ratio
are determined by timer mode register C.)
N: Value in timer write register C. (When N = 255 ($FF), PWM output is fixed low.)
Figure 35 PWM Output Waveform
57
HD404344R Series/HD404394 Series
Using Timer C Registers
Timer C sets the operation and the read/write data according to the following registers.
Timer mode register C (TMC: $00D)
Timer write register C (TWCL: $00E, TWCU: $00F)
Timer read register C (TRCL: $00E, TRCU: $00F)
•
Timer mode register C (TMC: $00D): Four-bit write-only register that selects the free-running/reload
timer, input clock, and prescaler division ratio, as shown in figure 36. It is reset to $0 by an MCU reset.
The data written to timer mode register C is valid after two instructions cycles. The initial setting of
timer C, which is set by writing to timer write register C (TWCL: $00E, TWCU: $00F), should be
programmed to execute only after a mode change has been effective.
Timer mode register C (TMC: $00D)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
TMC3
TMC2
TMC1
TMC0
Free-Running/Reload
Timer Selection
TMC2
TMC1
TMC0
Input Clock Period
2048tcyc
TMC3
0
1
0
1
0
1
0
1
0
1
0
0
1
Free-running timer
Reload timer
1024tcyc
1
512tcyc
128tcyc
32tcyc
8tcyc
0
1
4tcyc
2tcyc
Figure 36 Timer Mode Register C (TMC)
58
HD404344R Series/HD404394 Series
•
Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit
(TWCL: $00E) and an upper digit (TWCU: $00F), as shown in figures 37 and 38.
The operation of this register is the same as that of timer write register B.
Timer write register C (lower) (TWCL: $00E)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
TWCL3 TWCL2 TWCL1 TWCL0
Figure 37 Timer Write Register C (lower) (TWCL)
Timer write register C (upper) (TWCU: $00F)
Bit
3
2
1
0
Initial value
Read/Write
Bit name
Undefined Undefined Undefined Undefined
W
W
W
W
TWCU3 TWCU2 TWCU1 TWCU0
Figure 38 Timer Write Register C (upper) (TWCU)
•
Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit
(TRCL: $00E) and upper digit (TRCU: $00F), which allows the upper digit of timer C to be read
directly (figures 39 and 40).
The operation of this register is the same as that of timer read register B.
Timer read register C (lower) (TRCL: $00E)
Bit
3
2
1
0
Initial value
Read/Write
Bit name
Undefined Undefined Undefined Undefined
R
R
R
R
TRCL3 TRCL2 TRCL1 TRCL0
Figure 39 Timer Read Register C (lower) (TRCL)
Timer read register C (upper) (TRCU: $00F)
Bit
3
2
1
0
Initial value
Read/Write
Bit name
Undefined Undefined Undefined Undefined
R
R
R
R
TRCU3 TRCU2 TRCU1 TRCU0
Figure 40 Timer Read Register C (upper) (TRCU)
59
HD404344R Series/HD404394 Series
Notes on Use
When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 20. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.
Table 20
PWM Output Following Update of Timer Write Register
PWM Output
Timer Write Register is Updated during High Timer Write Register is Updated during Low
Mode
PWM Output
PWM Output
Timer write
register
updated to Interrupt
value N
Timer write
register
updated to
value N
Free
running
Interrupt
request
request
T × (N' + 1)
T × (255 – N) T × (N + 1)
T × (255 – N) T × (N + 1)
Reload
Timer write
register
updated to Interrupt
value N
Timer write
register
updated to
value N
Interrupt
request
request
T
T
T × (255 – N)
T
T × (255 – N)
T
60
HD404344R Series/HD404394 Series
Serial Interface
The MCU has a one-channel 8-bit serial interface built in with the following features.
•
One of 12 different internal clocks or an external clock can be selected as the transmit clock. The
internal clocks include the six prescaler outputs divided by two and by four, and the system clock.
•
•
•
During idle states, the serial output pin can be controlled as high or low output.
Transmit clock errors can be detected.
An interrupt request can be generated when any errors occurred or data transfer has completed.
Serial interrupt
request flag
Octal
counter (OC)
SO
(IFS)
Idle
controller
SCK
I/O
Serial data
controller
register (SR)
SI
Clock
1/2
Transfer
control
signal
1/2
Selector
3
Serial mode
register
(SMR)
øPER
System
clock
Prescaler S (PSS)
Port mode
register C
(PMRC)
Figure 41 Serial Interface Block Diagram
61
HD404344R Series/HD404394 Series
Serial Interface Operation
Selection and Changing of Serial Interface Operation Mode: The available settings for port mode
register A (PMRA: $004) and the serial mode register (SMR: $005) are shown in table 21. To change the
operating mode or to initialize the serial interface, write to the serial mode register.
The R0 /SCK pin is controlled by writing data to serial mode register (SMR: $005). The R0 /SI and
0
1
R0 /SO pins are controlled by writing data to port mode register A (PMRA: $004).
2
Table 21
Serial Interface Operating Modes
SMR
Bit 3
1
PMRA
Bit 1
0
Bit 0
Operating Mode
0
1
0
1
Continuous clock output mode
Transmit mode
1
Receive mode
Transmit/receive mode
Setting Serial Clock Source: The transmit clock is set by writing to the serial mode register (SMR: $005)
and port mode register C (PMRC: $025).
Serial Data Setting: Serial data is sent by writing to the serial data register (SRL: $006 and SRU: $007).
Serial data can then be obtained by reading the serial data register. Serial data is shifted by the transmit
clock.
The output of the SO pin is undefined until the first serial data is output after an MCU reset, or until the
output level control is performed during an idle state.
Transfer Control: Serial interface operation is initiated by an STS instruction. The octal counter is reset
by the STS instruction to 000 and then incremented by one by the rising edge of the transmit clock. If eight
rising edges from the transmit clock is input or the serial data transfer is cut-off, the counter is reset to 000,
the serial interrupt request flag (IFS: $003, bit 2) is set, and the serial data transfer stops.
As for using the built-in prescaler output for the transmit clock, selection for the transmit clock frequency
can be from 4t to 8192t by setting bits 2 to 0 (SMR2–SMR0) of the serial mode register (SMR: $005)
cyc
cyc
and bit 0 (PMRC0) of port mode register C (PMRC: $025). Writing to these registers for the setting of the
transmit clock is shown in table 22.
62
HD404344R Series/HD404394 Series
Table 22
Transmit Clock Selection (Prescaler Output)
PMRC
Bit 0
0
SMR
Bit 2
Bit 1
Bit 0
0
Prescaler Division Ratio
Transmit Clock Frequency
0
0
÷ 2048
÷ 512
÷ 128
÷ 32
4096tcyc
1024tcyc
256tcyc
64tcyc
1
1
0
0
1
0
0
1
1
0
0
÷ 8
16tcyc
1
÷ 2
4tcyc
1
0
÷ 4096
÷ 1024
÷ 256
÷ 64
8192tcyc
2048tcyc
512tcyc
128tcyc
32tcyc
1
0
1
1
0
÷ 16
1
÷ 4
8tcyc
Serial Interface Operating States: The serial interface has the following operating states shown in figure
42, both in external clock mode and internal clock mode.
STS wait state
Transmit clock wait state
Transfer state
Continuous clock output (internal clock mode only)
•
•
STS wait state: The serial interface is put into the STS wait state by an MCU reset (00, 10 in figure 42).
While in this state, the serial interface is initialized and does not operate, even if a transmit clock is
provided. If an STS instruction is executed while in this state (01, 11), the serial interface transfers to
the transmit clock wait state.
Transmit clock wait state: Transmit clock wait state period starts from when an STS instruction is
executed until the first transmit clock falling edge. While in the transmit clock wait state, if the transmit
clock is input (02, 12), the octal counter is incremented by the transmit clock, the data in the serial data
register shifts, and the serial interface enters the transfer state. However, note that if continuous clock
output mode is selected in internal clock mode, the serial interface does not enter transfer state but
enters continuous clock output state (17).
By writing to the serial mode register (SMR: $005) (04, 14) while in the transmit clock wait state, the
serial interface changes to the STS wait state.
•
Transfer state: The transfer state period starts from the first falling edge of the transmit clock to the
eighth rising edge of the transmit clock. While in the transfer state, if an STS instruction is executed or
eight pulses of the transmit clock is applied, the octal counter will reset to 000 and the state will change.
If an STS instruction is executed (05, 15), the state changes to the transmit clock wait state. After the
63
HD404344R Series/HD404394 Series
eight pulses of the transmit clock, the state changes to the transmit clock wait state for the external clock
mode (03). Also, the state changes to the STS wait state for the internal clock mode (13). In the internal
clock mode, the transmit clock stops after eight pulses of the transmit clock are output.
While in the transfer state, if the serial mode register (SMR: $005) (06, 16) is written to, the serial
interface is initialized and the state changes to the STS wait state.
After the transfer state has changed to another state, the octal counter is reset to 000 and the serial
interrupt request flag (IFS: $003, 2) is set.
•
Continuous clock output state (internal clock mode only): Continuous clock output state is the state in
which only the transmit clock from the SCK pin is output without data transfer. This can be done only
while in internal clock mode.
When the status of the 1 and 0 bits (PMRA1, PMRA0) of port mode register A (PMRA: $004) is 00
while in transmit clock wait state, the state can be changed to continuous clock output state by enabling
the transmit clock (17). By writing to the serial mode register (SMR: $005) while in continuous clock
output state (18), the state will change to the STS wait state.
STS wait state
(Octal counter = 000,
00
MCU reset
transmit clock disabled)
SMR write 04
←
SMR write (IFS
1) 06
STS instruction 01
02
Transmit clock
Transfer state
(Octal counter = 000)
Transmit clock wait state
(Octal counter = 000)
8 transmit clocks 03 or STS instruction 05 (IFS
1)
←
External clock mode
STS wait state
(Octal counter = 000,
10
MCU reset
SMR write 18
transmit clock disabled)
Continuous clock output state
(PMRA 0, 1 = 0, 0)
14
8 transmit clocks 13 or
SMR write
SMR write (IFS ← 1) 16
11
STS instruction
Transmit clock 17
Transmit clock 12
Transfer state
Transmit clock wait state
(Octal counter = 000)
(Octal counter = 000)
←
STS instruction 15 (IFS
1)
Internal clock mode
Note: Refer to the operating states section for the corresponding encircled numbers.
Figure 42 Serial Interface State Transitions
64
HD404344R Series/HD404394 Series
Output Level Control During Idle States: The output level of the SO pin can be set during either STS
wait state or transmit clock wait state by software. During idle states, the output level is controlled by
writing to bit 1 (PMRC1) of port mode register C (PMRC: $025). An example of output level control
during idle states is shown in figure 43. During transfer state, output level control cannot be executed.
Transmit clock
wait state
Transmit clock
wait state
State
STS wait state
Transfer state
STS wait state
MCU reset
PMRA write
SMR write
PMRC write
Port selection
External clock selection
Dummy write for
state transition
Output level control in
idle states
Output level control in
idle states
Data write for transmission
SRL, SRU
write
STS
instruction
SCK pin
(input)
SO pin
IFS
Undefined
LSB
MSB
Flag reset at transfer completion
External clock mode
Transmit clock
wait state
State
STS wait state
Transfer state
STS wait state
MCU reset
PMRA write
SMR write
PMRC write
Port selection
Internal clock selection
Output level control in
idle states
Output level control in
idle states
Data write for transmission
SRL, SRU
write
STS
instruction
SCK pin
(output)
Undefined
LSB
MSB
SO pin
IFS
Flag reset at transfer completion
Internal clock mode
Figure 43 Example of Serial Interface Operation Sequence
65
HD404344R Series/HD404394 Series
Transmit Clock Error Detection (External Clock Mode): Serial interface will malfunction if a spurious
pulse caused by external noise conflicts with a normal transmit clock during data transfer. A transmit clock
error of this type can be detected as shown in figure 44.
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer is completed and IFS is reset, writing to the serial mode register (SMR: $005)
changes the state from transfer to STS wait. At this time the serial interface is in the transfer state, and the
serial interrupt request flag (IFS: $003, bit 2) is set again, and therefore the error can be detected.
Transfer completion
←
(IFS 1)
Interrupts inhibited
←
IFS
0
SMR write
Yes
Transmit clock
error processing
IFS = 1?
No
Normal
termination
Transmit clock error detection flowchart
Transmit clock wait state
Transfer state
Transmit clock
wait state
Transfer state
State
SCK pin (input)
Noise
1
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit
clock error. When SMR is
written, IFS is set.
SMR write
IFS
Flag set because octal
counter reaches 000.
Flag reset at
transfer completion.
Transmit clock error detection procedure
Figure 44 Transmit Clock Error Detection
66
HD404344R Series/HD404394 Series
Notes On Use:
•
Initializing after writing to registers: If port mode register A (PMRA: $004) is written to in the transmit
clock wait state or transfer state, the serial interface should be reinitialized by writing to the serial mode
register (SMR: $005).
•
Serial interrupt request flag (IFS: $003, bit 2) set: For the serial interface, if the state is changed from
transfer state to another by writing to serial mode register (SMR:$005) or executing the STS instruction
during the first low pulse of the transmit clock, the serial interrupt request flag (IFS: $003, bit 2) is not
set. To set the serial interrupt request flag (IFS: $003, bit 2), a serial mode register (SMR: $005) write
or STS instruction execution must be programmed to be executed after confirming that the SCK pin is
at 1, that is, after executing the input instruction to port R0.
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written using the following registers:
•
•
•
•
•
Serial mode register (SMR: $005)
Port mode register C (PMRC: $025)
Serial data registers (SRL: $006 and SRU: $007)
Port mode register A (PMRA: $004)
Miscellaneous register (MIS: $00C)
Serial Mode Register (SMRA: $005): This register has the following functions (figure 45):
•
•
•
•
R0 /SCK pin function selection
Selection of transmit clock
0
Selection of prescaler division ratio
Serial interface initialization
The write-only serial mode register is reset to $0 by an MCU reset. Writing to the serial mode register
discontinues the transmit clock input to the serial data registers (SRL: $006 and SRU: $007) and the octal
counter. The octal counter is then reset to 000. If the serial mode register is written to during serial interface
operation, data transfer will be cut off and the serial interrupt request flag (IFS: $003, bit 2) will be set.
Data in the serial mode register becomes effective after two instruction execution cycles from the time the
serial mode register is written to. It is therefore necessary to program the STS instruction to be executed
two cycles after the serial mode register is written to.
67
HD404344R Series/HD404394 Series
Serial mode register (SMR: $005)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
SMR3
SMR2
SMR1
SMR0
Prescaler
Clock Source Division Ratio
R00/SCK
Mode Selection
SMR3
SMR2
SMR1
SMR0
SCK
0
1
Prescaler
Output
R00
0
1
0
1
0
1
0
1
See table 22.
0
0
SCK
1
0
1
System clock
—
Output
Input
1
External clock
—
Figure 45 Serial Mode Register (SMR)
Port Mode Register C (PMRC: $025): This register has the following functions:
•
•
Prescaler division ratio selection
Output level control during idle states
Port mode register C is a two-bit write-only register, which cannot be changed during data transfer.
Bit 0 (PMRC0) selects the prescaler division ratio. Only this bit is reset to 0 by an MCU reset.
Bit 1 enables the output level control of the SO pin during an idle state. The output levels at the pins are
therefore changed when writing to bit 1 (PMRC1).
68
HD404344R Series/HD404394 Series
Port mode register C (PMRC: $025)
Bit
3
—
2
—
1
0
0
Initial value
Read/Write
Bit name
Undefined
W
—
—
W
Not used
PMRC1
Not used
PMRC0
PMRC0
Transmit Clock Division Ratio
Prescaler output divided by 2
Prescaler output divided by 4
0
1
PMRC1
Output Level Control in Idle States
Low level
0
1
High level
Figure 46 Port Mode Register C (PMRC)
69
HD404344R Series/HD404394 Series
Serial Data Register (SRL: $006, and SRU: $007): This register has the following functions (figures 47
and 48):
•
•
Transmission data write and shift
Receive data shift and read
Data written to the serial data registers is output from the SO pin, LSB first, synchronously with the falling
edge of the transmit clock.
Also, data from the SI pin (from the LSB) is input synchronously with the rising edge of the transmit clock.
Reading or writing to the serial data register should be performed after data transfer. Read/write operation
to this register during data transfer does not guarantee valid data. The input/output timing chart for the
transmit clock and the data are shown in figure 49.
Serial data register (lower) (SRL: $006)
Bit
3
2
1
0
Initial value
Read/Write
Bit name
Undefined Undefined Undefined Undefined
R/W
SR3
R/W
SR2
R/W
SR1
R/W
SR0
Figure 47 Serial Data Register (SRL)
Serial data register (upper) (SRU: $007)
Bit
3
2
1
0
Initial value
Read/Write
Bit name
Undefined Undefined Undefined Undefined
R/W
SR7
R/W
SR6
R/W
SR5
R/W
SR4
Figure 48 Serial Data Register (SRU)
Ttransmit clock
1
2
3
4
5
6
7
8
Serial output
data
LSB
MSB
Serial input
data latch
timing
Figure 49 Serial Interface Timing
70
HD404344R Series/HD404394 Series
Port Mode Register A (PMRA: 004): This register A has the following functions:
•
•
R0 /SI pin function selection
1
R0 /SO pin function selection
2
Port mode register A is a three-bit write-only register and reset to 0 by an MCU reset, as listed in figure 50.
Port mode register A (PMRA: $004)
Bit
3
2
0
1
0
0
0
Initial value
Read/Write
Bit name
—
—
W
W
W
Not used PMRA2 PMRA1 PMRA0
PMRA0
R02/SO Mode Selection
0
1
R02
SO
PMRA2
R03/TOC Mode Selection
0
1
R03
TOC
PMRA1
R01/SI Mode Selection
0
1
R01
SI
Figure 50 Port Mode Register A (PMRA)
Miscellaneous Register
The miscellaneous register (MIS: $00C) has the following functions:
•
•
Control of R0 /SO pin PMOS
2
Pull-up MOS on/off selection
It is a two-bit write-only register and is reset to $0 by an MCU reset, as listed in figure 51.
71
HD404344R Series/HD404394 Series
Miscellaneous register (MIS: $00C)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
MIS3
MIS2
MIS1
MIS0
Pull-Up MOS
On/Off Selection
PMOS On/Off
Selection for Pin R02/SO
MIS3
MIS2
Pull-up MOS off
Pull-up MOS on
On
Off
0
1
0
1
Programming MIS1 and MIS0 to 1 is prohibited.
Figure 51 Miscellaneous Register
72
HD404344R Series/HD404394 Series
A/D Converter
The MCU has a built-in A/D converter that uses a sequential comparison method with a register ladder. It
can perform a digital conversion with 3 or 4 analog inputs at 8-bit resolution. The following describes the
features of the A/D converter.
•
•
•
•
A/D mode register 1 (AMR1: $019) is used to select digital or analog ports (figure 53).
A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed (figure 54).
The A/D channel register (ACR: $016) is used to select an analog input channel (figure 55).
A/D conversion is started by setting the A/D start flag (ADSF: $020, bit 2) to 1. After the conversion is
completed, converted data is stored in the A/D data register, and at the same time, the A/D start flag is
cleared to 0 (figure 56).
•
•
By setting the I off flag (IAOF: $021, bit 2) to 1, the current flowing through the resistance ladder
can be cut off even in standby or active mode (figure 57).
AD
A/D data registers (ADRL: $017, ADRU: $018) are read-only registers used to store the conversion
result. (ADRL: lower 4 bits, ADRU: upper 4 bits.) These registers cannot be cleared by a reset input.
Also, data in these registers are not guaranteed during the conversion period. After the conversion is
completed, an 8-bit result is set to these registers and kept until the next conversion starts (figures 58,
59, and 60).
Notes On Use:
•
•
•
•
Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF).
Do not write to the A/D start flag during A/D conversion.
Data in the A/D data register during A/D conversion is undefined.
Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop mode. In addition, to save power dissipation while in a stop mode, all
current flowing through the converter’s resistance ladder is cut off.
•
•
Output signal level from other ports should be fixed during A/D conversion.
The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to V . When using a
CC
shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode register as an analog pin will remain
pulled up.
73
HD404344R Series/HD404394 Series
4
A/D mode
register 1
(AMR1)
A/D interrupt
request flag
(IFAD)
A/D mode
register 2
(AMR2)
4
R33/AN3
R32/AN2
A/D data
registers
(ADRU, L)
Encoder
R31/AN1
*1(R30/AN0)
+
Comp
–
A/D channel
register (ACR)
A/D
controller
Control signal
for conversion
time
D/A
*2
VCC (Vref
)
A/D start flag
(ADSF)
IAD off flag
(IAOF)
GND
Operating mode signal (1 in stop mode)
Notes: 1. Available for the HD404344R series and HD4074344. Not available for the HD404394 series.
2. Connected to VCC for the HD404344R series and HD4074344. Connected to Vref for the
HD404394 series.
Figure 52 A/D Converter Block Diagram
74
HD404344R Series/HD404394 Series
A/D mode register 1 (AMR1: $019)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
AMR13 AMR12 AMR11 AMR10
AMR10* R30/AN0 Mode Selection
0
1
R30
AN0
AMR12
R32/AN2 Mode Selection
0
1
R32
AN2
AMR11
R31/AN1 Mode Selection
0
1
R31
AN1
AMR13
R33/AN3 Mode Selection
0
1
R33
AN3
Note: * Available for the HD404344R series and HD4074344, but not available for the HD404394 series.
Figure 53 A/D Mode Register 1 (AMR1)
A/D mode register 2 (AMR2: $01A)
Bit
3
2
1
0
0
Initial value
Read/Write
Bit name
—
—
—
—
—
—
W
Not used Not used Not used AMR20
AMR20
Conversion Time
34tcyc
0
1
67tcyc
Figure 54 A/D Mode Register 2 (AMR2)
75
HD404344R Series/HD404394 Series
A/D channel register (ACR: $016)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
ACR3
ACR2
ACR1
ACR0
ACR3 ACR2 ACR1 ACR0 Analog Input Selection
0
1
0
1
AN0*
AN1
AN2
AN3
0
0
0
1
Note: * Available for the HD404344R series and HD4074344, but not available for the HD404394 series.
Figure 55 A/D Channel Register (ACR)
A/D start flag (ADSF: $020, bit 2)
Bit
3
2
0
1
0
0
Initial value
Read/Write
Bit name
—
—
—
—
R/W
W
Not used ADSF WDON Not used
WDON
A/D Start Flag (ADSF)
A/D conversion completed
A/D conversion started
0
1
Refer to the description of timers
Figure 56 A/D Start Flag (ADSF)
76
HD404344R Series/HD404394 Series
IAD off flag (IAOF: $021, bit 2)
Bit
3
0
2
0
1
0
Initial value
Read/Write
Bit name
—
—
—
—
R/W
RAME
R/W
IAOF Not used Not used
IAD Off Flag (IAOF)
0
1
IAD current flows
IAD current is cut off
RAME
Refer to the description of operating
modes
Figure 57 I Off Flag (IAOF)
AD
ADRU: $018
ADRL: $017
3
2
1
0
3
2
1
0
MSB
Bit 7
LSB
Bit 0
Result
Figure 58 A/D Data Register
A/D data register lower (ADRL: $017)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
R
R
R
R
ADRL3 ADRL2 ADRL1 ADRL0
Figure 59 A/D Data Register Lower (ADRL)
77
HD404344R Series/HD404394 Series
A/D data register upper (ADRU: $018)
Bit
3
1
2
0
1
0
0
0
Initial value
Read/Write
Bit name
R
R
R
R
ADRU3 ADRU2 ADRU1 ADRU0
Figure 60 A/D Data Register Upper (ADRU)
78
HD404344R Series/HD404394 Series
Pin Description in PROM Mode
The HD4074344 and the HD4074394 are PROM versions of a ZTAT microcomputer. In PROM mode,
the MCU stops operating, thus allowing the user to program the on-chip PROM.
Pin Number
MCU Mode
Pin
PROM Mode
DP-28S/FP-28DA FP-30D
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Pin
A5
I/O
Remarks
1
1
R10
I
I
I
I
I
I
I
I
I
2
2
R11
A6
3
3
R12
A7
4
4
R13
A8
5
5
R20
A9
6
6
R21
A10
A11
A12
OE
7
7
R22
8
8
R23
9
9
OSC1
OSC2
GND
10
11
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
O
GND
NC
12
13
14
15
R30/AN0 or Vref
R31/AN1
R32/AN2
R33/AN3
NC
I/O or Vref
I/O
2
M0
I
I/O
XON
O0
I
I/O
I/O
16
17
18
19
20
21
22
23
24
25
26
27
28
VCC
VCC
VPP
RESET
O1
TEST
RESET
R00/SCK
R01/SI
R02/SO
R03/TOC
D0/INT0/EVNB
D1
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O2
I/O
O3
I/O
O4
I/O
A0
I
I
I
I
I
I
A1
D2
A2
D3
A3
D4/STOPC
D5
CE
A4
Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin
2. R30/AN0 is for the HD404344R series and Vref for the HD404394 series in MCU mode.
79
HD404344R Series/HD404394 Series
Programmable ROM Operation
The HD4074344 and HD4074394 on-chip PROMs are programmed in PROM mode.
In PROM mode, the MCU does not operate. It can be programmed like a standard 27256 EPROM using a
standard PROM programmer and a socket adapter as shown in figure 61. Table 23 lists the recommended
PROM programmers and socket adapters.
Since instructions of the HMCS400 series consists of 10 bits, the HMCS400 series microcomputers
incorporate a conversion circuit to enable the use of a general-purpose PROM programmer. By this circuit,
an instruction is read or written to using two addresses, lower five bits and upper five bits. For example, if
4 kwords of on-chip PROM are programmed by a general-purpose PROM programmer, 8 kbytes of
addresses ($0000–$1FFF) should be specified.
Control signals
Address bus
Data bus
CE, OE
2
A14, A13
A12–A0
A14–A0
A12–A0
3
O7–O5
O7–O0
O4–O0
O4–O0
XON
M0
RESET
VCC
GND
VPP
VCC
GND
VPP
HD4074344
HD4074394
28-to-28-pin socket adapter
30-to-28 pin socket adapter
PROM programmer
Figure 61 PROM Mode Connections
80
HD404344R Series/HD404394 Series
Table 23
PROM Programmer and Socket Adapter
PROM Programmer
Maker
Type Name
UNISITE
DATA I/O
AVAL Corp.
PKW-3100
Socket Adapter
Package
Maker
Type Name
DP-28S
Hitachi
HS4344ESS01H
HS4344ESP01H
HS4344ESF01H
FP-28DA
FP-30D
Programming and Verification
The HD4074344 and HD4074394 can be high-speed programmed without causing voltage stress or
affecting data reliability.
Table 24 shows how programming and verification modes are selected.
Table 24
PROM Mode Selection
Pin
Mode
CE
OE
VPP
VPP
VPP
VPP
O0–O4
Programming
Verification
Low
High
High
High
Low
High
Data input
Data output
High impedance
Programming inhibited
Precautions
1. Addresses $0000 to $1FFF should be specified if the PROM is programmed by a PROM programmer.
If address $2000 or higher is accessed, the PROM may not be programmed or verified correctly. Note
that the plastic package type devices cannot be erased and reprogrammed. Set all data in unused
addresses to $FF.
2. Be careful of not using the wrong PROM programmer or socket adapter, which may cause an
overvoltage and damage the LSI. Make sure that the LSI is firmly fixed onto the socket adapter, and
that the socket adapter is firmly fixed to the programmer.
3. The PROM should be programmed with V = 12.5 V. Other PROMs use 21 V. If 21 V is applied to
PP
the HD4074344 or HD4074394, the LSI may become permanently damaged. 12.5 V is Intel’s 27256
V
.
PP
81
HD404344R Series/HD404394 Series
Addressing Modes
RAM Addressing Modes
Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as
a RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.
Memory Register Addressing Mode: The memory registers (MR), which are located in 16 digits from
$040 to $04F, are accessed with the LAMR and XMRA instructions.
ROM Addressing Modes
Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the
JMPL, BRL, or CALL instruction.
1 0 3
W
0
3
0
0
3
0
0
Y
X
Instruction
Opcode
9
7
3
9
RAM address
RAM address 0 0 0 1 0 0
Register Indirect Addressing
Memory Register Addressing
1st instruction
word
2nd instruction
word
9
0 9
0
0
Opcode
Instruction
9
RAM address
Direct Addressing
Figure 62 RAM Addressing Modes
82
HD404344R Series/HD404394 Series
Current Page Addressing Mode: A program can branch to any address in the current page (256 words per
page) by executing the BR instruction.
Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page
subroutine area ($0000–$003F) by executing the CAL instruction.
Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.
1st
2nd
instruction word instruction word
9
3
0 9
0
9
5
0
Opcode
Opcode
Operand
Operand
13
0
13
0
Program counter
Direct Addressing
Program counter 0 0 0 0 0 0 0 0
Zero-Page Addressing
Operand
9
7
0
9
3
0
7
0
Opcode
Operand
Opcode
B
A
13
0
13
0
Program counter * * * * * *
Current Page Addressing
Program counter 0 0
Table Data Addressing
Figure 63 ROM Addressing Modes
83
HD404344R Series/HD404394 Series
Addressing Mode for P Instruction: By using the P instruction, the ROM data determined by table data
addressing can be referenced. The lower-order 8 bits of ROM data are written in the accumulator and the B
register when bit 8 of the ROM data is 1, and are written in the R1 and R2 port output registers when bit 9
is 1. If bit 8 and bit 9 are both 1, the ROM data is simultaneously written into the accumulator, the B
register, and the R1 and R2 port output registers. (See figure 64.)
The program counter is not affected by the P instruction.
Instruction
Opcode
p3 p2 p1 p0
[P]
B register
Accumulator
B3 B2 B1 B0 A3 A2 A1 A0
0
0
RA13RA12RA11RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
Referenced ROM address
ROM data
Address
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
B3 B2 B1 B0 A3 A2 A1 A0
Accumulator, B register
RO8 = 1
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
R23 R22 R21 R20 R13 R12 R11 R10
Pattern Output
Output registers R1, R2
RO9 = 1
Figure 64 P Instruction
84
HD404344R Series/HD404394 Series
BR Branching Instruction at Page Boundary: When the BR instruction is at a page boundary (256n +
255), the address in the program counter is transferred over to point to the next page as done by the internal
hardware. Therefore, executing the BR instruction at a page boundary will cause the program to branch to
the next page. (See figure 65.)
256 (n – 1) + 255
256n
BR AAA
AAA
NOP
BR AAA
BR BBB
256n + 254
256n + 255
256 (n + 1)
BBB
NOP
Figure 65 BR Instruction at Page Boundary
85
HD404344R Series/HD404394 Series
Absolute Maximum Ratings
Item
Symbol
VCC
Value
Unit
V
Notes
Supply voltage
Programming voltage
Pin voltage
–0.3 to +7.0
–0.3 to +14.0
VPP
V
1
VT
–0.3 to VCC + 0.3 V
2
–0.3 to +15.0
V
3
Total permissible input current
Total permissible output current
Maximum input current
∑IO
–∑IO
IO
100
mA
mA
mA
mA
mA
°C
4
30
5
30
6, 7
6, 8
9
4
Maximum output current
Operating temperature
Storage temperature
–IO
Topr
Tstg
4
–20 to +75
–55 to +125
10
11
°C
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation
must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.
1. Applies to pin TEST (VPP) of the HD4074344 and HD4074394.
2. Applies to the following pins.
HD404344R series and HD4074344: D0–D5, R0, R1, R2, R3
HD404394 series:
D0–D5, R0, R13, R2, R31–R33
3. Applies to the following pins.
HD404394 series:
R10–R12
4. The total permissible input current is the total of input currents simultaneously flowing in from all
the I/O pins to GND.
5. The total permissible output current is the total of output currents simultaneously flowing out from
VCC to all I/O pins.
6. The maximum input current is the maximum current flowing from each I/O pin to GND.
7. Applies to D1, D2, R1, and R2.
8. Applies to the following pins.
HD404344R series and HD4074344: D0, D3–D5, R0, R3
HD404394 series:
D0, D3–D5, R0, R31–R33
9. The maximum output current is the maximum current flowing out from VCC to each I/O pin.
10. The operating temperature indicates the temperature range in which power can be supplied to
the LSI (voltage Vcc shown in the electrical characteristics tables can be applied).
11. In the case of chips, the storage specification differs from that of the package products. Please
consult your Hitachi sales representative for details.
86
HD404344R Series/HD404394 Series
Electrical Characteristics
DC Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R,
HD40C4341R: V = 2.5 to 5.5 V, GND = 0 V, T = –20 to +75°C, HCD404344R, HCD40C4344R:
CC
a
V
= 2.5 to 5.5 V, GND = 0 V, T = +75°C, HD404394, HD404392, HD404391, HD4074344,
CC
a
HD4074394: V = 2.7 to 5.5 V, GND = 0 V, T = –20 to +75°C, unless otherwise specified)
CC
a
Item
Symbol Pins
Min
Typ Max
Unit Test Condition
Notes
Input high
voltage
VIH
RESET, SCK,
0.8VCC
—
VCC + 0.3
V
INT0, STOPC,
EVNB
SI
0.7VCC
VCC – 0.5
–0.3
—
—
—
VCC + 0.3
VCC + 0.3
0.2VCC
V
V
V
OSC1
Input low
voltage
VIL
RESET, SCK,
INT0, STOPC,
EVNB
SI
–0.3
–0.3
—
—
—
0.3VCC
0.5
V
V
OSC1
Output high VOH
voltage
SCK, SO, TOC VCC – 1.0
—
V
–IOH = 0.5 mA
IOL = 0.5 mA
Output low
voltage
VOL
SCK, SO, TOC
—
—
—
—
0.4
1
V
I/O leakage |IIL|
current
RESET, SCK,
SI, SO, TOC,
OSC1, INT0,
STOPC, EVNB
VCC
µA
Vin = 0 V to VCC
1
2
Current
ICC1
—
—
3.5
mA
VCC = 5 V,
dissipation in
active mode
fOSC = 4 MHz
ICC2
—
—
—
—
0.4
0.5
1.5
mA
mA
mA
VCC = 3 V,
2, 4
5
fOSC = 400 kHz
VCC = 5 V,
Current
ISBY1
VCC
3
dissipation in
standby
mode
fOSC = 4 MHz
ISBY2
—
—
—
—
—
—
0.2
0.4
0.6
mA
mA
mA
VCC = 3 V,
3, 4
fOSC = 400 kHz
VCC = 5 V,
3, 5
ISBY3
3, 5, 6
f
OSC = 800 kHz
87
HD404344R Series/HD404394 Series
DC Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R,
HD40C4341R: V = 2.5 to 5.5 V, GND = 0 V, T = –20 to +75°C, HCD404344R, HCD40C4344R:
CC
a
V
= 2.5 to 5.5 V, GND = 0 V, T = +75°C, HD404394, HD404392, HD404391, HD4074344,
CC
a
HD4074394: V = 2.7 to 5.5 V, GND = 0 V, T = –20 to +75°C, unless otherwise specified) (cont)
CC
a
Item
Symbol Pins
Min
Typ Max
Unit Test Condition
Notes
Current
dissipation in
stop mode
ISTOP
VCC
—
—
—
10
—
µA
Vin (RESET) =
VCC – 0.3 V to VCC
Vin (TEST) =
0 to 0.3 V
,
Stop mode
retaining
voltage
VSTOP
VCC
2
V
Notes: 1. Excludes current flowing through pull-up MOS and output buffers.
2. ICC is the source current when no I/O current is flowing while the MCU is in reset state.
Test conditions: MCU: Reset
Pins: RESET, TEST at GND
D0–D5, R0–R3 at VCC
3. ISBY is the source current when no I/O current is flowing while the MCU timer is operating.
Test conditions: MCU: I/O reset
Standby mode
Pins:
RESET at VCC
TEST at GND
D0–D5, R0–R3 at VCC
4. Applies to the HD404394 series and HD4074344.
5. Applies to the HD404344R series.
6. The current in case of excluding the current through A/D converters ladder resistance (flag IAOF is
set to “1”). Circuit structure and circuit constants of oscillator circuit is the following condition.
Circuit Structure
Circuit Constants
C1
Ceramic oscillator: KBR-800FTR (KYOSERA)
C1 = C2 = 100 pF
Rf = 1 MΩ
Rd = 2.2 kΩ
OSC1
OSC2
Ceramic
oscillator
Rf
Rd
C2
88
HD404344R Series/HD404394 Series
I/O Characteristics for Standard Pins (HD404344R, HD404342R, HD404341R, HD40C4344R,
HD40C4342R, HD40C4341R: V
= 2.5 to 5.5 V, GND = 0 V, T = –20 to +75°C, HCD404344R,
CC
a
HCD40C4344R: V
= 2.5 to 5.5 V, GND = 0 V, T = +75°C, HD404394, HD404392, HD404391,
CC
a
HD4074344, HD4074394: V
specified)
= 2.7 to 5.5 V, GND = 0 V, T = –20 to +75°C, unless otherwise
a
CC
Pins
HD404344R HD404394
Item
Symbol Series,
Series
Min
Typ Max
Unit Test Condition Note
HD4074344
Input high VIH
voltage
D0–D5,
D0–D5,
0.7VCC
—
VCC + 0.3 V
R0–R3
R0, R13, R2,
R31–R33
D0–D5,
Input low
voltage
VIL
D0–D5,
R0–R3
–0.3
—
0.3VCC
V
R0, R13, R2,
R31–R33
D0–D5,
Output high VOH
voltage
D0–D5,
R0–R3
VCC – 1.0 —
VCC – 0.5 —
—
V
–IOH = 0.5 mA
R0,
R31–R33
R13, R2
D0–D5,
—
—
V
V
500 kΩ at VCC
2
Output low VOL
voltage
D0–D5,
R0–R3
—
—
0.4
IOL = 0.5 mA
R0, R13, R2,
R31–R33
D1, D2,
D1, D2,
R1, R2
D0–D5,
R0–R3
—
—
—
—
2.0
1
V
I
OL = 15 mA,
R13, R2
D0–D5,
VCC = 4.5–5.5 V
Input
|IIL|
µA Vin = 0 V to VCC
1
leakage
current
R0, R13, R2,
R31–R33
D0–D5,
Pull-up
MOS
–IPU
D0–D5,
R0–R3
30
150 300
µA VCC = 5 V,
R0,
Vin = 0 V
current
R31–R33
Notes: 1. Output buffer current and pull-up MOS current are excluded.
2. Applies to the HD404394 series.
89
HD404344R Series/HD404394 Series
I/O Characteristics for NMOS Intermediate-Voltage Pins for HD404394 Series (V = 2.7 to 5.5 V,
CC
GND = 0 V, T = –20 to +75°C, unless otherwise specified)
a
Item
Symbol Pins
Min
Typ Max
Unit Test Condition
Notes
Input high voltage
Input low voltage
Output high voltage
Output low voltage
VIH
VIL
R10–R12 0.7VCC
R10–R12 –0.3
R10–R12 11.5
—
—
—
—
—
12.0
0.3VCC
—
V
V
1
1
1
1
1
VOH
VOL
V
V
V
500 kΩ at 12 V
IOH = 0.5 mA
R10–R12
R10–R12
—
—
0.4
2.0
IOL = 15 mA,
VCC = 4.5 to 5.5 V
Vin = 0 V to 12 V
I/O leakage current
|IIL|
R10–R12
—
—
20
µA
1, 2
Notes: 1. Applies to the HD404394 series.
2. Excludes output buffer current.
A/D Converter Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R,
HD40C4342R, HD40C4341R: V = 2.5 to 5.5 V, GND = 0 V, T = –20 to +75°C, HCD404344R,
CC
a
HCD40C4344R: V
= 2.5 to 5.5 V, GND = 0 V, T = +75°C, HD404394, HD404392, HD404391,
CC
a
HD4074344, HD4074394: V
specified)
= 2.7 to 5.5 V, GND = 0 V, T = –20 to +75°C, unless otherwise
a
CC
Item
Analog reference voltage Vref
Analog input voltage AVin
Symbol Pins
Min
Typ Max Unit
Test Condition
Note
Vref
0.5VCC
—
—
—
—
VCC
VCC
Vref
V
V
V
2
1
2
AN0–AN3 GND
AN1–AN3 GND
—
Current flowing between IAD
ref and GND
200 µA
Vref = VCC = 5.0 V 2
V
Analog input capacitance CAin
Resolution
AN0–AN3
—
—
0
15
8
—
—
4
pF
Bit
Number of input channels
—
—
—
—
—
—
—
Channel
Channel
LSB
LSB
LSB
tcyc
1
2
1
0
3
Absolute accuracy
AN0–AN3 –2.0
AN0–AN3 –2.5
AN1–AN3 –3.0
34
2.0
2.5
3.0
67
—
Ta = 25°C,
2
Vref = VCC = 5.0 V 3
Conversion time
Input impedance
AN0–AN3
1
MΩ
fOSC = 1 MHz,
Vin = 0 V
Notes: 1. Applies to the HD404344R series.
2. Applies to the HD4074344.
3. Applies to the HD404394 series.
90
HD404344R Series/HD404394 Series
AC Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R,
HD40C4341R: V
= 2.5 to 5.5 V, GND = 0 V, T = –20 to +75°C, HCD404344R, HCD40C4344R:
CC
a
V
= 2.5 to 5.5 V, GND = 0 V, T = +75°C, HD404394, HD404392, HD404391, HD4074344,
CC
a
HD4074394: V = 2.7 to 5.5 V, GND = 0 V, T = –20 to +75°C, unless otherwise specified)
CC
a
Item
Symbol Pins
Min Typ Max Unit Test Condition Note
Clock oscillation frequency fOSC
(ceramic oscillator)
OSC1, OSC2
0.4
—
4.5
3.5
10
MHz Division by 4
Clock oscillation frequency fOSC
(resistor oscillator)
OSC1, OSC2
1.0
2.0
—
MHz Division by 4
Rf = 20 kΩ
Instruction cycle time
(external clock, ceramic
oscillator)
tcyc
0.89
µs
Division by 4
Instruction cycle time
(resistor oscillator)
tcyc
tRC
1.14
—
—
—
—
—
—
—
4.0
2
µs
Division by 4
Rf = 20 kΩ
Oscillation setting time
(external clock)
OSC1, OSC2
OSC1, OSC2
OSC1, OSC2
OSC1
ms
ms
ms
ns
1
Oscillation setting time
(ceramic oscillator)
tRC
—
2
1
Oscillation setting time
(resistor oscillator)
tRC
—
0.5
—
—
Rf = 20 kΩ
1, 11
External clock high-level
width
tCPH
tCPL
92
92
2
2
External clock low-level
width
OSC1
ns
External clock rise time
External clock fall time
tCPr
tCPf
tIH
OSC1
—
—
2
—
—
—
20
20
—
ns
2
2
3
OSC1
ns
INT0, EVNB high-level
width
INT0, EVNB
tcyc
INT0, EVNB low-level
width
tIL
INT0, EVNB
2
—
—
tcyc
3
RESET low-level width
STOPC low-level width
RESET rise time
tRSTL
tSTPL
tRSTr
tSTPr
RESET
STOPC
RESET
STOPC
2
—
—
—
—
—
—
20
20
tcyc
tRC
ms
ms
4
5
4
5
1
—
—
STOPC rise time
91
HD404344R Series/HD404394 Series
AC Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R,
HD40C4341R: V
= 2.5 to 5.5 V, GND = 0 V, T = –20 to +75°C, HCD404344R, HCD40C4344R:
CC
a
V
= 2.5 to 5.5 V, GND = 0 V, T = +75°C, HD404394, HD404392, HD404391, HD4074344,
CC
a
HD4074394: V = 2.7 to 5.5 V, GND = 0 V, T = –20 to +75°C, unless otherwise specified) (cont)
CC
a
Item
Input capacitance
Symbol Pins
Min Typ Max Unit Test Condition Note
Cin
All input pins
except TEST,
—
—
15
pF
f = 1 MHz,
Vin = 0 V
V
ref and R10–R12
TEST
—
—
15
pF
f = 1 MHz,
Vin = 0 V
6
—
—
—
—
—
—
—
—
40
30
15
30
pF
pF
pF
pF
7
Vref
8
R10–R12
9
10
Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the
following situations:
a.
b.
c.
After VCC reaches the minimum specification value at power-on.
After RESET input goes low when stop mode is cancelled.
After STOPC input goes low when stop mode is cancelled.
To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET
or STOPC must be input for at least a duration of tRC
.
When using a ceramic oscillator, consult with the manufacturer to determine what stabilization
time is required, since it will depend on the circuit constants and stray capacitance.
2. Refer to figure 66.
3. Refer to figure 67.
4. Refer to figure 68.
5. Refer to figure 69.
6. Applies to the HD404341R, HD404342R, HD404344R, HD404391, HD404392, and HD404394.
7. Applies to the HD4074344 and HD4074394.
8. Applies to the HD404394 series.
9. Applies to the HD404344R series.
10. Applies to the HD404394 series and HD4074344.
11. Applies to the HD40C4344R, HD40C4342R, HD404341R
92
HD404344R Series/HD404394 Series
Serial Interface Timing Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R,
HD40C4342R, HD40C4341R: V
= 2.5 to 5.5 V, GND = 0 V, T = –20 to +75°C, HCD404344R,
CC
a
HCD40C4344R: V
= 2.5 to 5.5 V, GND = 0 V, T = +75°C, HD404394, HD404392, HD404391,
CC
a
HD4074344, HD4074394: V
specified)
= 2.7 to 5.5 V, GND = 0 V, T = –20 to +75°C, unless otherwise
a
CC
During Transmit Clock Output
Item
Symbol
Pins Test Condition Min
Typ
Max
Unit
Note
Transmit clock cycle time
tScyc
SCK
SCK
SCK
SCK
SCK
SO
Load shown in
figure 71
1
—
—
tcyc
1
Transmit clock high width
Transmit clock low width
Transmit clock rise time
Transmit clock fall time
tSCKH
tSCKL
tSCKr
tSCKf
Load shown in 0.4
figure 71
—
—
—
—
—
—
tScyc
tScyc
ns
1
1
1
1
1
Load shown in 0.4
figure 71
—
Load shown in
figure 71
—
—
—
80
80
300
Load shown in
figure 71
ns
Serial output data delay time tDSO
Load shown in
figure 71
ns
Serial input data setup time
Serial input data hold time
tSSI
tHSI
SI
SI
100
200
—
—
—
—
ns
ns
1
1
During Transmit Clock Input
Item
Symbol
Pins Test Condition Min
Typ
—
Max
—
Unit
tcyc
tScyc
tScyc
ns
Note
Transmit clock cycle time
Transmit clock high width
Transmit clock low width
Transmit clock rise time
Transmit clock fall time
tScyc
SCK
SCK
SCK
SCK
SCK
SO
1
1
1
1
1
1
1
tSCKH
tSCKL
tSCKr
tSCKf
0.4
0.4
—
—
—
—
—
—
—
—
80
—
80
ns
Serial output data delay time tDSO
Load shown in
figure 71
—
300
ns
Serial input data setup time tSSI
SI
SI
100
200
—
—
—
—
ns
ns
1
1
Serial input data hold time
tHSI
Note: 1. Refer to figure 70.
93
HD404344R Series/HD404394 Series
OSC1
1/fCP
VCC – 0.5 V
tCPL
tCPH
0.5 V
tCPr
tCPf
Figure 66 External Clock Timing
INT0, EVNB
0.8VCC
0.2VCC
tIL
tIH
Figure 67 Interrupt Timing
RESET
0.8VCC
0.2VCC
tRSTL
tRSTr
Figure 68 RESET Timing
STOPC
0.8VCC
tSTPL
0.2VCC
tSTPr
Figure 69 STOPC Timing
94
HD404344R Series/HD404394 Series
tScyc
t SCKf
tSCKr
tSCKL
VCC – 0.5 V (0.8VCC)*
0.4 V (0.2VCC)*
SCK
SO
SI
tSCKH
tDSO
VCC – 0.5 V
0.4 V
t SSI
t HSI
0.7VCC
0.3VCC
Note: * VCC – 0.5 V and 0.4 V are the threshold voltages for transmit clock output, and
0.8VCC and 0.2VCC are the threshold voltages for transmit clock input.
Figure 70 Serial Interface Timing
VCC
RL = 2.6 kΩ
Test
point
Hitachi
1S2074
R =
12 kΩ
C =
30 pF
H
or equivalent
Figure 71 Timing Load Circuit
95
HD404344R Series/HD404394 Series
2.0
2.5
2.0
1.5
1.0
0.5
Ta = 25°C, fcyc = fosc/4
Sample: Typ
Ta = 25°C, Rf = 20 kΩ
cyc = fosc/4
Sample: Typ
f
fosc = 4 MHz
fosc = 2 MHz
1.5
fosc = 1 MHz
fosc = 800 kHz
fosc = 400 kHz
1.0
0.5
0.0
0.0
1
2
3
4
5
6
1
2
3
4
5
6
Vcc (V)
Vcc (V)
(a) Icc vs Vcc Characteristics
(ceramic oscillator)
(b) Icc vs Vcc Characteristics
(resistor oscillator)
3.5
3.0
2.5
2.0
1.5
5.0
4.0
3.0
2.0
1.0
Ta = 25°C, Rf = 20 kΩ
Sample: Typ
Ta = 25°C, Sample: Typ
Vcc = 5 V
Vcc = 3.5 V
Vcc = 2.5 V
1.0
0.0
1
2
3
4
5
6
0
10
20
30
40
50
Vcc (V)
Rf (kΩ)
(c) fosc vs Vcc Characteristics
(d) fosc vs Rf Characteristics
(resistor oscillator)
(resistor oscillator)
2.5
2.0
1.5
1.0
0.5
Ta = 25°C
Sample: Typ
Vcc = 4.5 V
Vcc = 5 V
Vcc = 5.5 V
0.0
0
10
20
30
40
50
IOL (mA)
(e) VOL vs IOL Characteristics
(D1, D2, R1, R2 pins)
Figure 72 Characteristics curve HD404344R series (consultation value)
96
HD404344R Series/HD404394 Series
Notes On ROM Out
Please pay attention to the following items regarding ROM out.
On ROM out, fill the ROM area indicated below with 1s to create the same data size as 4-kword versions
(HD404344R and HD404394). A 4-kword data size is required to change ROM data to mask
manufacturing data since the program used is for a 4-kword version.
This limitation apply to the case of using EPROM and the case of using data base.
ROM 1 kwords version:
HD404341R, HD40C4341R,
HD404391
ROM 2 kwords version:
HD404342R, HD40C4342R,
HD404392
Address $0400 to $0FFF
Address $0800 to $0FFF
$0000
$0000
Vector address
Vector address
$000F
$0010
$000F
$0010
Zero page subroutine
(64 words)
Zero page subroutine
(64 words)
$003F
$0040
$003F
$0040
Pattern and program
(1,024 words)
Pattern and program
(2,048 words)
$03FF
$0400
$07FF
$0800
Not used
Not used
$0FFF
$0FFF
Fill this area with all 1s
97
HD404344R Series/HD404394 Series
HD404341R/HD404342R/HD404344R/HCD404344R/HD40C4341R/HD40C4342R/
HD40C4344R/HCD40C4344R Option List
Please check off the appropriate applications and enter the necessary information.
Date of order
Customer
Department
Name
ROM code name
LSI number
1. ROM size
HD404341R
HD404342R
HD404344R
HCD404344R
1-kword
2-kword
4-kword
4-kword
HD404341R
HD404342R
HD404344R
1-kword
2-kword
4-kword
Ceramic oscillator
External clock
RC oscillator
HCD40C4344R 4-kword
2. ROM code media
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
3. System oscillator (OSC1–OSC2) (Shaded areas indicate selections that are not available.)
HD404341R/HD404342R/HD404344R/HCD404344R
HD40C4341R/HD40C4342R/HD40C4344R/HCD40C4344R
Ceramic oscillator
External clock
RC oscillator
f =
f =
MHz
MHz
4. Stop mode
5. Package type
Used
DP-28S
FP-28DA
FP-30D
Chip
Not used
Note: The specifications of shipped chips differ from of the package product.
Please contact our sales staff for details.
98
HD404344R Series/HD404394 Series
HD404391/HD404392/HD404394 Option List
Please check off the appropriate applications and enter the necessary information.
Date of order
Customer
Department
Name
ROM code name
LSI number
1. ROM size
HD404391
HD404392
HD404394
1-kword
2-kword
4-kword
2. ROM code media
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
3. System oscillator (OSC1–OSC2)
Ceramic oscillator
External clock
f =
f =
MHz
MHz
4. Stop mode
Used
Not used
5. Package type
DP-28S
FP-28DA
FP-30D
99
HD404344R Series/HD404394 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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For further information write to:
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Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
100
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