HD6477042VF16 [HITACHI]
RISC Microcontroller, 32-Bit, OTPROM, SH7000 CPU, 16.7MHz, CMOS, PQFP112, 20 X 20 MM, QFP-112;
| 型号： | HD6477042VF16 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | RISC Microcontroller, 32-Bit, OTPROM, SH7000 CPU, 16.7MHz, CMOS, PQFP112, 20 X 20 MM, QFP-112 可编程只读存储器 时钟 微控制器 外围集成电路 |
| 文件： | 总121页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SuperH RISC engine
SH7040 Series
On-Chip Supporting Modules
Application Note
Name
Hitachi Micro Systems, Incorporated
1/24/97
Notice
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form,
the whole or part of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from
accidents or any other reasons during operation of the user’s unit according to this
document.
4. Circuitry and other examples described herein are meant merely to indicate the
characteristics and performance of Hitachi’s semiconductor products. Hitachi
assumes no responsibility for any intellectual property claims or other problems that
may result from applications based on the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of
any third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in
MEDICAL APPLICATIONS without the written consent of the appropriate officer
of Hitachi’s sales company. Such use includes, but is not limited to, use in life
support systems. Buyers of Hitachi’s products are requested to notify the relevant
Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Preface
The SH7040, SH7041, SH7042, and SH7043 are high-performance microcomputers with a 32-bit
SH-2 CPU core that uses a RISC (reduced instruction set computer) type instruction set, and
comprehensive on-chip peripheral functions.
On-chip peripherals include ROM, RAM, a 16-bit multifunction timer pulse unit (MTU), serial
communication interface (SCI), port output enable (POE), data transfer controller (DTC), and
DMA controller (DMAC), enabling these microcomputers to be used for a wide range of
applications covering small to large-scale systems.
This Application Note includes sample tasks that use the SH7040 Series’ on-chip peripheral
functions, which we hope users will find useful in carrying out software design.
The operation of the task programs in this Application Note has been checked, but operation
should be confirmed again before any of these programs are actually used.
Contents
Section 1 Using the SH7040 Series Application Note..............................................
1.1 Application Note Organization..........................................................................................
1
1
Section 2 SH7040 Series On-Chip Supporting Modules .........................................
2.1 Pulse High and Low Width Measurement (MTU)............................................................
3
3
2.2 Pulse Output (MTU).......................................................................................................... 11
2.3 PWM 4-Phase Output (MTU) ........................................................................................... 17
2.4 PWM 7-Phase Output (MTU) ........................................................................................... 25
2.5 Positive-Phase and Opposite-Phase PWM 3-Phase Output (MTU).................................. 33
2.6 Complementary PWM 3-Phase Output (MTU) ................................................................ 41
2.7 2-Phase Encoder Count (MTU)......................................................................................... 53
2.8 Externally Triggered Timer Waveform Cutoff (MTU)..................................................... 67
2.9 DC Motor Control Signal Output (MTU).......................................................................... 75
2.10 Activation of A/D Conversion by MTU and Storage of Conversion
Results (A/D, DTC)........................................................................................................... 83
2.11 RAM Monitor Using DMAC (DMAC, SCI) .................................................................... 95
Appendix A
A.1 Header File ........................................................................................................................ 109
Section 1 Using the SH7040 Series Application Note
This Application Note describes the peripheral functions of the SH7040 Series by means of simple
sample tasks.
1.1 Application Note Organization
The on-chip I/O volume uses the layout shown in figure 1 to describe the use of the peripheral
functions.
On-chip I/O volume
Specifications
Functions Used
Operation
Software
Modules
Arguments
Internal Registers
RAM
Flowchart
Program List
Figure 1 Application Note Organization
HITACHI 1
Specifications
Describes the system specifications for each task.
Functions Used
Describes the features of the peripheral function(s) used in the sample task, and peripheral
function assignment.
Operation
Describes the operation of each task, using timing charts.
Software
1. Modules
Describes the software modules used in the operation of the sample task.
2. Arguments
Describes the input arguments needed to execute the module, and the output arguments after
execution.
3. Internal Registers
Describes the peripheral function internal registers (timer control registers, serial mode
registers, etc.) set by the modules.
4. RAM
Describes the labels and functions of the RAM used by the modules.
Flowchart
Describes the software that executes the sample task, using a general flowchart.
Program List
Shows a program list of the software that executes the sample task.
2 HITACHI
Section 2 SH7040 Series On-Chip Supporting Modules
2.1 Pulse High and Low Width Measurement
MTU (Input Capture)
Specifications
1. Pulse high- and low-level widths are measured as shown in figure 2-1-1, and stored in RAM.
2. At 28.7 MHz operation, pulse high- and low-level widths of 35 ns to 2.28 ms can be measured,
in 35 ns units.
Pulse
Pulse high-level width
Pulse low-level width
Figure 2-1-1 Pulse Width Measurement Timing
HITACHI 3
Functions Used
1. In this sample task, pulse high- and low-level widths are measured using ch0.
a. Figure 2-1-2 shows the ch0 block diagram. This task uses the following functions.
•
A function that performs detection of the rising edge and falling edge of a pulse, and
sets the timer value at that point in an internal register (input capture)
•
•
A function that clears the timer counter when input capture occurs (counter clear)
A function that initiates interrupt handling on detection of the rising edge and falling
edge of a pulse
Timer I/O control register 0H
(TIOR0H)
Timer control register 0
(TCR0)
(Detected edge
specification)
(Input capture clear
specification)
Pulse input
Edge detection and
capture signal generation
circuit
Input capture interrupt 0A
(TGIOA)
Input capture 0A
input pin
(TIOC0A)
Timer general register 0A
(TGR0A)
Timer counter 0
(TCNT0)
Figure 2-1-2 MTU/ch0 Block Diagram
2. Table 2-1-1 shows the function assignments for this sample task. MTU functions are assigned
as shown in this table to measure pulse high- and low-level widths.
Table 2-2-1 Function Assignment
Pin/Register Name
TCR0
Function Assignment
Selects counter clear source
TIOR0H
Selects input capture signal input edge
Inputs pulse to be measured
TIOC0A
TGR0A
Detects counter value at rise and fall of pulse
TGI0A
Initiates pulse high- and low-level width measurement on rise and fall of
pulse
4 HITACHI
Operation
Figure 2-1-3 shows the principles of the operation. Pulse high- and low-level widths are measured
by means of SH7040 Series hardware and software processing as shown in the figure.
Immediately
after reset
Input pulse
(TIOC0A)
ch0
counter
value
H'00
Time
Hardware processing
None
Hardware processing
Hardware processing
1. TGI0A generation
2. Transfer TCNT0 value
to TGR0A
1. TGI0A generation
2. Transfer TCNT0 value
to TGR0A
Software processing
Initialization
1. Enable pulse input
from TIOC0A
2. Set TGR0A rising edge
as pulse detected edge
3. Enable TGI0A
Software processing
Software processing
TGI0A processing
1. TGR0A value → pulse
low-level width
2. Set falling edge as
detected edge
TGI0A processing
1. TGR0A value → pulse
high-level width
2. Set rising edge as
detected edge
4. Start count operation
Figure 2-1-3 Principles of Pulse Width Measurement Operation
HITACHI 5
Software
1. Modules
Module Name
Label
Function Assignment
Main routine
pwhlmn
pwhl1
MTU initialization
Pulse high- and low-level
width measurement
Initiated by TGI0A; measures pulse high- and low-
level widths according to TGR0A value and sets
result in RAM
2. Arguments
Label/
Data
Input/
Register Name Function Assignment
Length
Module
Output
pwh_hdata Setting of timer value corresponding to
1 word
Pulse high-
and low-level
width
Output
pulse high-level width
Pulse high-level width is calculated from
following formula:
measurement
Pulse high-level width (ns)
= Timer value × ø cycle (35 ns
at 28.7 MHz operation)
pwh_ldata
Setting of timer value corresponding to
pulse low-level width
1 word
Pulse low-level width is calculated from
following formula:
Pulse low-level width (ns)
= Timer value × ø cycle (35 ns
at 28.7 MHz operation)
6 HITACHI
3. Internal Registers Used
Register Name
PFCE.PECR2
T0.TCR0
Function Assignment
Module
Enables pulse input from TIOC0A
Main routine
Main routine
Selects TCNT counter clock, specifies input
capture A as counter clear source
Pulse high- and low-level
width measurement
T0.TIOR0H
Set so that transfer is performed from TCNT to
TGR0A on detection of pulse rise or fall
Main routine
T0.TIER0
Enables interrupts by TGI0A
T0.TGRA0
TCNT value at rise or fall of pulse is set in this
register and used to calculate pulse cycle
Pulse high- and low-level
width measurement
T0.TSR0
Input capture A generation status
INTC.IPRD
TMRSH.TSTR
Sets TGIOA interrupt priority level to 15
Specifies timer counter operation/disabling
Main routine
4. RAM Used
This sample task does not use any RAM apart from the arguments.
Note: The SH7040 header file name is used as the register label.
HITACHI 7
Flowchart
1. Main routine
pwhlmn
Set input capture A
as ch0 counter clear source
with T0.TCR0
Set rising edge
as pulse detected edge
with T0.TIOR0H
Enable interrupts by TGI0A
with T0.TIER
Set TGI0A
interrupt priority level of 15
with INCT.IPRD
Enable pulse input
from TIOC0A
with PFCE.PECR2
Enable ch0 count operation
with TMRSH.TSTR
8 HITACHI
2. Pulse high- and low-level width measurement
pwhl1
Clear interrupt request flag
No
Rising edge detected?
Yes
Set pulse width
in low-level area
Set pulse width
in high-level area
Set falling edge
as pulse detected edge
with T0.TIOR0H
Set rising edge
as pulse detected edge
with T0.TIOR0H
RTE
HITACHI 9
Program List
/*---------------------------------------------------------------------------*/
/*
INCLUDE FILE
*/
/*---------------------------------------------------------------------------*/
#include <machine.h>
#include "SH7040.H"
/*---------------------------------------------------------------------------*/
/*
PROTOTYPE
*/
/*---------------------------------------------------------------------------*/
void pwhlmn(void);
#pragma interrupt(pwhl1)
/*---------------------------------------------------------------------------*/
/*
RAM ALLOCATION
*/
/*---------------------------------------------------------------------------*/
#define pwh_hdata
#define pwh_ldata
(*(unsigned short *)0xffffe800)
(*(unsigned short *)0xffffe802)
/*---------------------------------------------------------------------------*/
/* MAIN PROGRAM */
/*---------------------------------------------------------------------------*/
void pwhlmn(void)
{
T0.TCR0 = 0x20;
T0.TIOR0H = 0x08;
T0.TIER0 = 0x01;
INTC.IPRD = 0xf000;
set_imask(0x0);
PFCE.PECR2 = 0X0001;
TMRSH.TSTR = 0x01;
while(1);
/* timer clear input capture TGRA0 */
/* input capture rising edge TIOC0A */
/* initialize TGIOA0 */
/* set initialize level=15 */
/* set imask level=0 */
/* TIOCnx select */
/* start timer0 */
/* loop */
}
void pwhl1()
{
T0.TSR0 =0xfe;
/* clear flag */
if(( T0.TIOR0H & 0x0f ) == 0x08)
/* rising edge? */
{
pwh_hdata = T0.TGR0A;
/* set pwh */
T0.TIOR0H |= 0x01
/* input capture falling edge TIOC0A */
}
else
{
pwh_ldata = T0.TGR0A;
T0.TIOR0H &=0xfe;
/* set pwl */
/* input capture rising edge TIOC0A */
10 HITACHI
2.2 Pulse Output
MTU (Output Compare Match)
Specifications
1. Using MTU ch0, a 50% duty pulse of the specified cycle is output as shown in figure 2-2-1.
2. At 28.7 MHz operation, any output pulse cycle from 69.6 ns to 2.28 ms can be set.
Pulse cycle
TIOC0A pin
50%
50%
Figure 2-2-1 Example of Pulse Output
HITACHI 11
Functions Used
1. In this sample task, a pulse with a 50% duty cycle is output using MTU ch0.
a. Figure 2-2-2 shows the MTU/ch0 block diagram for by this sample task. The following
functions are used by ch0:
•
A function for automatically outputting pulses by hardware without software
intervention (output compare)
•
•
A function that clears the timer counter in the event of a compare-match (counter clear)
A function that inverts the output each time a compare-match occurs (toggle output)
(Toggle output setting)
Timer general
register 0A
(TGR0A)
Timer I/O control
register 0H
ø
ø/4
ø/16
ø/64
(TIOR0H)
Compare
match 0A
Pulse
TCLKA/B/C/D
output
TIOC0A
pin
Output compare
signal generator
Comparator A
(Input clock
selection)
Timer control
register 0
(TCR0)
Timer counter 0
(TCNT0)
(Counter clear
source setting)
Figure 2-2-2 MTU/ch0 Block Diagram
2. Table 2-2-1 shows the function assignments for this sample task. MTU functions are assigned
as shown in this table to perform pulse output.
Table 2-2-1 Function Assignment
Pin/Register Name
TIOC0A
Function Assignment
Pulse output pin
TCR0
Selects counter clear source and input clock
Pulse output level setting
1/2 pulse cycle setting
TIOR0H
TGR0A
12 HITACHI
Operation
Figure 2-2-3 shows the principles of the operation. Pulses are output by means of SH7040
hardware and software processing as shown in the figure.
Immediately
after reset
TCNT0 count
value
TGR0A
H'0000
TIOC0A pin
Hardware processing
None
Hardware processing
Hardware processing
1. TGR0A compare-match
generation
1. TGR0A compare-match
generation
Software processing
2. Counter clear
3. High-level output from
TIOC0A
2. Counter clear
3. Low-level output from
TIOC0A
1. Pin function controller
initialization
• Set TIOC0A pin to
output
Software processing
None
Software processing
None
2. Timer initialization
• TCR0 setting
• TIOR0H setting
• Set 1/2 cycle in
TGR0A
3. Start count operation
Figure 2-2-3 Principles of Pulse Output Operation
HITACHI 13
Software
1. Modules
Module Name
Label
Function Assignment
Main routine
puls_out
PFC and pulse output setting
2. Arguments
Label/
Data
Input/
Register Name Function Assignment
Length Module Output
pul_cyc
Setting of timer value corresponding to 1/2 pulse 1 word Main
Input
cycle
routine
Pulse cycle is calculated from following formula:
Pulse cycle (ns) = Timer value × ø cycle
(35 ns at 28.7 MHz
operation)
3. Internal Registers Used
Register Name
PFCE.PECR2
TMRSH.TSTR
T0.TCR0
Function Assignment
Module
Sets multiplexed pin to TIOC0A output
Sets ch0 timer counter operation/disabling
Main routine
Specifies TGR0A compare-match as counter clear
source, and ø as input clock
T0.TIOR0H
Initial TIOC0A output = 0; output toggled on compare-
match
T0.TGR0A
T0.TMDR0
1/2 output pulse cycle setting
Sets ch0 to normal mode
4. RAM Used
This application example does not use any RAM apart from the arguments.
Note: The SH7040 header file name is used as the register label.
14 HITACHI
Flowchart
1. Main routine
puls_out
Set TIOC0A to output
with PFCE.PECR2
Set counter clear source
with T0.TCR0
Set compare-match 0A toggle output
with T0.TIOR0H
Set 1/2 pulse cycle in T0.TGR0A
Set normal operation mode
with T0.TMDR0
Enable ch0 count operation
with TMRSH.TSTR
HITACHI 15
Program List
/*-----------------------------------------------------------*/
/*
INCLUDE FILE
*/
/*-----------------------------------------------------------*/
#include<machine.h>
#include"SH7040.H"
/*-----------------------------------------------------------*/
/*
PROTOTYPE
*/
/*-----------------------------------------------------------*/
void puls_out(void);
/*-----------------------------------------------------------*/
/*
/*-----------------------------------------------------------*/
#define pul_cyc (*(unsigned short *)0xffffe800)
/*-----------------------------------------------------------*/
/* MAIN PROGRAM */
RAM ALLOCATION
*/
/*-----------------------------------------------------------*/
void puls_out(void)
{
PFCE.PEIOR = 0x0001;
PFCE.PECR2 = 0x0001;
/* TIOC0A output */
/* TIOC0A output compare/match output */
T0/TCR0 = 0x20;
T0.TIOR0H = 0x03;
T0.TGR0A = pul_cyc;
T0.TCNT0 = 0x0000;
T0.TMDR0 = 0xc0;
TMRSH.TSTR = 0x01;
while(1);
/* compare/match clear of TGR0A */
/* start' 0' compare/match toggle output */
/* 1/2 sycle */
/* timer start value set */
/* mode set */
/* timer count start */
}
16 HITACHI
2.3 PWM 4-Phase Output
MTU (PWM Mode 1)
Specifications
1. Using MTU PWM mode 1, 4-phase PWM output is performed based on the specified duty
values and cycles.
2. PWM mode 1 allows any cycle to be set for each channel. Two outputs are possible for each of
ch0, ch3, and ch4, and one output for ch1 and ch2. Thus waveforms with different high-level
widths can be generated in the same cycle on ch0, ch3, and ch4.
3. A duty of 0% to 100% can be set, with 1/65535 resolution.
ch1 PWM cycle
ch2 PWM cycle
ch1 PWM cycle
TIOC1A pin
TIOC2A pin
ch2 PWM cycle
ch2 PWM cycle
ch3 PWM cycle
ch3 PWM cycle
TIOC3A pin
TIOC3C pin
Figure 2-3-1 Example of PWM Output
HITACHI 17
Functions Used
1. In this sample task, 4-phase PWM output is performed using MTU ch1 to ch3.
In PWM mode 1, PWM output is generated using the TGRA and TGRB registers as a pair, and
the TGRC and TGRD registers as a pair. Up to 8-phase PWM output is possible by using ch0
to ch4.
a. Figure 2-3-2 shows the MTU block diagram for this sample task.
ch1, 2
(Initial output setting)
Timer general registers
Timer I/O
1A/B, 2A/B
control register 1
(TGR1A/B, TGR2A/B)
(TIOR1)
Compare-match
Pulse output
1A/B
Output compare
signal generator
Comparator A
TIOC1A pin
TIOC2A pin
Timer counters 1, 2
(TCNT1, 2)
ø
ø/4
ø/16
Timer control
registers 1, 2
(TCR1, 2)
(Input clock
selection)
ø/64
(Counter clear source
setting)
ø/256
ø/1024
TCLKA/B/C
ch3
(Initial output setting)
Timer general registers
3A/B/C/D
Timer I/O
control register 3
(TIOR3)
(TGR3A/B/C/D)
Compare-match
3A/B/C/D
Pulse output
Output compare
signal generator
Comparator A
TIOC3A pin
TIOC3C pin
(Counter clear source
setting)
Timer counter 3
(TCNT3)
ø
ø/4
ø/16
Timer control
register 3
(TCR3)
(Input clock
selection)
ø/64
ø/256
ø/1024
TCLKA/B/C
Figure 2-3-2 MTU/ch1, ch2, ch3 Block Diagram
18 HITACHI
2. Table 2-3-1 shows the function assignments for this sample task. MTU functions are assigned
as shown in this table to perform PWM pulse output.
Table 2-3-1 Function Assignment
Pin/Register Name
Function Assignment
TIOC1A
TIOC2A
TIOC3A
TIOC3C
PWM pulse output pins
TCR1
TCR2
TCR3
Select ch1 to ch3 timer counter clear sources and input clocks
Specify ch1 to ch3 operating in PWM mode 1
PWM cycle settings
TMDR1
TMDR2
TMDR3
TGR1A
TGR2A
TGR3A
TGR1B
TGR2B
TGR3B
TGR3C
TGR3D
Duty value settings
HITACHI 19
Operation
Figure 2-3-3 shows the principles of the operation. 4-phase PWM output is performed from the
ch1 to ch3 PWM output pins (TIOC1A, TIOC2A, TIOC3A/C) by means of SH7040 hardware and
software processing as shown in the figure.
Immediately after reset
TCNT1 count value
TGR1A
TGR1B
H'0000
TCNT2 count value
TGR2A
TGR2B
H'0000
TCNT3 count value
TGR3A
TGR3C
TGR3B
TGR3B
H'0000
TIOC1A pin
TIOC2A pin
TIOC3A pin
TIOC3C pin
Hardware processing
None
Hardware processing
Software processing
Change PWM output pin
output level to high on
compare-match generation
1. Pin function controller initialization
• Set TIOC3C, TIOC3A pins to output
• Set TIOC2A, TIOC1A pins to output
2. Timer initialization
• TCR1, 2, 3 setting
• TGR1A/B, TGR2A/B, TGR3A/B/C/D
setting
Hardware processing
Change PWM output pin
output level to low on
compare-match A
Software processing
None
Software processing
None
• TIOR1, 2, 3H/L setting
3. Start count operation
Figure 2-3-3 Principles of PWM Waveform Operation
20 HITACHI
Software
1. Modules
Module Name
Label
Function Assignment
Main routine
pwm_1
PFC and PWM output setting
2. Arguments
Label/
Data
Input/
Register Name Function Assignment
Length Module Output
pul_cyc1
pul_cyc2
pul_cyc3
Setting of timer value corresponding to pulse
cycle
1 word
Main
routine
Input
Pulse cycle is calculated from following formula:
Pulse cycle (ns) = Timer value × ø cycle
(35 ns at 28.7 MHz
operation)
pul_duty1b
pul_duty2b
pul_duty3b
pul_duty3c
pul_duty3d
Setting of timing for change of waveform output
from TIOC pin
HITACHI 21
3. Internal Registers Used
Register Name
Function Assignment
Module
TMRSH.TSTR
Performs start of channel 1, 2, 3, timer count
Main routine
T1.TCR1
T2.TCR2
T3.TCR3
Clear timer counter clear source on TGR1A, TGR2A, TRG3A
compare-match
Select ø as input clock
T1.TGR1A
T1.TGR1B
Channel 1 PWM cycle setting
Setting of timer counter value that causes high-level output from
TIOC1A
T2.TGR2A
T2.TGR2B
Channel 2 PWM cycle setting
Setting of timer counter value that causes high-level output from
TIOC2A
T3.TGR3A
T3.TGR3B
Channel 3 PWM cycle setting
Setting of timer counter value that causes high-level output from
TIOC3A
T3.TGR3C
T3.TGR3D
Setting of timer counter value for low-level output from TIOC3C
Setting of timer counter value that causes high-level output from
TIOC3C
T1.TIOR1
T2.TIOR2
T3.TIOR3H
T3.TIOR3L
Sets 0 initial output and 0 output on output compare for TGR1A,
and 0 initial output and 1 output on output compare for TGR1B
Sets 0 initial output and 0 output on output compare for TGR2A,
and 0 initial output and 1 output on output compare for TGR2B
Sets 0 initial output and 0 output on output compare for TGR3A,
and 0 initial output and 1 output on output compare for TGR3B
Sets 0 initial output and 0 output on output compare for TGR3C,
and 0 initial output and 1 output on output compare for TGR3B
T1.TMDR1
T2.TMDR2
T3.TMDR3
Set operating mode to PWM mode 1
4. RAM Used
This application example does not use any RAM apart from the arguments.
Note: The SH7040 header file name is used as the register label.
22 HITACHI
Flowchart
1. Main routine
pwm_1
Perform TIOC1A, 2A, 3A, 3C output
setting with PFCE.PECR2, 1
Set TCR counter clear sources
in TGR1A, TGR2A, TGR3A
Set pulse cycles in T1.TGR1A,
T2.TGR2A, T3.TGR3A
Set duty values in T1.TGR1B,
T2.TGR2B, T3.TGR3B,
T3.TGR3C, T3.TGR3D
Set waveform output value
with TIOR
Set TMDR1, 2, 3 to PWM mode 1
Enable ch1, ch2, ch3 count
operation with TMRSH.TSTR
HITACHI 23
Program List
/*-------------------------------------------------------------------*/
/*
INCLUDE FILE
*/
/*-------------------------------------------------------------------*/
#include<machine.h>
#include"SH7040.H"
/*-------------------------------------------------------------------*/
/*
PROTOTYPE
*/
/*-------------------------------------------------------------------*/
void pwm_1(void);
/*-------------------------------------------------------------------*/
/*
RAM ALLOCATION
*/
/*-------------------------------------------------------------------*/
#define pul_cyc1
#define pul_duty1b
#define pul_cyc2
#define pul_duty2b
#define pul_cyc3
#define pul_duty3b
#define pul_duty3c
#define pul_duty3d
(*(unsigned short *)0xffffe800)
(*(unsigned short *)0xffffe802)
(*(unsigned short *)0xffffe804)
(*(unsigned short *)0xffffe806)
(*(unsigned short *)0xffffe808)
(*(unsigned short *)0xffffe80a)
(*(unsigned short *)0xffffe80c)
(*(unsigned short *)0xffffe80e)
/*-------------------------------------------------------------------*/
/* MAIN PROGRAM */
/*-------------------------------------------------------------------*/
void pwm_1(void)
{
PFCE.PEIOR = 0x0550;
PFCE.PECR1 = 0x0011;
PFCE.PECR2 = 0x1100;
/* TIOC1A,TIOC2A,TIOC3A/C output */
/* TIOC3A/C output */
/* TIOC1A, TIOC2A output */
T1.TCR1 = 0x20;
T1.TIOR1 = 0x02;
T1.TCNT1 = 0x0000;
T1.TGR1A = pul_cyc1;
T1.TGR1B = pul_duty1b;
T1.TMDR1 = 0xc2;
/* TGR1A compare/match clear */
/* start '0' compare/match '1' output */
/* timer counter '0' set */
/* timer general register set */
/* pwm mode 1 */
T2.TCR2 = 0x20;
T2.TIOR2 = 0x02;
T2.TCNT2 = 0x0000;
T2 TGR2A = pul_cyc2;
T2.TGR2B = pul_duty2b;
T2.TMDR2 = 0xc2;
/* TGR2A compare/match clear */
/* start '0' compare/match '1' output */
/* timer counter '0' set */
/* timer general register set */
/* pwm mode 1 */
T3.TCR3 = 0x20;
T3.TIOR3H = 0x02;
T3.TIOR3L = 0x21;
T31.TCNT3 = 0x0000;
T31.TGR3A = pul_cyc3;
T31/TGR3B = pul_duty3b;
T31.TGR3C = pul_duty3c;
T31.TGR3D = pul_duty3d;
T3.TMDR3 = 0xc2;
/* TGR3A compare/match clear */
/* start '0' compare/match '1' output */
/* start '0' compare/match '1' output */
/* timer counter '0' set */
/* timer general register set */
/* pwm mode 1 */
/* timer start */
TMRSH.TSTR = 0x46;
while(1);
}
24 HITACHI
2.4 PWM 7-Phase Output
MTU (PWM Mode 2)
Specifications
1. The pulse high-level width is varied to generate variable-duty 7-phase PWM output as shown
in figure 2-4-1.
2. At 28.7 MHz operation, any output PWM cycle from 69.9 ns to 2.28 ms can be set.
PWM cycle
TIOC0B pin
TIOC0C pin
TIOC0D pin
TIOC1A pin
TIOC1B pin
TIOC2A pin
TIOC2B pin
Figure 2-4-1 Example of PWM Output
HITACHI 25
Functions Used
1. In this sample task, 7-phase PWM output is performed by synchronous operation of MTU ch0
to ch2.
a. Figure 2-4-2 shows the MTU block diagram for this sample task.
This sample task uses the following MTU functions:
•
A function for automatically outputting pulses by hardware without software
intervention (output compare-match)
•
•
A function that clears the counter in the event of a compare-match (counter clear)
A function that inverts the output each time a compare-match occurs (toggle output)
0. ch0 (master)
(TGR0A compare-match set
as counter clear source)
Synchronous clear
source generation
Timer control
register 0 (TCR0)
Control
logic
(PWM cycle setting)
Timer general register 0A (TGR0A)
Compare-match
Comparator
Clear
Timer counter 0 (TCNT0)
ch1, ch2 (slaves)
(Synchronous clear set for
counter clear source)
Control
logic
Timer control
registers 1, 2 (TCR1, 2)
(ch0 to ch2 set to PWM mode 2)
Timer mode registers
(TMDR0–2)
Timer general registers
(respective duty values set
for TGR0B to TGR2B)
Pulse output
Pulse I/O
control
Compare-match
Comparator
TIOC0B pin
TIOC0C pin
TIOC0D pin
TIOC1A pin
TIOC1B pin
TIOC2A pin
TIOC2B pin
Clear
Timer counters 1, 2
(TCNT1, 2)
Figure 2-4-2 Synchronous Clear Block Diagram
26 HITACHI
2. Table 2-4-1 shows the function assignments for this task. MTU functions are assigned as
shown in this table to perform PWM pulse output.
Table 2-4-1 MTU Function Assignment
Pin/Register Name
Function Assignment
TIOC0B
TIOC0C
TIOC0D
TIOC1A
TIOC1B
TIOC2A
TIOC2B
PWM pulse output pins
TSYR
Synchronous operation of ch0 to ch2
Select ch0 to ch2 timer counter clear sources and input clocks
PWM cycle setting
TCR0 to TCR2
TGR0A
TGR0B
TBR0C
TGR0D
TGR1A
TGR1B
TGR2A
TGR2B
Duty value settings
TMDR0 to TMDR2
Specify ch0 to ch2 operating in PWM mode 2
HITACHI 27
Operation
Figure 2-4-3 shows the principles of the operation. 7-phase PWM output is performed from the
ch0 to ch2 PWM output pins (TIOC0B/C/D, TIOC1A/B, TIOC2A/B) by means of SH7040
hardware and software processing as shown in the figure.
Immediately after reset
TCNT0 count value
TGR0A
TGR0B
TGR0C
TGR0D
H'0000
TCNT1 count value
TGR1A
TGR1B
H'0000
TCNT2 count value
TGR2A
TGR2B
H'0000
TIOC0B pin
TIOC0C pin
TIOC0D pin
TIOC1A pin
TIOC1B pin
TIOC2A pin
TIOC2B pin
Hardware processing
None
Hardware processing
Software processing
Hardware processing
Change PWM output pin
output level to high on
compare-match generation
1. Pin function controller initialization
1. Change PWM output pin
output level to low on TGR0A
compare-match
•
Set TIOC pins to output
2. Timer initialization
•
•
TCR0, 1, 2 setting
TGR0A/B/C/D, TGR1A/B, TGR2A/B
setting
2. Clear ch0 to ch2 timer
counters (synchronous clear)
Software processing
None
Software processing
None
•
TIOR0H/L, TIOR1, 2 setting
3. Start count operation
Figure 2-4-3 Principles of PWM Output (7-Phase) Operation Used for Sawtooth
Waveform Generation
28 HITACHI
Software
1. Modules
Module Name
Label
Function Assignment
Main routine
pwm_2
PFC and PWM output setting
2. Arguments
Label/
Data
Input/
Register Name Function Assignment
Length Module Output
pul_cyc0a
Setting of timer value corresponding to pulse
1 word
Main
Input
cycle
routine
Pulse cycle is calculated from following formula:
Pulse cycle (ns) = Timer value × ø cycle
(35 ns at 28.7 MHz
operation)
pul_duty0b
pul_duty0c
pul_duty0d
pul_duty1b
pul_duty2a
pul_duty2b
Setting of timing for change of waveform output
from TIOC pin
HITACHI 29
3. Internal Registers Used
Register Name
PFCE.PECR2
TMRSH.TSTR
TMRSH.TSYR
Function Assignment
Module
Sets TIOC0B/C/D, TIOC1A/B, TIOC2A/B as output pins
Timer count start execution
Main routine
Sets synchronous operation for timer counters 0 and 1
Clear timer counter clear source on TGR0A compare-match
Select ø as input clock
T0.TCR0
T1.TCR1
T2.TCR2
T0.TGR0A
T0.TGR0B
PWM cycle setting
Setting of timer counter value that causes high-level output from
TIOC0B
T0.TGR0C
T0.TGR0D
T1.TGR1A
T1.TGR1B
T2.TGR2A
T1.TGR2B
T0.TIOR0H
T0.TIOR0L
T1.TIOR1
T1.TIOR2
Setting of timer counter value that causes high-level output from
TIOC0C
Setting of timer counter value that causes high-level output from
TIOC0D
Setting of timer counter value that causes high-level output from
TIOC1A
Setting of timer counter value that causes high-level output from
TIOC1B
Setting of timer counter value that causes high-level output from
TIOC2A
Setting of timer counter value that causes high-level output from
TIOC2B
Sets 0 initial output and 0 output on output compare for TGR0A,
and 0 initial output and 1 output on output compare for TGR0B
Sets 0 initial output and 1 output on output compare for TGR0C,
and 0 initial output and 1 output on output compare for TGR0D
Sets 0 initial output and 1 output on output compare for TGR1A,
and 0 initial output and 1 output on output compare for TGR1B
Sets 0 initial output and 1 output on output compare for TGR1A,
and 0 initial output and 1 output on output compare for TGR1B
T0.TMDR0
T1.TMDR1
T2.TMDR2
Set operating mode for each channel to PWM mode 2
4. RAM Used
This application example does not use any RAM apart from the arguments.
Note: The SH7040 header file name is used as the register label.
30 HITACHI
Flowchart
Main routine
pwm_2
Set TIOC0B/C/D, TIOC1A/B, TIOC2A/B
to output with PFCE.PECR2
Set counter clear source to TGR0A
with T0.TCR0, and set synchronous
clear for T1.TCR1, T2.TCR2
Set pulse cycle in T0.TGR0A
Set duty values in T0.TGR0B/C/D,
T1.TGR1A/B, T2.TGR2/B
Set waveform output value
with TIOR
Set TMDR0, 1, 2 to PWM mode 2
Enable ch0, ch1, ch2 count
operation with TMRSH.TSTR
HITACHI 31
Program List
/*-------------------------------------------------------------------*/
/*
INCLUDE FILE
*/
/*-------------------------------------------------------------------*/
#include<machine.h>
#include"SH7040.H"
/*-------------------------------------------------------------------*/
/*
PROTOTYPE
*/
/*-------------------------------------------------------------------*/
void pwm_2(void);
/*-------------------------------------------------------------------*/
/*
RAM ALLOCATION
*/
/*-------------------------------------------------------------------*/
#define pul_cyc0
(*(unsigned short *)0xffffe800)
(*(unsigned short *)0xffffe802)
(*(unsigned short *)0xffffe804)
(*(unsigned short *)0xffffe806)
(*(unsigned short *)0xffffe808)
(*(unsigned short *)0xffffe80a)
(*(unsigned short *)0xffffe80c)
(*(unsigned short *)0xffffe80e)
#define pul_duty0b
#define pul_duty0c
#define pul_duty0d
#define pul_duty1a
#define pul_duty1b
#define pul_duty2a
#define pul_duty2b
/*-------------------------------------------------------------------*/
/* MAIN PROGRAM */
/*-------------------------------------------------------------------*/
void pwm_2(void)
{
PFCE.PEIOR = 0x00fe;
PFCE.PECR2 = 0x5554;
/* TIOC0B/C/D,TIOC1A/B,TIOC2A/B output */
/* TIOC0B/C/D,TIOC1A/B,TIOC2A/B output */
T0.TCR0 = 0x20;
T0.TIOR0H = 0x20;
T0.TIOR0L = 0x22;
T0.TCNT0 = 0x0000;
T0.TGR0A = pul_cyc0;
T0.TGR0B = pul_duty0b;
T0.TGR0C = pul_duty0c;
T0.TGR0D = pul_duty0d;
T0.TMDR0 = 0xc3;
/* TGR0A compare/match clear */
/* start '0' compare/match '1' output */
/* start '0' compare/match '1' output */
/* timer counter '0' set */
/* timer general register set */
/* pwm mode 2 */
T1.TCR1 = 0x60;
T1.TIOR1 = 0x22;
T1.TCNT1 = 0x0000;
T1.TGR1A = pul_duty1a;
T1.TGR1B = pul_duty1b;
T1.TMDR1 = 0xc3;
/* TGR0A compare/match clear */
/* start '0' compare/match '1' output */
/* timer counter '0' set */
/* timer general register set *1
/* pwm mode 2 *1
T2.TCR2 = 0x60;
T2.TIOR2 = 0x22;
T2.TCNT2 = 0x0000;
T2.TGR2A = pul_duty2a;
T2.TGR2B = pul_duty2b;
T2.TMDR2 = 0xc3;
/* TGR0A compare/match clear */
/* start '0' compare/match '1' output */
/* timer counter '0' set */
/* timer general register set */
/* pwm mode 2 */
TMRSH.TSYR = 0x07;
TMRSH.TSTR = 0x07;
while(1);
/* ch0,1,2 synchronize */
/* timer start */
}
32 HITACHI
2.5 Positive-Phase and Opposite-Phase
PWM 3-Phase Output
MTU (Reset-Synchronized
PWM Mode)
Specifications
1. The pulse high-level width is varied to generate positive-phase and opposite-phase 3-phase
output of variable-duty pulses (duty pulses) as shown in figure 2-5-1.
2. At 28.7 MHz operation, any output pulse cycle from 34.8 ns to 2.28 ms can be set.
Pulse cycle
Pulse high-level
width
Pulse low-level width
TIOC3B pin
TIOC3D pin
Pulse high-level width
Pulse low-level width
TIOC4A pin
TIOC4C pin
Pulse high-level width
Pulse low-level
width
TIOC4B pin
TIOC4D pin
Pulse high-level width
× 100 (%)
Duty =
pulse cycle
Figure 2-5-1 Example of Positive-Phase and Opposite-Phase PWM 3-Phase
Output Waveform
HITACHI 33
Functions Used
1. In this sample task, 3-phase output is performed of PWM waveforms with a positive-
phase/opposite-phase relationship and a common turning point, using MTU ch3 and ch4 in
combination.
In reset-synchronized PWM mode, PWM output is generated using the TGRA and TGRC
registers as a pair, and the TGRB and TGRD registers as a pair.
a. Figure 2-5-2 shows the MTU block diagram for this sample task.
Synchronous setting
ø
ø/4
ø/16
ø/64
Timer
general
register 4A
(TGR4A)
Timer
general
register 3A
(TGR3A)
Clock
selection
circuit
(Reset-synchronized
PWM mode setting)
ø/256
ø/1024
TCLKA/B
Timer mode register 3
(TMDR3)
Compare-
match A
Comparator A
Timer control
register 3 (TCR3)
(Compare-match A
clear specification)
Pulse output
TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4B pin
TIOC4C pin
TIOC4D pin
Timer counter
(TCNT3)
Output control
Counter clear
signal
generator
Comparator B
Compare-
match B
Timer general
registers B
(TGR3B, TGR4B)
Timer start register
(TSTR)
(Count operation enabling)
Figure 2-5-2 MTU/ch3, ch4 Block Diagram
34 HITACHI
2. Table 2-5-1 shows the function assignments for this task. MTU functions are assigned as
shown in this table to perform PWM output.
Table 2-5-1 Function Assignment
Pin/Register Name
TIOC3B
Function Assignment
PWM output 1
TIOC3D
TIOC4A
PWM output 1 opposite-phase waveform
PWM output 2
TIOC4B
PWM output 3
TIOC4C
TIOC4D
TCR3
PWM output 2 opposite-phase waveform
PWM output 3 opposite-phase waveform
Selects ch3 timer counter clear source and input clock
Specifies ch3 operating in reset-synchronized PWM mode
PWM cycle setting
TMDR3
TGR3A
TGR3B
TGR4A
TGR4B
Duty value settings
HITACHI 35
Operation
Figure 2-5-3 shows the principles of the operation. 6-phase PWM waveforms are output from the
PWM output pins (TIOC3B/D, TIOC4A/B/C/D) by means of SH7040 hardware and software
processing as shown in the figure.
Immediately after reset
TCNT3 count value
TGR3A
TGR3B
TGR4A
TGR4B
H'0000
TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
Hardware processing
None
Software processing
1. Pin function controller initialization
•
Set TIOC3B/D, TIOC4A/B/C/D as output pins
Hardware processing
2. Timer initialization
•
•
•
•
•
TCR3 setting
TOCR setting
TGR setting
TOER setting
TMDR setting
Toggle output each time TGR3B,
TGR4A, or TGR4B compare-match
or timer counter clear occurs
Software processing
None
3. Start timer counter
Figure 2-5-3 Principles of Reset-Synchronized PWM Waveform Output Operation
36 HITACHI
Software
1. Modules
Module Name
Label
Function Assignment
Main routine
rst_pwm
PFC and PWM output setting
2. Arguments
Label/
Data
Input/
Register Name Function Assignment
Length Module Output
pul_cyc1
Setting of timer value corresponding to pulse
1 word
Main
Input
cycle
routine
Pulse cycle is calculated from following formula:
Pulse cycle (ns) = Timer value × ø cycle
(35 ns at 28.7 MHz
operation)
pul_duty3b
pul_duty4a
pul_duty4b
Setting of timing for change of waveform output
from TIOC pin
3. Internal Registers Used
Register Name
RFCE.PECR1
TMRSH.TSTR
T3.TCR3
Function Assignment
Module
Main routine
Sets TIOC3B/D, TIOC4A/B/C/D as output pins
ch3 timer count start execution
Clears timer counter clear source on TGR3A compare-match
Selects ø as input clock
T3.TOCR
Enabling of toggle output synchronized with PWM cycle, and
positive-phase and opposite-phase output level setting
T31.TGR3A
T31.TGR3B
PWM cycle setting
Setting of timer counter value that causes toggle output from
TIOC3B/D
T31.TGR4A
T31.TGR4B
Setting of timer counter value that causes high-level output
from TIOC4A/C
Setting of timer counter value that causes high-level output
from TIOC4B/D
T3.TOER
Reset-synchronized PWM output enable setting
Reset-synchronized PWM mode setting
T3.TMDR3
HITACHI 37
4. RAM Used
This application example does not use any RAM apart from the arguments.
Note: The SH7040 header file name is used as the register label.
38 HITACHI
Flowchart
1. Main routine
rst_pwm
Set TIOC3B/D, TIOC4A/B/C/D pins to
output with PFCE.PECR1
Set counter clear source to
TGR3A with TCR
Set enabling of toggle output
synchronized with PWM cycle,
and positive-phase and opposite-phase
output levels, with T3.TOCR
Set pulse cycle in T31.TGR3A
Set duty values in T31.TGR3B,
T3.TGR4A/B
Enable reset-synchronized PWM
output with T3.TOER
Set reset-synchronized PWM mode
with T3.TMDR3
Enable ch3 count operation
with TMRSH.TSTR
HITACHI 39
Program List
/*-------------------------------------------------------------------*/
/*
INCLUDE FILE
*/
/*-------------------------------------------------------------------*/
#include<machine.h>
#include"SH7040.H"
/*-------------------------------------------------------------------*/
/*
PROTOTYPE
*/
/*-------------------------------------------------------------------*/
void rst_pwm(void);
/*-------------------------------------------------------------------*/
/*
RAM ALLOCATION
*/
/*-------------------------------------------------------------------*/
#define pul_cyc1
#define pul_duty3b
#define pul_duty4a
#define pul_duty4b
(*(unsigned short *)0xffffe800)
(*(unsigned short *)0xffffe802)
(*(unsigned short *)0xffffe804)
(*(unsigned short *)0xffffe806)
/*-------------------------------------------------------------------*/
/* MAIN PROGRAM */
/*-------------------------------------------------------------------*/
void rst_pwm(void)
{
PFCE.PEIOR = 0xfa00;
PFCE.PECR1 = 0x5545;
/* TIOC3B/D,TIOC4A/B/C/D output */
/* TIOC3B/D,TIOC4A/B/C/D output */
T3.TCR3 = 0x20;
/* TGR3A compare/match/clear */
/* timer counter '0' set */
/* timer general register set */
T31.TCNT3 = 0x0000;
T31.TGR3A =pul_cyc1;
T31.TGR3B =pul_duty3b;
T31.TCNT4 = 0x0000;
/* timer counter '0' set */
T31.TGR4A = pul_duty4a; /* timer general register set */
T31.TGR4B = pul_duty4b;
T3.TOER = 0xff;
T3.TOCR = 0x43;
T3.TMDR3 = 0xc8;
TMRSH.TSTR = 0x40;
while(1);
/* timer output enable register */
/* timer output control register */
/* reset-synchronized pwm mode */
/* timer start */
}
40 HITACHI
2.6 Complementary PWM 3-Phase Output
MTU (Complementary
PWM Mode)
Specifications
1. 3-phase output of PWM waveforms with non-overlapping of the positive phase and opposite
phase is performed as shown in figure 2-6-1.
2. The duty can be varied arbitrarily from 0% to 100% by a setting in RAM.
High-level pulse width
Duty =
× 100 (%)
pulse cycle
3. Toggle waveform output is performed in synchronization with the cycle.
4. At 28.7 MHz operation, any output pulse cycle from 69.6 ns to 2.28 ms can be set.
Cycle
TIOC3A pin
Non-overlap time
TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
Figure 2-6-1 Complementary PWM 3-Phase Output Waveform
HITACHI 41
Functions Used
1. In this sample task, 3-phase output is performed of PWM waveforms with non-overlapping of
the positive phase and opposite phase, using MTU ch3 and ch4 in combination. Toggle
waveform output is also performed, synchronized with the PWM waveform cycle.
a. Figure 2-6-2 shows the MTU/ch3, ch4 block diagram for this sample task. This task uses
the following functions:
•
•
•
A function to generate 3-phase PWM waveform output with non-overlapping of
positive and opposite phases (complementary PWM mode)
A function to transfer buffer register (TGR3C/D, TGR4C/D) contents to a compare
register (TGR3A/B, TGR4A/B) when a compare-match occurs
A function to output a toggle waveform synchronized with the PWM waveform cycle
ø
ø/4
ø/16
ø/64
ø/256
ø/1024
TCLKA
TCLKB
Timer output
master enable
register (TOER)
Timer mode
register 3
(TMDR3)
Timer output
control register
(TOCR)
Timer control
register 3 (TCR3)
Pulse output
TIOC3A pin
TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
Clock selection
Timer counters 3, 4
(TCNT3, 4)
Output control
circuit
Compare-match
signal
Comparator
Timer general
registers 3B, 4A/B
(TGR3B, TGR4A/B)
Dead time
register
(TDDR)
Timer general
register 3A
(TGR3A)
Timer subcounter
(TCNTS)
When TGR4B is set
Timer general registers
3B, 4A/B
(TGR3B, TGR4A/B)
PWM carrier
cycle register
(TCDR)
Timer general
register 3C
(TGR3C)
Dead time
register
(TDDR)
Figure 2-6-2 MTU/ch3, ch4 Block Diagram
2. Table 2-6-1 shows the function assignments for this task. MTU functions are assigned as
42 HITACHI
shown in this table to perform PWM pulse output.
Table 2-6-1 Function Assignment
Pin/Register Name
TIOC3A
Function Assignment
Toggle output synchronized with PWM
PWM output 1
TIOC3C
TIOC3D
Opposite-phase waveform in non-overlapping relationship with PWM
output 1
TIOC4A
TIOC4B
TIOC4C
PWM output 2
PWM output 3
Opposite-phase waveform in non-overlapping relationship with PWM
output 2
TIOC4D
Opposite-phase waveform in non-overlapping relationship with PWM
output 3
TOCR
TOER
Enabling/disabling of toggle output synchronized with PWM cycle
Enabling/disabling of complementary PWM output pin signal output
Selects ch3 timer counter clear source and input clock
Specifies ch3, ch4 operating in complementary PWM mode
Setting of 1/2 PWM cycle + dead time value
TCR3
TMDR3
TGR3A
TGR3C
TGR3B
TGR4A
TGR4B
TGR4C
TGR4D
TDDR
TGR3A buffer register
Output pulse turning point setting (compare register)
TGR4A buffer register
TGR4B buffer register
Dead time setting
TCDR
1/2 cycle setting
TCBR
TCDR buffer register
HITACHI 43
Figure 2-6-3 shows the principles of the operation. Complementary PWM waveform output is
performed by means of SH7040 hardware and software processing.
Immediately after reset
TGR3A
TCDR
TCNTS
TCNT3
TCNT4
TGR4B
TDDR
H'0000
TIOC4B pin
TIOC4D pin
Hardware processing
1. When TMDR is set, transfer value
from buffer register to compare
register
Hardware processing
1. Compare-match generation
2. Pulse output
Software processing
Initialization
Software processing
None
1. Set same counter clock for ch3, ch4
2. PWM output level setting
3. Set non-overlap period in TCNT3
4. Set cycle with TGR3A, waveform
change timing with TGR4B
5. Buffer register setting
6. Set non-overlap period with TDDR
7. Set TCNT4 upper limit with TCBR,
TCDR
Hardware processing
1. TCNTS operation
Hardware processing
1. Halt TCNTS
8. Enable TIOC4B/D pin output
9. Set complementary PWM mode
10. Start count operation
Software processing
None
Software processing
None
Figure 2-6-3 Principles of Complementary PWM Single-Phase Waveform
Output Operation
44 HITACHI
Figure 2-6-4 shows the PWM waveform output method. When complementary PWM mode is set,
the following rules apply to data transfer and compare operations.
Data Transfer
•
•
In period Ta, data written in the buffer register is transferred to a temporary register (at the
point at which data is set in TGR4D).
In period Tb1, when transfer mode is set as transfer at the crest, data is not transferred from the
buffer register to the temporary register. In period Tb2, the same operation is performed as in
period Ta.
Similarly, in the case of trough setting, data is not transferred in period Tb2.
Data transfer to the buffer register can be performed as desired.
•
Compare
•
In period Tb, the temporary register and compare register are compared with the TCNT3,
TCNT4, and TCNTS counters to control the PWM waveform.
•
•
In area (a), a compare-match of the pre-change data with (3) or (4) has priority.
In area (b), a compare-match of the post-change data with (1) or (2) has priority.
However, generation of a compare-match at which the output waveform is set to the active level
(compare-match (1) or (3)) occurs only after the generation of a compare at which the respective
output waveform is set to the positive level (compare-match (4) or (2)).
Tb1
Ta
Tb2
Ta
Tb1
TGR3A
TCDR
(3) (4)
(1) (2)
TDDR
H'0000
Area (a)
Area (b)
Figure 2-6-4 Principles of Operation of PWM Waveform Output Method
HITACHI 45
Figure 2-6-5 shows the principles of the operation. Complementary PWM waveform output is
performed by means of SH7040 hardware and software processing. The transfer mode in which
data is changed at the trough is selected.
Immediately after reset
Ta
Tb1
Ta
Tb2
TGR3A
TCDR
TCNT3
TCNT4
TCNTS
TGR4B
TDDR
H'0000
TIOC4B pin
TIOC4D pin
Buffer register TGR4D
A
A
B
B
Temporary register TMP3
Compare register TGR4B
Undefined
Undefined
A
B
Hardware processing
*
1. When TMDR is set, transfer value from
buffer register to compare register
Hardware processing
1. Transfer data from buffer register
to temporary register
Software processing
Initialization
Software processing
1. Set data in TGR4D
1. Set same counter clock for ch3, ch4
2. PWM output level setting
3. Set non-overlap period in TCNT3
4. Set cycle with TGR3A, waveform change
timing with TGR4B
5. Buffer register setting
6. Set non-overlap period with TDDR
7. Set TCNT4 upper limit with TCBR, TCDR
8. Enable TIOC4B/D pin output
9. Set complementary PWM mode
10. Start count operation
Hardware processing
1. Transfer data from buffer register
to compare register
Software processing
None
Note: * This processing also occurs with 3-phase output when data is set in TGR4D.
Figure 2-6-5 Principles of Complementary PWM Single-Phase Waveform
Output Operation
46 HITACHI
Operation
Figure 2-6-6 shows the principles of the operation. 6-phase PWM output from the ch3 and ch4
PWM output pins (TIOC3B/D, TIOC4A/B/C/D) is performed by means of SH7040 hardware and
software processing.
Immediately after reset
TCNT1 count value
TGR3A
TCDR
TGR3B
TCNTS
TCNT3
TCNT4
TGR4A
TGR4B
TDDR
H'0000
TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
Hardware processing
None
Software processing
Hardware processing
Initialization
TGR3A compare-match interrupt
generation
1. Set same counter clock for ch3, ch4
2. Set waveform output synchronized with PWM cycle
3. PWM output level setting
Software processing
1. Set RAM contents in buffer
register
4. Set non-overlap period in TCNT3
5. Set cycle with TGR3A, waveform change
timing with TGR3B, TGR4A/B
6. Buffer register setting
7. Set non-overlap period with TDDR
8. Set TCNT4 upper limit with TCBR, TCDR
9. Enable TIOC3A/B/D, TIOC4A/B/C/D pin output
10. Set complementary PWM mode
11. Start count operation
Figure 2-6-6 Principles of PWM Waveform Output Operation
HITACHI 47
Figure 2-6-7 shows the principles of the operation. Toggle output synchronized with the PWM
cycle is performed by means of SH7040 hardware and software processing.
Immediately after reset
TGR3A
TCDR
TCNT3
TCNTS
TGR4B
TCNT4
TDDR
H'0000
TIOC3A pin
TIOC4B pin
TIOC4D pin
Hardware processing
Hardware processing
Hardware processing
1. When TMDR is set, transfer value
from buffer register to compare
register
TGR3A compare-match
generation
1. Toggle output of
PWM waveform
synchronized with
cycle
ch4 underflow generation
1. Toggle output of
PWM waveform
synchronized with
cycle
Software processing
Initialization
Software processing
None
1. Set same counter clock for ch3, ch4
2. Set waveform output synchronized
with PWM cycle
Software processing
None
3. PWM output level setting
4. Set non-overlap period in TCNT3
5. Set cycle with TGR3A, waveform
change timing with TGR4B
6. Buffer register setting
7. Set non-overlap period with TDDR
8. Set TCNT4 upper limit with TCBR,
TCDR
9. Enable TIOC4B/D pin output
10. Set complementary PWM mode
11. Start count operation
Figure 2-6-7 Principles of Toggle Waveform Output Operation Synchronized
with PWM Cycle
48 HITACHI
Software
1. Modules
Module Name
Main routine
Data setting
Label
Function Assignment
comple
setdata
Complementary PWM output setting
Sets waveform change timing in buffer register
2. Arguments
Label/
Data
Input/
Register Name Function Assignment
Length Module Output
pul_cyc1
Setting of 1/2 pulse cycle + dead time value
1 word
Main
Input
routine
Pulse cycle is calculated from following formula:
Pulse cycle (ns) = Timer value × ø cycle
(35 ns at 28.7 MHz
operation)
pul_duty3d
pul_duty4c
Setting of timing for change of waveform output
from TIOC pin
pul_duty4d
c_cyc
PWM carrier cycle register value setting
Non-overlap period setting
dead_time
Main
routine
Data
setting
HITACHI 49
3. Internal Registers Used
Register Name
PFCE.PEIOR
PFCE.PECR1
TMRSH.TSTR
T3.TCR3
Function Assignment
Module
Sets TIOC3B/D, TIOC4A/B/C/D pins to output
Sets TIOC3B/D, TIOC4A/B/C/D pins to MTU output
Timer count start execution
Main routine
Selects timer counter clear source and input clock
Enables TGR3A interrupt
T3.TIER3
T31.TGR3A
T31.TGR3B
Setting of 1/2 carrier cycle + dead time register value
Setting of timer counter value that causes output from
TIOC3B, TIOC3D
T31.TGR3C
T31.TGR3D
T31.TCNT3
T31.TGR4A
T31.TGR3A buffer register
T31.TGR3B buffer register
Dead time value setting
Main routine
Data setting
Main routine
Setting of timer counter value that causes output from
TIOC4A, TIOC4C
T31.TGR4B
Setting of timer counter value that causes output from
TIOC4B, TIOC4D
T31.TGR4A
T31.TGR4B
T31.TDDR
T31.TCDR
T31.TCBR
T31.TGR4A buffer register
T31.TGR4B buffer register
Dead time value setting
Setting of 1/2 cycle value
T31.TCDR buffer register
Main routine
Data setting
Main routine
Main routine
Data setting
T3.TOCR
Enabling of toggle output synchronized with PWM cycle, and Main routine
positive-phase and opposite-phase output level setting
T3.TOER
Complementary PWM output enable setting
Set complementary PWM mode
T3.TMDR3
INTC.IPRE
Sets TGI0A compare-match interrupt priority level to 15
4. RAM Used
This application example does not use any RAM apart from the arguments.
Note: The SH7040 header file name is used as the register label.
50 HITACHI
Flowchart
1. Main routine
comple
Set TIOC3B/D, TIOC4A/B/C/D
as MTU output pins
with PFCE.PECR1, PFCE.PEIOR
Set counter clear source disabled
with T3.TCR3, 4
Set 1/2 cycle + non-overlap value
in T31.TGR3A/C
Set duty value in T31.TGR3D,
T31.TGR4C/D
Set dead time value in TCNT3
Set dead time value in T31.TDDR
and 1/2 cycle value in T31.TCDR
and T31.TCBR
Set enabling of toggle output
synchronized with PWM cycle,
and positive-phase and opposite-phase
output levels, with T3.TOCR
Enable complementary PWM
output in TOER
Set complementary PWM mode
with T3.TMDR3
Enable TGI3A interrupt with T3.TIER3
Set TGI0A interrupt priority level to 15
with INTC.IPRE
Enable ch3, ch4 count operation
with TMRSH.TSTR
HITACHI 51
Program List
/*-------------------------------------------------------------------*/
/*
INCLUDE FILE
*/
/*-------------------------------------------------------------------*/
#include<machine.h>
#include"SH7040.H"
/*-------------------------------------------------------------------*/
/*
PROTOTYPE
*/
/*-------------------------------------------------------------------*/
void comple(void);
#pragma interrupt(setdata)
/*-------------------------------------------------------------------*/
/*
RAM ALLOCATION
*/
/*-------------------------------------------------------------------*/
#define pul_cyc1
#define pul_duty3d
#define pul_duty4c
#define pul_duty4d
#define c_cyc
(*(unsigned short *)0xffffe800)
(*(unsigned short *)0xffffe802)
(*(unsigned short *)0xffffe804)
(*(unsigned short *)0xffffe806)
(*(unsigned short *)0xffffe808)
(*(unsigned short *)0xffffe80a)
#define dead_time
/*-------------------------------------------------------------------*/
/* MAIN PROGRAM */
/*-------------------------------------------------------------------*/
void comple(void)
{
PFCE.PEIOR = 0xfb00;
PFCE.PECR1 = 0x5545;
/* TIOC3B/D,TIOC4A/B/C/D output */
/* TIOC3B/D,TIOC4A/B/C/D output */
T3.TCR3 = 0x00;
T31.TGR3C = pul_cyc1;
/* not clear */
/* TGR3A buffer register */
T31.TGR3D = pul_duty3d; /* TGR3D buffer register */
T31.TCNT3 = dead_time;
/* dead time set */
T3.TCR4 = 0x00;
/* don't clear */
T31.TGR4C = pul_duty4c; /* TGR4A buffer register */
T31.TGR4D = pul_duty4d; /* TGR4B buffer register */
T31.TCNT4 = 0x0000;
T31.TDDR = dead_time;
T31.TCBR = c_cyc;
/* timer '0' set */
/* dead time register */
/* TCDR buffer register */
T3.TOCR = 0x43;
T3.TOER = 0xff;
T3.TMDR3 = 0xff;
T3.TIER3 = 0x01;
INTC.IPRE = 0x00f0;
set_imask(0x0);
TMRSH.TSTR = 0xc0;
while(1);
/* timer output control register */
/* timer output enable register */
/* coplementary-pwm mode */
/* timer interrupt enable register */
/* set initialize level=15 */
/* set imask level=0 */
/* timer start */
}
void setdata()
{
T31.TSR3 &= 0xfe;
/* clear flag */
T31.TCBR = c_cyc;
T31.TGR3C = pul_cyc1;
T31.TGR3D = pul_duty3d;
T31.TGR4C = pul_duty4c;
T31.TGR4D = pul_duty4d;
}
52 HITACHI
2.7 2-Phase Encoder Count
MTU (Phase Counting Mode)
Specifications
1. Two external clocks are input to ch1, and the counter is incremented or decremented according
to the phase difference of the pulses, as shown in figure 2-7-1. The ch1 count value is
measured in synchronization with the measurement times (measurement time 1/2) set for ch0,
and the result is stored in RAM.
2. The initial value of the timer counter is H'0000, and counting can be performed from
–2147483648 to 2147483647 using a software counter.
Measurement time 1
TCNT0
Measurement time 2
TCNT1
Counting up
Counting down
TCLKA pin
TCLKB pin
External
clock
input
Figure 2-7-1 2-Phase Encoder Counter Latching
HITACHI 53
Functions Used
1. In this sample task, MTU ch1 is used as an up/down-counter, and the measurement times are
set in TGR0A/B. The TCNT1 value in a control cycle is latched by ch1 input capture with
TGR0A/B output compare as the trigger. The ch1 counter input clock width is latched using
ch0 input capture.
a. Figure 2-7-2 shows the ch0 block diagram. Ch0 outputs a ch1 input capture trigger each
measurement interval, using the following functions. Ch1 measures the TCNT1 value on
input of the input capture signal.
•
•
A function for automatically outputting pulses by hardware without software
intervention (output compare)
A function for detecting pulse input edges and latching the timer value in an internal
register (input capture)
ch0
(Counter clear source
setting)
General register
0A (TGR0A)
Timer control
register 0 (TCR0)
Compare-match 0A (TGI0A)
Compare-match 0C (TGI0C)
Comparator A
ø
ø/2
ø/4
Clock
selection
Timer counter 0
(TCNT0)
MTU/ch1
circuit
ø/8
Comparator C
General register 0C
(TGR0C)
Timer I/O control register
Timer control register 0
0H (TIOR0H)
(TCR0)
(Detected edge specification)
(Input capture clear specification)
Input capture trigger
Edge detection and
capture signal
generation circuit
General register 0B
(TGR0B)
Timer counter 0
(TCNT0)
Figure 2-7-2 MTU/ch0 Block Diagram
54 HITACHI
b. Figure 2-7-3 shows the ch1 block diagram. In ch1 the timer counter is
incremented/decremented using the following functions. The counter value at the time an
input capture rising edge is detected is taken as the measurement result.
•
•
A function for detecting the phase difference between two external clocks, and
incrementing/decrementing the timer counter (phase counting mode)
A function for detecting pulse input edges and latching the timer value at that time in an
internal register (input capture)
•
•
•
A function that initiates interrupt handling when input capture is generated
A function that clears the timer counter when a pulse input edge is detected
A function that initiates interrupt handling on detection of timer counter overflow or
underflow
ch1
Compare-match
0A/C (TGI0A/C)
Input capture interrupt A/B
(TIOC1A/B)
Edge detection
and capture signal
generation circuit
(Phase counting
mode setting)
(Detected edge
specification)
Timer mode
register 1
(TMDR1)
Timer I/O
control register 1
(TIOR1)
MTU
ch0
Overflow/underflow
interrupt
(TCIU1, TCIV1)
Timer general
register 1A
(TGR1A)
Overflow/underflow
signal generator
Timer counter 1
(TCNT1)
Timer general
register 1B
(TGR1B)
Clock
selection
circuit
TCLKA pin
TCLKB pin
Figure 2-7-3 MTU/ch1 Block Diagram
HITACHI 55
2. Table 2-7-1 shows the function assignments for this sample task. MTU functions are assigned
as shown in this table to detect the phase difference between two 2-phase encoder pulses, and
incrementing/decrementing the counter.
Table 2-7-1 Function Assignment
Pin/Register Name
TCLKA
Function Assignment
External clock input pins
TCLKB
TSTR
Enabling/disabling of ch0, ch1 timer counter operation
Counter clock and counter clear source selection
TCR0
TIOR0H
Sets TIOC0A to output compare. Sets TIOC0B to input capture on
generation of ch0 output compare.
TIOR0L
TGR0A
TGR0B
TGR0C
TMDR1
TCR1
Sets TIOC0C to output compare
Measurement time 1 setting
Holds input capture B count result
Set to 2 every measurement interval
Phase counting mode setting
Counter clock and counter clear source selection
Sets TIOC0A/C to input capture on generation of ch1 output compare
Enables TGI1A/B, TIOU1, TIOV1 interrupts
Holds input capture A count result
TIOR0
TIER1
TGR1A
TGR1B
56 HITACHI
Operation
Figure 2-7-4 shows the principles of the operation. The counter is incremented/decremented by
means of SH7040 hardware and software processing.
Immediately
after reset
TCNT1
counter value
H'FFFF
H'05
H'04
H'03
H'02
H'01
H'00
Time
TCLKB
TCLKA
Hardware processing
None
Hardware processing
Hardware processing
Hardware processing
1. TCNT1
1. TCNT1
1. TIOU1
incrementing
decrementing
generation
Software processing
Software processing
None
Software processing
None
Software processing
Initialization
1. Set phase counting
mode
TIOU1 handling
1. Software
2. Start count operation
down-count due
to underflow
Figure 2-7-4 Principles of Phase Counting Mode Operation (1)
HITACHI 57
Interrupt handling is executed by means of SH7040 hardware and software processing in the case
of counter overflow/underflow or external event occurrence, as shown in figure 2-7-5.
Immediately
after reset
TCNT0
counter value
H'FFFF
H'8004
H'8003
H'8002
H'8001
H'8000
H'7FFF
H'7FFE
H'7FFD
H'7FFC
H'7FFB
H'0000
Time
Output
compare signal
(MTU/ch0)
TCLKB
TCLKA
Hardware processing
None
Hardware processing
1. TGI1A generation
2. TGI1B generation
Software processing
Software processing
Initialization
1. Set ø as counter clock
TGI1A/B handling
2. Set input capture signal to ch0 output
compare
1. Store count result in RAM
3. Set TGR0A/B every measurement interval
4. Set phase counting mode
5. Set input capture signal to ch1 output
compare
6. Enable input capture A, input capture B,
and overflow/underflow interrupts
7. Enable count operation
Figure 2-7-5 Principles of Phase Counting Mode Operation (2)
58 HITACHI
Software
1. Modules
Module Name
Label
en2
Function Assignment
Main routine
Initialization of MTU, etc.
Counter value
measurement 1
phacnt1
Initiated by TGI1A; sets up/down-count result in RAM
from TGRA value
Sets counter cycle result in RAM from TGRC value
Counter value
measurement 2
phacnt2
Initiated by TGI1B; sets up/down-count result in RAM
from TGRB value
Overflow
ovf1
unf1
Initiated by TIOV1; increments software counter
Initiated by TIOU1; decrements software counter
Underflow
2. Arguments
Label/
Data
Input/
Register Name Function Assignment
Length
Module
Output
msr_tim1
msr_tim2
Setting of timer value corresponding to Word
counter measurement time
Main routine
Input
Measurement time is found from
following formula:
Measurement time (ns)
= Timer value × ø cycle (35 ns
at 28.7 MHz operation)
cnt–data1
cnt_data2
Setting of up/down-count result
Longword Counter value
measurement 1
Output
Counter value
measurement 2
p_cycle
Setting of count cycle result
Word
Counter value
measurement 1
HITACHI 59
3. Internal Registers Used
Register Name
TMRSH.TSRT
T0.TCR0
Function Assignment
Module
Enabling/disabling of ch0/1 timer counter operation
Counter clock and counter clear source selection
Main routine
T0.TIOR0H
Sets TIOC0A to output compare. Sets TIOC0B to input
capture on generation of ch0 output compare.
T0.TIOR0L
T0.TGR0A
T0.TGR0B
Sets TIOC0C to output compare
Measurement time 1 setting
Holds input capture B count result
Counter value
measurement 1
T0.TGR0C
T1.TMDR1
T1.TCR1
Set to 2 every measurement interval
Phase counting mode setting
Main routine
Counter clock and counter clear source selection
T1.TIOR1
Sets TIOC0A/C to input capture on generation of ch1
output compare
T1.TIER1
Enables TGI1A/B, TIOU1, TIOV1 interrupts
Holds input capture A count result
T1.TGR1A
Counter value
measurement 1
T1.TGR1B
T1.TSR1
Holds input capture B count result
Counter value
measurement 2
TGI1A/B, TIOU1, TIOV1 generation status
Counter value
measurement 1, 2
Overflow, Underflow
4. RAM Used
Module
Label
Function Assignment
Counter value
wrk
Used as work area when setting data
measurement 1, 2
All modules
cnt
Software counter
Note: The SH7040 header file name is used as the register label.
60 HITACHI
Flowchart
1. Main routine
en2
Set ø as TCNT0 input clock
and compare-match A as counter
clear source with T0.TCR0
Set TIOC0A to output compare
operation and TIOC0B to input capture
operation with T0.TIOR0H
Set TIOC0C to input capture
operation with T0.TIOR0L
Set TIOC1A/B to input capture
operation with T1.TIOR1
Set counter measurement times
with T0.TGR0A/C
Enable interrupts with T1.TIER1
Set interrupt priority level to 15
with INTC.IPRD
Enable pulse input from TCLKA/B pins
Set phase counting mode
with T1.TMDR1
Enable ch0/1 count operation
HITACHI 61
2. Counter value measurement 1
phacnt1
Clear interrupt request flag
No
ch1 down-count?
Yes
Set ch1 count result
in RAM
Set ch1 count result
in RAM
Set pulse width in RAM
RTE
62 HITACHI
3. Counter value measurement 2
phacnt2
Clear interrupt request flag
No
ch1 up-count?
Yes
Set ch1 count result
in RAM
Set ch1 count result
in RAM
RTE
HITACHI 63
4. Overflow
ovf1
Clear interrupt request flag
Increment software counter
RTE
5. Underflow
ovf1
Clear interrupt request flag
Increment software counter
RTE
64 HITACHI
Program List
/*-------------------------------------------------------------------*/
/*
INCLUDE FILE
*/
/*-------------------------------------------------------------------*/
#include<machine.h>
#include "SH7040.H"
/*-------------------------------------------------------------------*/
/*
PROTOTYPE
*/
/*-------------------------------------------------------------------*/
void en2(void);
#pragma interrupt(phacnt1,phacnt2,ovf1,unf1)
/*-------------------------------------------------------------------*/
/*
RAM ALLOCATION
*/
/*-------------------------------------------------------------------*/
#define msr_tim1(*(unsigned short *)0xffffe800)
#define msr_tim2(*(unsigned short *)0xffffe802)
#define cnt_data2 (*(signed long *)0xffffe804)
#define cnt_data1 (*(signed long *)0xffffe808)
#define p_cycle (*(unsigned long *)0xffffe80c)
#define cnt
#define wrk
(*(signed long *)0xffffe810)
(*(unsigned short *)0xffffe814)
/*-------------------------------------------------------------------*/
/* MAIN PROGRAM */
/*-------------------------------------------------------------------*/
void en2(void)
{
T0.TCR0 = 0xa0;
/* timer clear output compare TGRA0 */
/* output compare TIOC0A */
/* input capture TIOC0B */
/* output compare TIOC0C */
/* input capture TIOC1A,B */
/* interrupt TIOC1A,TIOC1B,TCIU1,TCIV1 */
/* set position cycle */
T0.TIOR0H = 0xf0;
T0.TIOR0L = 0x00;
T1.TIOR1 = 0xff;
T1.TIER1 = 0x33;
T0.TGR0C = msr_tim2;
T0.TGR0A = msr_tim1;
INTC.IPRD = 0x00ff;
set_imask(0x0);
/* set speed cycle */
/* set interrupt level=15 */
/* set imask level=0 */
PFCA.PACRL2 = 0x5000; /* TIOCnx sellect */
T1.TMDR1 = 0x04;
T0.TMDR0 = 0x20;
TMRSH.TSTR = 0x03;
while(1);
/* set phase counting mode1 */
/* TGRB and TGRD buffer mode */
/* start timer0,1 */
/* loop */
}
HITACHI 65
void ovf1(void)
{
T1.TSR1 &= 0xef;
cnt++;
/* clear flag */
/* count up */
}
void unf1(void)
{
T1.TSR1 &= 0xdf;
cut--;
/* clear flag */
/* count down */
}
void phacnt1(void)
{
T1.TSR1 &= 0xfe;
wrk = T1.TGR1B;
if(cnt<0)
/* clear flag */
/* count<0 */
cnt_data1 = (unsigned long)wrk-0x010000+cnt*0x010000; /* set sp */
else
cnt_data1 = (unsigned long)wrk+cnt*0x010000;
p_cycle = T0.TGR0D;
/* set sp */
/* set width pulse */
}
void phacnt2(void)
{
T1.TSR1 &= 0xfd;
wrk = T1.TGR1A;
if(cnt<0)
/* clear flag */
cnt_data2 = (unsigned long)wrk-0x010000+cnt*0x010000; /* set po */
else
cnt_data2 = (unsigned long)wrk+cnt*0x010000;
/* set po */
}
66 HITACHI
2.8 Externally Triggered Timer Waveform Cutoff
MTU, POE
Specifications
1. Waveform cutoff is performed by setting the timer output waveform to the high-impedance
state in synchronization with the falling edge of an external signal, as shown in figure 2-8-1.
External signal
POE0 pin
Timer output
High-impedance state
TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
Figure 2-8-1 Example of Externally Triggered Timer Waveform Cutoff
HITACHI 67
Functions Used
1. In this sample task, waveform output cutoff is performed by setting waveforms output by MTU
channels 3 and 4 (reset-synchronized PWM mode) to the high-impedance state in
synchronization with the falling edge of an external signal.
a. Figure 2-8-2 shows the MTU/ch3, ch4, POE block diagram.
Synchronous setting
ø
Timer
general
register 4A
(TGR4A)
Timer
general
register 3A
(TGR3A)
Clock
selection
circuit
ø/2
ø/4
ø/8
(Reset-synchronized
PWM mode setting)
Timer mode register 3
(TMDR3)
Compare-
match A
Comparator A
Timer control
register 3 (TCR3)
(Compare-match A
clear specification)
Timer counter
(TCNT3)
Output control
Counter clear
signal
generator
Comparator B
Compare-
match B
Timer general
registers B
(TGR3B, TGR4B)
Timer start register
(TSTR)
Pulse output
(Count operation enabling)
POE
TIOC3B/D,
TIOC4A/B/C/D
pins
Output
Input level control/status register
decision circuit
(IOCS)
(POE input mode setting)
POE0 pin
Input level detection circuit
Figure 2-8-2 MTU/ch3, ch4, POE Block Diagram
68 HITACHI
2. Table 2-8-1 shows the function assignments for this task. MTU and POE functions are
assigned as shown in this table to perform waveform cutoff.
Table 2-8-1 Function Assignment
Pin/Register Name
TIOC3B
TIOC3D
TIOC4A
TIOC4B
TIOC4C
TIOC4D
POE0
Function Assignment
Pulse output pins
Cutoff external signal input pin
TSTR3
Enables/disables ch3 timer counter operation
Selects ch3 timer counter clear source and input clock
Sets ch3, ch4 to reset-synchronized PWM mode
PWM cycle setting
TCR3
TMDR3
TGR3A
TGR3B
TGR3C
TGR3D
TGR4A
TGR4B
TOER
Output waveform change timing setting
Enables/disables TIOC3B/D, TIOC4A/B/C/D pin timer output
POE input mode selection
ICSR
HITACHI 69
Operation
Figure 2-8-3 shows the principles of the operation. Waveform cutoff is performed automatically
by hardware. (For the principles of reset-synchronized PWM operation, see section 2.5, Positive-
Phase and Opposite-Phase PWM 3-Phase Output, in this Application Note.)
External signal
POE0 pin
Immediately
after reset
Timer output
High-impedance state
TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
Time
Hardware processing
Hardware processing
None
1. High-impedance output from
TIOC3B/D, TIOC4A/B/C/D
pins
Software processing
Initialization
Software processing
None
1. Set TGR3A compare-match as counter
clear source
2. Set reset-synchronized PWM mode
3. Set chopping cycle in TGR3A, timing of
waveform change from TGR3B, TGR4A,
TGR4B
4. Enable TIOC3B/D, TIOC4A/B/C/D pin output
5. Set waveform cutoff on falling edge of POE0
6. Start count operation
Figure 2-8-3 Principles of Externally Triggered Timer Waveform Cutoff Operation
70 HITACHI
Software
1. Modules
Module Name
Label
Function Assignment
Main routine
down
DC motor control waveform generation
2. Arguments
Label/
Data
Input/
Register Name Function Assignment
Length
Module
Output
cycle
duk1
PWM cycle setting
1 word
Main routine Input
Setting of timing for change of waveform
output from TIOC3B/D
duk2
duk3
Setting of timing for change of waveform
output from TIOC4A/C
Setting of timing for change of waveform
output from TIOC4B/D
3. Internal Registers Used
Register Name
TMRSH.TSTR
T3.TCR3
Function Assignment
Timer count operation
Selection of timer counter clear source and input clock
Module
Main routine
T3.TOCR
Enabling of toggle output synchronized with PWM cycle, and
positive-phase and opposite-phase output level setting
T31.TGR3A
T31.TGR3B
PWM cycle setting
Setting of timing for change of waveform output from TIOC3B,
TIOC3D
T31.TGR4A
T31.TGR4B
Setting of timing for change of waveform output from TIOC4A,
TIOC4C
Setting of timing for change of waveform output from TIOC4B,
TIOC4D
T3.TOER
T3.TMDR3
POE.ICSR
Sets TIOC3B/D, TIOC4A/B/C/D pins to MTU output
Reset-synchronized PWM mode setting
Setting to high-impedance output synchronized with falling
edge of POE0 pin input signal
FPCE.PEIOR
FPCE.PECR1
Sets TIOC3B/D, TIOC4A/B/C/D pins to output
Sets TIOC3B/D, TIOC4A/B/C/D pins to MTU output
HITACHI 71
4. RAM Used
This sample task does not use any RAM apart from the arguments.
Note: The SH7040 header file name is used as the register label.
72 HITACHI
Flowchart
1. Main routine
down
Set high-impedance output synchronized
with falling edge of POE0 pin input
signal with POE.ICSR
Set TIOC3B/D, TIOC4A/B/C/D pins
to output with FPCE.PEIOR
Set TIOC3B/D, TIOC4A/B/C/D pins
to MTU output with FPCE.PECR1
Set counter clear source
to TGR3A with T3.TCR3
Set enabling of toggle output
synchronized with PWM cycle,
and positive-phase and opposite-phase
output levels, with T3.TOCR
Set pulse cycle in T31.TGR3A
Set duty values in T31.TGR3B,
T31.TGR4A/B
Set reset-synchronized
PWM mode with TMDR
Set TIOC3B/D, TIOC4A/B/C/D
pins to MTU output with T31.TOER
Enable ch3 count operation
with TMRSH.TSTR
HITACHI 73
Program List
/*-------------------------------------------------------------------*/
/*
INCLUDE FILE
*/
/*-------------------------------------------------------------------*/
#include<machine.h>
#include"SH7040.H"
/*-------------------------------------------------------------------*/
/*
PROTOTYPE
*/
/*-------------------------------------------------------------------*/
void down(void);
/*-------------------------------------------------------------------*/
/*
RAM ALLOCATION
*/
/*-------------------------------------------------------------------*/
#define cycle
#define duk1
#define duk2
#define duk3
(*(unsigned short *)0xffffe800)
(*(unsigned short *)0xffffe802)
(*(unsigned short *)0xffffe804)
(*(unsigned short *)0xffffe806)
/*-------------------------------------------------------------------*/
/* MAIN PROGRAM */
/*-------------------------------------------------------------------*/
void down(void)
{
POE.ICSR = 0x00;
POE.OCSR = 0x00;
PFCE.PEIOR = 0xfa00;
PFCE.PECR1 = 0x5544;
T0.TCR0 = 0x20;
T0.TIOR0H = 0x88;
T0.TIOR0L = 0x08;
T3.TCR3 = 0x20;
T3.TOCR = 0x00;
T31.TCNT3 = 0x0000;
T3.TMDR3 = 0xc8;
T31.TGR3A = cycle;
T31.TGR3B = duk1;
T31.TGR4A = duk2;
T31.TGR4B = duk3;
T3.TOER = 0xff;
TMRSH.TSTR = 0xc0;
while(1);
/* stop timer POE0 falling edge */
/* set output level */
/* TIOCnx sellect */
/* timer clear input capture TGRA0 */
/* input capture riseing edge TIOC0A */
/* input capture riseing edge TIOC0A */
/* timer clear input capture TGRA3 */
/* set output level */
/* set timer counter 0x0000 */
/* reset-synchronized pwm mode */
/* cycle set */
/* width set */
/* set timer3,4 output */
/* start timer3,4 */
/* loop */
}
74 HITACHI
2.9 DC Motor Control Signal Output
MTU (Gate Control Register)
Specifications
1. Waveforms required for DC brushless motor control are output as shown in figure 2-9-1. The
waveforms are output by chopping the pin gate signals and reset-synchronized PWM output.
TIOC0A pin
Feedback
TIOC0B pin
input
TIOC0C pin
TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
Chopping output
Figure 2-9-1 Example of DC Brushless Motor Control Signal Output
HITACHI 75
Functions Used
1. In this sample task, 3-phase output is performed of PWM waveforms with a positive-
phase/opposite-phase relationship and a common turning point, using MTU ch3 and ch4 in
combination. The gate signals generated from the created waveforms and feedback input are
chopped and output.
a. Figure 2-9-2 shows the MTU block diagram for this sample task.
Synchronous setting
ø
Timer
general
register 4A
(TGR4A)
Timer
general
register 3A
(TGR3A)
Clock
selection
circuit
ø/2
ø/4
ø/8
(Reset-synchronized
PWM mode setting)
Timer mode register 3
(TMDR3)
Compare-
match A
Comparator A
Timer control
register 3 (TCR3)
(Compare-match A
clear specification)
Timer counter
(TCNT3)
Output control
Counter clear
signal
generator
Comparator B
Compare-
match B
Timer general
registers B
(TGR3B, TGR4B)
Timer start register
(TSTR)
Pulse output
(Count operation enabling)
TIOC3B/D,
TIOC4A/B/C/D
pins
(DC motor control waveform output enabling)
Chopping
circuit
Timer gate control register
(TGCR)
TIOC0A/B/C pins
Gate signal
Gate output circuit
Figure 2-9-2 MTU/ch3, ch4 Block Diagram
76 HITACHI
2. Table 2-9-1 shows the function assignments for this task. MTU functions are assigned as
shown in this table to perform DC motor control waveform output.
Table 2-9-1 Function Assignment
Pin/Register Name
TIOC3B
TIOC3D
TIOC4A
TIOC4B
TIOC4C
TIOC4D
TIOC0A
TIOC0B
TIOC0C
TSTR
Function Assignment
Pulse output pins
Feedback signal input pins
Enables/disables ch3, ch4 timer counter operation
Selects ch3 timer counter clear source and input clock
Sets ch3, ch4 to reset-synchronized PWM mode operation
PWM cycle setting
TCR3
TMDR3
TGR3A
TGR3B
TGR3C
TGR3D
TGR4A
TGR4B
TOER
Output waveform change timing setting
Enables/disables TIOC3B/D, TIOC4A/B/C/D pin timer output
Enables/disables DC motor control waveform output
TGCR
HITACHI 77
Operation
Figure 2-9-3 shows the principles of the operation. DC motor control waveform output is
performed automatically by hardware. (For the principles of reset-synchronized PWM operation,
see section 2.5, Positive-Phase and Opposite-Phase PWM 3-Phase Output, in this Application
Note.)
Immediately
after reset
TIOC0A pin
Feedback
input
TIOC0B pin
TIOC0C pin
TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
Hardware processing
None
Hardware processing
1. Output gate signals to
TIOC3B/D, TIOC4A/B/C/D
pins on rising/falling edge
of TIOC0A/B/C
Software processing
Initialization
1. Set TGR3A compare-match as counter
clear source
2. Set reset-synchronized PWM mode
3. Set chopping cycle in TGR3A,
timing of waveform change from TGR3B,
TGR4A, TGR4B
2. Chop reset-synchronized
PWM output and gate output
when output level is high
Software processing
None
4. Enable TIOC3B/D, TIOC4A/B/C/D pin output
5. Enable DC motor control gate signal output
6. Start count operation
Figure 2-9-3 Principles of DC Motor Control Signal Output Operation
78 HITACHI
Software
1. Modules
Module Name
Label
Function Assignment
Main routine
dc_3out
DC motor control waveform generation
2. Arguments
Label/
Data
Input/
Register Name Function Assignment
Length
Module
Output
cycle
duk1
PWM cycle setting
1 word
Main routine Input
Setting of timing for change of waveform
output from TIOC3B/D
duk2
duk3
Setting of timing for change of waveform
output from TIOC4A/C
Setting of timing for change of waveform
output from TIOC4B/D
3. Internal Registers Used
Register Name
FPCE.PEIOR
FPCE.PECR1
TMRSH.TSTR
T3.TCR3
Function Assignment
Sets TIOC3B/D, TIOC4A/B/C/D pins to output
Module
Main routine
Sets TIOC3B/D, TIOC4A/B/C/D pins to MTU output
Timer count operation/halt setting
Selection of timer counter clear source and input clock
T3.TOCR
Enabling of toggle output synchronized with PWM cycle, and
positive-phase and opposite-phase output level setting
T31.TGR3A
T31.TGR3B
PWM cycle setting
Setting of timing for change of waveform output from TIOC3B,
TIOC3D
T31.TGR4A
T31.TGR4B
Setting of timing for change of waveform output from TIOC4A,
TIOC4C
Setting of timing for change of waveform output from TIOC4B,
TIOC4D
T3.TOER
T3.TMDR3
T3.TGCR
Sets TIOC3B/D, TIOC4A/B/C/D pins to MTU output
Reset-synchronized PWM mode setting
Enables DC motor control waveform output
HITACHI 79
4. RAM Used
This sample task does not use any RAM apart from the arguments.
Note: The SH7040 header file name is used as the register label.
80 HITACHI
Flowchart
1. Main routine
dc_3out
Set TIOC3B/D, TIOC4A/B/C/D pins
to output with FPCE.PEIOR
Set TIOC3B/D, TIOC4A/B/C/D pins
to MTU output with FPCE.PECR1
Set counter clear source to TGR3A
with T3.TCR3
Set enabling of toggle output
synchronized with PWM cycle,
and positive-phase and opposite-phase
output levels, with T3.TOCR3
Set pulse cycle in TGR3A
Set duty values with T31.TGR3B,
T31.TGR4A/B
Set TIOC3B/D, TIOC4A/B/C/D pins
to MTU output with TOER
Set reset-synchronized PWM mode
with T3.TMDR
Enable DC motor control output
with TGCR
Enable ch3 count operation
with TSTR
HITACHI 81
Program List
/*-------------------------------------------------------------------*/
/*
INCLUDE FILE
*/
/*-------------------------------------------------------------------*/
#include<machine.h>
#include"SH7040.H"
/*-------------------------------------------------------------------*/
/*
PROTOTYPE
*/
/*-------------------------------------------------------------------*/
void dc_3(void);
/*-------------------------------------------------------------------*/
/*
RAM ALLOCATION
*/
/*-------------------------------------------------------------------*/
#define cycle
#define duk1
#define duk2
#define duk3
(*(unsigned short *)0xffffe800)
(*(unsigned short *)0xffffe802)
(*(unsigned short *)0xffffe804)
(*(unsigned short *)0xffffe806)
/*-------------------------------------------------------------------*/
/* MAIN PROGRAM */
/*-------------------------------------------------------------------*/
void dc_3(void)
{
PFCE.PEIOR = 0xfa00;
PFCE.PECR1 = 0x5544;
PFCE.PECR2 = 0x0055
/* set output level */
/* TIOCnx sellect */
T0.TCR0 = 0x20;
T3.TCR3 = 0x20;
T3.TOCR = 0x00;
T31.TCNT3 = 0x0000;
T3.TMDR3 = 0xc8;
T31.TGR3A = cycle;
T31.TGR3B = duk1;
T31.TGR4A = duk2;
T31.TGR4B = duk3;
T3.TOER = 0xff;
T3.TGCR = 0x70;
TMRSH.TSTR = 0xc1;
while(1);
/* timer clear input capture TGRA0 */
/* timer clear input capture TGRA3 */
/* set output level */
/* set timer counter 0x0000 */
/* reset-synchronized pwm mode */
/* cycle set */
/* width set */
/* set timer3,4 output */
/* set DC motor output */
/* start timer0,3,4 */
/* loop */
}
82 HITACHI
2.10 Activation of A/D Conversion by MTU
and Storage of Conversion Results
DTC (Block Transfer),
A/D Converter
Specifications
1. Voltages are input on 8 channels as shown in figure 2-10-1, and the A/D conversion results are
stored in RAM by the DTC.
2. Group mode or single mode can be set for A/D conversion, with 2 channels sampled
simultaneously.
3. A/D conversion is started by an MTU TGR0A compare-match.
4. DTC block transfer is performed by means of A/D end interrupts.
Input voltage ch0
AN0
Input voltage ch1
AN1
Input voltage ch2
AN2
Input voltage ch3
AN3
Input voltage ch4
AN4
Input voltage ch5
AN5
Input voltage ch6
AN6
Input voltage ch7
AN7
Figure 2-10-1 Block Diagram of Voltage Measurement by SH7040
HITACHI 83
Functions Used
1. In this sample task, A/D conversion is started by an MTU compare-match, and the conversion
results are stored in RAM by the DTC.
a. Figure 2-10-2 shows the ch0 block diagram. Initiation of A/D conversion is performed
using the following functions:
•
•
A function for starting A/D conversion upon MTU compare-match without software
intervention
A function for automatically outputting pulses by hardware without software
intervention (output compare)
ch0
TIOC0A
(A/D start source)
Control logic
A/D
converter
Timer interrupt enable register 0
(TIER0)
Timer I/O control register 0H
(TIOR0H)
Timer general register 0A
(TGR0A)
Output
compare signal
generator
Comparator
Timer counter 0 (TCNT0)
Figure 2-10-2 SH7040 ch0 Block Diagram
84 HITACHI
b. Figure 2-10-3 shows the A/D converter block diagram. The A/D converter performs
analog-to-digital conversion using the following functions. The DTC is activated at the end
of A/D conversion.
•
•
•
A function that performs A/D conversion on a number of channels (chA to chH)
(group/single mode)
A function that performs continuous conversion by sampling the input voltages on two
channels simultaneously (simultaneous sampling)
A function that activates the DTC at the end f A/D conversion
A/D converter
A/D data register A (ADDRA)
A/D data register B (ADDRB)
A/D data register C (ADDRC)
Vref
AVSS
AVCC
10-bit
D/A
A/D data register D (ADDRD)
A/D data register E (ADDRE)
A/D data register F (ADDRF)
A/D data register G (ADDRG)
A/D data register H (ADDRH)
DTC
ADI (DTC activation source)
*
*
S&HA
S&HB
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
+
A/D
conversion
control circuit
TIOC0A
(A/D activation source)
MTU/
ch0
A/D control/status register
(ADCSR)
A/D control register
(ADCR)
Note: * Sample-and-hold circuit
Figure 2-10-3 Block Diagram of Voltage Measurement by SH7040
HITACHI 85
c. Figure 2-10-4 shows the DTC block diagram. The DTC performs block transfer using the
following function:
•
A function that transfers one block of data in response to one activation source (block
transfer function)
DTC
DTC mode register
(DTMR)
DTC information base
register (DTBR)
A/D
converter
ADI (DTC activation source)
DTC enable register C
(DTEC)
DTC controller
DTC source address
register (DTSAR)
DTC destination address
register (DTDAR)
Bus
controller
DTC transfer count
register B (DTCRB)
DTC transfer count
register A (DTCRA)
Transfer
data
Transfer destination
block
Internal address/data bus
Figure 2-10-4 SH7040 DTC Block Diagram
86 HITACHI
2. Table 2-10-1 shows the function assignments for this task.
Table 2-10-1Function Assignment
Pin/Register Name
A0 to A7
TCR0
Function Assignment
Analog measurement pins
Counter clear source selection
TIOR0H
TIER0
Input capture signal input edge selection
Enables A/D conversion start request generation
Sampling cycle setting
TGR0A
ADCR
A/D conversion mode and measurement pin setting
Conversion time and activation source selection
Store A/D conversion results
ADCSR
ADDRA to ADDRH
DTMR
Sets DTC to block transfer mode
Transfer number specification
DTCRA
DTCRB
Block length specification
DTSAR
Transfer source address setting
Transfer destination address setting
DTC vector upper 16 bit setting
DTDAR
DTBR
DTEC
Enables DTC activation at end of A/D conversion
HITACHI 87
Operation
Figure 2-10-5 shows the principles of the operation. As shown in the figure, A/D conversion is
started by a TGR0A compare-match, input voltages on AN0 to AN7 are sampled 2 channels at a
time, and conversion is performed sequentially on AN0 to AN7. When conversion is completed
for all the specified channels, the DTC is activated and the A/D conversion results are transferred
to RAM.
Immediately after reset
TGR0A
H'0000
A/D start (ADST)
A/D end (ADF)
Hardware processing
Hardware processing
1. TGR0A compare-match generation
2. Start A/D conversion
1. Execute A/D conversion for AN0–AN7
2. Store conversion results sequentially
in ADDRA–ADDRH
Software processing
None
Hardware processing
Software processing
None
1. Transfer data from
ADDRA–ADDRH to
transfer destination
address
Hardware processing
None
2. Clear ADI
Software processing
None
Software processing
Initialization
1. MTU settings
• Enable A/D activation by TGR0A compare-match
• Set A/D sampling cycle
2. A/D converter settings
• Set single/group mode as A/D conversion mode
• Set AN0–AN7 as analog input channels
• Set simultaneous 2-channel sample-and-hold operation
• Enable A/D conversion end interrupt
3. DTC settings
Hardware processing
1. A/D conversion end
interrupt generation
2. DTC activation
• Set block transfer mode as DTC transfer mode
• Set DTC activation by A/D end interrupt
• Set transfer conditions
Software processing
None
4. Start count operation
Figure 2-10-5 Principles of Pulse Width Measurement Operation
88 HITACHI
Figure 2-10-6 shows the principles of the DTC activation operation. When the DTC is operated,
the following settings should be made before activation source generation.
•
•
•
Register information settings. (Sample register information settings for block transfer mode are
shown in table 2-11-2.)
Set the lower 16 bits of the start address in which the register information is set in the DTC
vector table.
Set the upper 16 bits of the start address in which the register information is set in the DTC
information base register.
As shown in figure 2-10-6, when the DTC is activated, the lower 16 bits of the register
information start address are read from the DTC vector table. The register information start
address is generated from the value read and the DTC information base register (holding the upper
16 bits of the register information start address). Register information is read and transferred
sequentially starting from the register information start address.
Table 2-11-2 Register Information
Address
RF
Register Name
Data Length
Word
DTC mode register (DTMR)
RF+2
RF+6
RF+8
RF+12
DTC transfer count register A (DTCRA)
DTC transfer count register B (DTCRB)
DTC source address register (DTSAR)
DTC destination address register (DTDAR)
Word
Word
Longword
Longword
RF: Register information start address
HITACHI 89
Register
information
start address
DTC information
base register (DTBR)
upper 16 bits
DTC vector
address lower
16 bits
RF
+
RF+1
RF+2
RF+3
RF+4
RF+5
RF+6
RF+7
RF+8
RF+9
RF+10
RF+11
RF+12
RF+13
RF+14
RF+15
RF+16
DTC
vector table
Register
information
Figure 2-10-6 Principles of the DTC Activated Operation
90 HITACHI
Software
1. Modules
Module Name
Label
Function Assignment
Main routine
adscan
Setting of A/D converter activation by MTU and DTC
activation at end of A/D conversion
2. Arguments
Label/
Data
Input/
Register Name Function Assignment
Length
Module Output
transsadr DTC transfer destination address setting
Longword Main
routine
Input
For 8 channel A/D conversion results, 8 data items
are stored in longword units starting with transaddr
Each 10-bit conversion result is set as follows:
Upper byte
AD9 AD8
Lower byte AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
HITACHI 91
3. Internal Registers Used
Register Name
TMRSH0.TSTR
T0.TCR0
Function Assignment
Module
Timer count operation/disable setting
Main routine
TCNT counter clock selection and setting of output compare
A as counter clear source
T0.TIOR0H
T0.TIER0
Sets TGR0A to output compare
Enables A/D conversion start request generation
Sets A/D conversion sampling cycle
T0.TGRA0
A_D.ADCR
Setting of A/D conversion mode (single mode),
simultaneous sampling operation, and activation source as
MTU conversion start trigger
A_D.ADCSR
A/D conversion channel (group mode), conversion channel
(AN0–AN7), and conversion time setting
Enables A/D conversion end interrupt
A/D conversion result storage
A_D.ADDRA to
A_D.ADDRH
—
DTC.DTMR
DTC.DTCRA
DTC.DTCRB
DTC.DTSAR
DTC.DTDAR
DTC.DTBR
DTC.DTEC
PFCE.PECR2
INTC.IPRG
Sets DTC to block transfer mode
Main routine
Sets number of transfers to 1
Specifies block length of 8
Sets ADDRA as transfer destination address
Sets RAM as transfer destination address
Setting of DTC vector upper 16 bits
Enables DTC activation at end of A/D conversion
Enables pulse input from TIOC0A
Sets A/D conversion end interrupt level to 15
4. RAM Used
This sample task does not use any RAM apart from the arguments.
Note: The SH7040 header file name is used as the register label.
92 HITACHI
Flowchart
1. Main routine
adscan
Set output compare A as counter
clear source with T0.TCR0
Set TGR0A to output
compare with T0.TIOR0H
Enable A/D conversion start request
generation on TGR0A compare-match
with T0.TIER0
Set single, group, simultaneous sampling
operation for A/D conversion
with A_D.ADCR, A_D.ADCSR
Enable A/D conversion end interrupt
with A_D.ADCSR
Make following DTC vector settings:
• Set block transfer as DTC
transfer mode.
• Set 1 as number of transfers
• Set 8 as transfer block length
• Set transfer source address
• Set transfer destination address
Set upper 16 bits of DTC vector
with DTC.DTBR
Enable DTC activation on generation
of A/D conversion end interrupt
with DTC.DTEC
Set ADI interrupt priority level to 15
with INTC.IPRG
Enable ch0 count operation
with TMRSH.TSTR
HITACHI 93
Program List
/*-------------------------------------------------------------------*/
/*
INCLUDE FILE
*/
/*-------------------------------------------------------------------*/
#include<machine.h>
#include"SH7040.H"
/*-------------------------------------------------------------------*/
/*
PROTOTYPE
*/
/*-------------------------------------------------------------------*/
void a_d(void);
/*-------------------------------------------------------------------*/
/*
RAM ALLOCATION
*/
/*-------------------------------------------------------------------*/
#define DTMR
#define DTCRA
#define DTCRB
#define DTSAR
#define DTDAR
#define dtmr1
(*(unsigned short *)0xffffe800)
(*(unsigned short *)0xffffe802)
(*(unsigned short *)0xffffe806)
(*(unsigned long *)0xffffe808)
(*(unsigned long *)0xffffe80c)
(*(unsigned short *)0xffffe810)
#define dtcra1 (*(unsigned short *)0xffffe812)
#define dtcrb1 (*(unsigned short *)0xffffe816)
#define dtsar1 (*(unsigned long *)0xffffe818)
#define dtdar1 (*(unsigned long *)0xffffe81c)
/*-------------------------------------------------------------------*/
/*
MAIN PROGRAM
*/
/*-------------------------------------------------------------------*/
void a_d(void)
{
T0.TCR0 = 0x20;
T0.TIOR0H = 0x00;
T0.TIER0 = 0x80;
T0.TGR0A = 0x1000;
A_D.ADCR = 0x14;
A_D.ADCSR = 0x4f;
DTMR = dtmr1;
DTCRA = dtcra1;
DTCRB = dtcrb1;
DTSAR = dtsar1;
DTDAR = dtdar1;
DTC.DTBR = 0xffff;
DTC.DTEC = 0x40;
INTC.IPRG = 0x0f00;
set_imask(0x0);
TMRSH.TSTR = 0x01;
while(1);
/* timer clear output compare TGR0A */
/* interrupt TGI00A */
/* set get A/D cycle */
/* set sampling */
/* set mode single/group */
/* set transmission mode DTC */
/* set transmission frequency */
/* set transmission block frequency */
/* set transmission address */
/* set transmission address */
/* set DTC data base register */
/* set a/d end start DTC */
/* set interrupt level=15 */
/* set imask level=0 */
/* TCNTO start */
/* loop */
}
Note: Set the lower 16 bits of the register information start address in DTC vector table address
0x422 (vector when DTC activation condition is A/D conversion end).
94 HITACHI
2.11 RAM Monitor Using DMAC
SCI, DMAC
Specifications
1. Using the SH7040’s SCI in asynchronous mode, a RAM reference address (4-byte data)
transmitted from the console is received, and its contents are fetched from RAM and
transmitted to the console via the SCI, as shown in figure 2-11-1.
2. The transmission protocol is 9600 bps, 8-bit data, one stop bit, non-parity.
3. DMAC direct address mode is used for data transfer from RDR to RAM, and the RDR receive
data is stored in RAM, as shown in figure 2-12-2.
4. DMAC indirect address mode is used for data transfer from RAM to TDR, as shown in figure
2-11-3. The operation is performed as follows:
a. The data held in RAM is stored in a temporary buffer in the DMAC, and data is fetched
from RAM using the buffer data as the address.
b. The fetched data is transferred sequentially to TDR in byte units.
5. The DMAC transfer conditions are shown in tables 2-11-1 and 2-11-2.
RS-232C
Console
level
conversion
RXD
TXD
RDR
TX
DMA transfer
RAM
RX
TDR
DMA transfer
Figure 2-11-1 Block Diagram of SCI Transfer of RAM Data by SH7040
Address 1
Address 2
RDR
4 bytes
Address 3
Address 4
Figure 2-11-2 Data Transfer Using DMAC (Transfer Source Direct Address)
HITACHI 95
RAM
DMAC
Address 1
Address 2
Address 3
Address 4
Temporary
buffer
4 bytes
Address
Data 1
Data 2
Data 3
Data 4
TDR
Figure 2-11-3 Data Transfer Using DMAC (Transfer Source Indirect Address)
Table 2-11-1 DMAC Transfer Conditions in SCI Reception (RDR → RAM)
Condition
Description
Channel 0
On-chip SCI channel 0
On-chip RAM
4
DMAC channel
Transfer source
Transfer destination
Number of transfers
Transfer source address
Transfer destination address
Transfer request source
Bus mode
Fixed
Incremented
SCI channel 0
Cycle steal
Byte
Transfer unit
Table 2-11-2 DMAC Transfer Conditions in SCI Transmission (RAM → TDR)
Condition
Description
Channel 3
On-chip RAM
On-chip SCI channel 0
4
DMAC channel
Transfer source
Transfer destination
Number of transfers
Transfer source address
Transfer destination address
Transfer request source
Bus mode
Incremented
Fixed
SCI channel 0
Cycle steal
Byte
Transfer unit
96 HITACHI
Functions Used
1. This sample task performs RAM monitoring using the SCI and DMAC.
a. Figure 2-11-4 shows the SCI transmission block diagram. This task performs data
transmission to the console using the following SCI functions:
•
•
A function that carries out data communication asynchronously, with synchronization
performed character by character (asynchronous mode)
A function that generates an interrupt on completion of transmission (TEI interrupt)
Interrupt setting
Transmit mode setting
Serial control register (SCR)
TXD pin
(serial output)
Asynchronous mode setting
Serial communication format setting
Transmit shift register (TSR)
Serial mode register (SMR)
Transmission/reception
control circuit
Directs start of transmission
Transmit data register (TDR)
Holds transmit data
Serial status register (SSR)
Transfer rate generation
Baud rate generator
Transmit-data-empty interrupt (TEI)
DMAC/
ch3
Baud rate register (BRR)
Figure 2-11-4 SCI Transmission Block Diagram
HITACHI 97
b. Figure 2-11-5 shows the SCI reception block diagram. This task performs data reception
from the console using the following SCI functions, as shown in the figure:
•
•
A function that carries out data communication asynchronously, with synchronization
performed character by character (asynchronous mode)
A function that generates an interrupt on completion of reception (RXI interrupt)
Interrupt setting
Receive mode setting
Serial control register (SCR)
Asynchronous mode setting
Serial communication format
setting
Holds receive data
Serial mode register (SMR)
Receive data register (RDR)
Transmission/reception
control circuit
RXD pin
(serial input)
Transfer rate generation
Baud rate generator
Receive shift register (RSR)
Baud rate register (BRR)
Receive data full interrupt (RXI)
DMAC/
ch0
Figure 2-11-5 SCI Reception Block Diagram
98 HITACHI
c. Figure 2-11-6 shows the DMAC/ch0 block diagram for this sample task. This task
performs block transfer using the following DMAC/ch0 functions:
•
•
A function that directly transfers data for both the transfer source and transfer
destination when the DMAC is activated (direct address transfer mode)
A function that activates the DMAC via the SCI
DMAC0
Transfer mode setting
Transfer number setting
DMA channel
control register 0
(CHCR0)
DMA
operation register
(DMAOR)
DMA transfer
count register 0
(TCR0)
RXI
(DMA0 activation source)
DEI0
DMA control
SCI
Transfer source
address setting
Transfer destination
address setting
Bus
controller
DMA destination
address register 0
(DAR0)
DMA source
address register 0
(SAR0)
Transfer
destination
block
Transfer
source block
Internal address/data bus
Figure 2-11-6 DMA/ch0 Block Diagram
HITACHI 99
d. Figure 2-11-7 shows the DMAC/ch3 block diagram for this sample task. This task
performs block transfer using the following DMAC/ch3 functions:
•
•
A function that transfers data stored in the transfer source register when the DMAC is
activated (indirect address transfer mode)
A function that activates the DMAC via the SCI
DMAC3
Transfer mode setting
Transfer number setting
DMA channel
control register 3
(CHCR3)
DMA
operation register
(DMAOR)
DMA transfer
count register 3
(TCR3)
TEI
(DMA3 activation source)
DEI3
DMA control
SCI
Transfer source
address setting
Transfer destination
address setting
Bus
controller
DMA destination
address register 3
(DAR3)
DMA source
address register 3
(SAR3)
Transfer
destination
block
Transfer
source block
Internal address/data bus
Figure 2-11-7 DMA/ch3 Block Diagram
100 HITACHI
Table 2-11-1 shows the function assignments for this sample task. DMAC and SCI functions are
assigned to perform data transfer transmission/reception via the SCI.
Table 2-11-1 Function Assignment
Pin/Register Name
SAR0
Function Assignment
Transfer source address setting
SAR3
DAR0
DAR3
TCR0
Transfer destination address setting
Transfer number setting
TCR3
CHCR0
CHCR3
DMAOR
RXD
Setting of DMAC operating mode, transfer method, etc.
Executing DMAC channel priority level setting
Data receive pin
TXD
Data transmit pin
SMR
SCI transmission format setting
SCI interrupt enabling/disabling setting
Interrupt status setting
SCR
SSR
RDR
Holds receive data from console
Holds transmit data to be sent to console
Transfer rate setting
TDR
BRR
HITACHI 101
Operation
Figure 2-11-9 shows the principles of the operation. As shown in this figure, data transmission and
reception is performed serially by means of SH7040 hardware and software processing.
Data 1
Data 4
RXR
TXR
Data 1
Data 4
Hardware processing
None
Hardware processing
Hardware processing
1. Store RDR contents
in RAM
2. Generate DEI0
1. Store contents of RAM
transfer data in TDR as
address
2. Increment transfer
source address
Software processing
Initialization
1. Set SCI to asynchronous
mode
2. Set transfer rate
3. Enable DMA transfer end
interrupt
Software processing
1. Enable transmit-data-empty
interrupt requests
Software processing
None
4. Set transfer source and
destination addresses,
and number of transfers
5. Set SCI as transfer
request source, and
byte-size as transfer unit
Hardware processing
1. Store contents of RAM transfer
data in TDR as address
2. Generate DEI3
Software processing
1. Re-set transfer source and
destination addresses and number
of transfers
2. Disable transmit-data-empty
interrupt requests
Hardware processing
1. Store RDR contents in RAM
2. Increment transfer destination
address
Software processing
None
Figure 2-11-8 Principles of Data Transfer Operation Using SCI
102 HITACHI
Software
1. Modules
Module Name
Label
Function Assignment
Main routine
rammon
dma_rdr
Performs SCI and DMAC initialization
Receive data transfer
Initiated by DEI0; enables transmit-data-empty
interrupt requests
Transmit data transfer
dma_tdr
Initiated by DEI3; re-sets transfer source and
destination addresses and number of transfers
Disables transmit-data-empty interrupt requests
2. Arguments
Label/
Data
Input/
Register Name Function Assignment
Length
Module
Output
data0 Stores transfer address
Longword
Main routine
Input
3. Internal Registers Used
Register Name
DM0.SAR0
DM0.DAR0
DM0.TCR0
DM0.CHCR0
DM3.SAR3
Function Assignment
RDR address setting
Module
Main routine
Main routine
Transfer destination RAM start address setting
Set to H'4 (4 transfers)
Setting of DMAC operating mode, transfer method, etc
Transfer source RAM start address setting
Main routine
Receive data
transfer
DM3.DAR3
TDR address setting
Main routine
DM3.TCR3
Set to H'4 (4 transfers
DM3.CHCR3
DMAC.DMAOR
Setting of DMAC operating mode, transfer method, etc.
Executing DMAC channel priority level setting
Main routine
Transmit data
transfer
PFCA.PADRL
PFCA.PACRL2
IINTC.IPRC
SCI0.SMR0
SCI0.SCR0
Specifies SCI input/output
Sets pin multiplexing to SCI0 use
Sets DMAC0, DMAC3 interrupt priority levels to 14, 15.
Sets SCI to asynchronous mode
Enables transmit and receive interrupts, and transmit and
receive operations
SCI0.BRR0
Transfer rate setting
HITACHI 103
4. RAM Used
Label
Function
Data Length
Module
lk_addr
Stores RAM reference address
Unsigned long
Main routine
Note: The SH7040 header file name is used as the register label.
104 HITACHI
Flowchart
1. Main routine
rammon
Set TXD and RXD pin input/output
direction with PFCA.PADR
Set as SCI pins with PFCA.PACRL2
Set transfer method with SCI0.SMR
Set bit rate with SCI0.BRR
Secure setting time
Enable receive interrupts,
receive operation with SCI0.SCR
Set transfer source address and
transfer destination address
with DM0.SCR0/DM0.DCR0
Set transfer method
with DM0.TCR0/DM0.CHCR0
Set transfer source address and
transfer destination address
with DM3.SCR3/DM3.DCR3
Set transfer method
with DM3.TCR3/DM3.CHCR3
Activate DMAC with DMAC.DMAOR
Set interrupt priority levels
to 15/10 with INTC.IPRC/IPRF
HITACHI 105
2. Receive data transfer
dma_rdr
Clear interrupt request flag
Enable transmit interrupts,
transmit operation
Set transfer source address,
number of transfers
Clear interrupt request flag
RTE
3. Transmit data transfer
dma_tdr
Clear interrupt request flag
Enable receive interrupts,
receive operation
Set transfer destination
address, number of transfers
RTE
106 HITACHI
Program List
/*-------------------------------------------------------------------*/
/*
INCLUDE FILE
*/
/*-------------------------------------------------------------------*/
#include<machine.h>
#include"sh7040.h"
/*-------------------------------------------------------------------*/
/*
PROTOTYPE
*/
/*-------------------------------------------------------------------*/
void rammon(void);
#pragma interrupt(dma0)
#pragma interrupt(dma_sci)
#pragma interrupt(sci_rxi)
/*-------------------------------------------------------------------*/
/*
RAM ALLOCATION
*/
/*-------------------------------------------------------------------*/
#define data0(*(volatile unsigned char *)0xffffe800)
volatile struct addr
{
long addr0;
/* transmit address */
};
#define dat(*(struct addr *)0xFFFFE810)
/*-------------------------------------------------------------------*/
/* MAIN PROGRAM */
/*-------------------------------------------------------------------*/
rammon()
{
signed int lp;
dat.addr0 = (long)&data0;
data0 = 'H';
PFCA.PADRL = 0x0002;
PFCA.PACRL2 = 0x0005;
SCI0.SCR0 = 0x00;
/* out put TXD0,input RXD0 */
/* TXD0,RXD0 sellect */
/* stop transmit•receive */
SCI0.SMR0 = 0x00;
/* asynchronous mode,8bit data,not parity */
/* bit rates 9600bps */
SCI0.BRR0 = 0x40;
SCI0.SCR0 = 0x00;
/* clock seiiect */
for(lp = 1; lp<1; lp++);
SCI0.SCR0 = 0x50;
/* wait400ns */
/* interrupt receive sci,receiving enabled */
/* source address:RAM */
DM0.SAR0 = (long)(&SCI0.RDR);
DM0.DAR0 = (long)(&dat.addr0);
DM0.TCR0 = 0x04;
/* distination address:SCI transmit register */
/* transmit count:4 */
DM0.CHCR0 = 0x00004905;
DM3.SAR3 = (long)(&dat.addr0);
DM3.DAR3 = (long)(&SCI0.TDR);
DM3.CHCR3 = 0x00181804;
DMAC.DMAOR = 0x0001;
INTC.IPRC = 0xe00f;
INTC.IPRF = 0x00a0;
set_imask(0x0);
/* indirect,source increment,byte-size transfer */
/* source address:RAM */
/* distination address:SCI transmit register */
/* indirect,source increment,byte-size transfer */
/* data transfer enabled */
/* set interrupt level=15 */
/* set interrupt level=10 */
/* interrupt requested enabled */
/* loop */
while(1);
}
HITACHI 107
void dma_rdr(void)
{
DM0.CHCR0 &= 0xfffffffd;
SCI0.SCR0 = 0xa0;
DM3.SAR3 = (long)(&dat.addr0);
DM3.TCR3 = 0x01;
DM3.CHCR3 I= 0x00000001;
}
/* clear flag */
/* interrupt transmit sci,transmit enabled */
/* source address:RAM */
/* transmit count:4 */
/* clear flag */
void dma_tdr(void)
{
DM3.CHCR3 &= 0xfffffffc;
SCI0.SCR0 = 0x70;
DM0.DAR0 = (long)(&dat.addr0);
DM0.TCR0 = 0x04;
/* clear flag */
/* interrupt receive sci,receiving enabled */
/* distination address:SCI transmit register */
/* transmit count:4 */
}
108 HITACHI
Appendix A
A.1 Header File
Program List
/*----------------------------------------------------------------------*/
/*
*/
/* Internal I/O register address define
/*
*/
*/
/*----------------------------------------------------------------------*/
/*----------------------------------------------------------------------*/
/* INTC
*/
/*----------------------------------------------------------------------*/
volatile struct intc
{
short IPRA;
short IPRB;
short IPRC;
short IPRD;
short IPRE;
short IPRF;
short IPRG;
short IPRH;
short ICR;
short ISR;
/* interrupt priority register A */
/* interrupt priority register B */
/* interrupt priority register C */
/* interrupt priority register D */
/* interrupt priority register E */
/* interrupt priority register F */
/* interrupt priority register G */
/* interrupt priority register H */
/* interrupt controll register */
/* IRQ status register */
};
#define INTC (*(volatile struct intc *)0xffff8348)
/*----------------------------------------------------------------------*/
/*UBC
*/
/*----------------------------------------------------------------------*/
volatile struct ubc
{
short UBARH;
short UBARL;
short UBAMRH;
short UBAMRL;
short UBBR;
/* user break address register H */
/* user break address register L */
/* user break mask register H */
/* user break mask register L */
/* user break bus cycle register */
};
#define UBC (*(volatile struct ubc *)0xffff8600)
HITACHI 109
/*----------------------------------------------------------------------*/
/* DTC
*/
/*----------------------------------------------------------------------*/
volatile struct dtcsh
{
char DTEA;
char DTEB;
char DTEC;
char DTED;
char DTEE;
char res1;
short DTCSR;
short DTBR;
/* enable register A */
/* enable register B */
/* enable register C */
/* enable register D */
/* enable register E */
/* control/status register */
/* information base register */
};
#define DTC (*(volatile struct dtcsh *)0xffff8700)
/*----------------------------------------------------------------------*/
/* CAC
*/
/*----------------------------------------------------------------------*/
volatile struct cac
{
char CCR;
/* cash control register */
};
#define CAC (*(volatile struct cac *)0xffff8740)
/*----------------------------------------------------------------------*/
/* BSC
*/
/*----------------------------------------------------------------------*/
volatile struct bsc
{
short BCR1;
short BCR2;
short WCR1;
short WCR2;
short res2;
short DCR;
short RTCSR;
short RTCNT;
short RTCOR;
/* bus control register 1 */
/* bus control register 2 */
/* wait control register 1 */
/* wait control register 2 */
/* DRAM area control register */
/* refresh timer control register */
/* refresh timer counter */
/* refresh timer constant register */
};
#define BSC (*(volatile struct bsc *)0xffff8620)
110 HITACHI
/*----------------------------------------------------------------------*/
/* DMAC
*/
/*----------------------------------------------------------------------*/
volatile struct dmacsh
{
long DMAOR;
/* operation register */
};
volatile struct dmac0
{
long SAR0;
long DAR0;
long TCR0;
long CHCR0;
};
/* source address register 0 */
/* destination address register 0 */
/* transfer count register 0 */
/* channel control register 0 */
volatile struct dmac1
{
long SAR1;
long DAR1;
long TCR1;
long CHCR1;
};
/* source address register 1 */
/* destination address register 1 */
/* transfer count register 1 */
/* channel control register 1 */
volatile struct dmac2
{
long SAR2;
long DAR2;
long TCR2;
long CHCR2;
};
/* source address register 2 */
/* destination address register 2 */
/* transfer count register 2 */
/* channel control register 2 */
volatile struct dmac3
{
long SAR3;
long DAR3;
long TCR3;
long CHCR3;
};
/* source address register 3 */
/* destination address register 3 */
/* transfer count register 3 */
/* channel control register 3 */
#define DMAC (*(volatile struct dmac *)0xffff86b0)
#define DM0 (*(volatile struct dmac0 *)0xffff86c0)
#define DM1 (*(volatile struct dmac1 *)0xffff86d0)
#define DM2 (*(volatile struct dmac2 *)0xffff86e0)
#define DM3 (*(volatile struct dmac3 *)0xffff86f0)
/*----------------------------------------------------------------------*/
/* MTU
*/
/*----------------------------------------------------------------------*/
volatile struct tmrsh1
{
char TSTR;
char TSYR;
/* timer start register */
/* timer synchronous register */
};
#define TMRSH (*(volatile struct tmrsh1*)0xffff8240)
/*----------------------------------------------------------------------*/
HITACHI 111
/* MTU CHO
*/
/*----------------------------------------------------------------------*/
volatile struct timer0
{
char TCR0;
char TMDR0;
char TIOR0H;
char TIOR0L;
char TIER0;
char TSR0;
short TCNT0;
short TGR0A;
short TGR0B;
short TGR0C;
short TGR0D;
/* timer controll register 0 */
/* timer mode register 0 */
/* timer i/o controll register 0H */
/* timer i/o controll register 0L */
/* timer interrupt enable register 0 */
/* timer stasus register 0 */
/* timer counter 0 */
/* timer general register 0A */
/* timer general register 0B */
/* timer general register 0C */
/* timer general register 0D */
};
#define T0 (*(volatile struct timer0 *)0xffff8260)
/*----------------------------------------------------------------------*/
/* MTU CH1
*/
/*----------------------------------------------------------------------*/
volatile struct timer1
{
char TCR1;
char TMDR1;
char TIOR1;
char res3;
char TIER1;
char TSR1;
short TCNT1;
short TGR1A;
short TGR1B;
/* timer controll register 1 */
/* timer mode register 1 */
/* timer i/o controll register 1H */
/* timer interrupt enable register 1 */
/* timer status register 1 */
/* timer counter 1 */
/* timer general register 1A */
/* timer general register 1B */
};
#define T1 (*(volatile struct timer1 *)0xffff8280)
/*----------------------------------------------------------------------*/
/* MTU CH2
*/
/*----------------------------------------------------------------------*/
volatile struct timer2
{
char TCR2;
char TMDR2;
char TIOR2;
char res4;
char TIER2;
char TSR2;
short TCNT2;
short TGR2A;
short TGR2B;
/* timer controll register 2 */
/* timer mode register 2 */
/* timer i/o controll register 2H */
/* timer interrupt enable register 2 */
/* timer status register 2 */
/* timer counter 2 */
/* timer general register 2A */
/* timer general register 2B */
};
#define T2 (*(volatile struct timer2 *)0xffff82a0)
/*----------------------------------------------------------------------*/
/* MTU CH3,4
*/
112 HITACHI
/*----------------------------------------------------------------------*/
volatile struct timer3
{
char TCR3;
char TCR4;
char TMDR3;
char TMDR4;
char TIOR3H;
char TIOR3L;
char TIOR4H;
char TIOR4L;
char TIER3;
char TIER4;
char TOER;
char TOCR;
char res5;
char TGCR;
/* timer contorol register 3 */
/* timer contorol register 4 */
/* timer mode register 3 */
/* timer mode register 4 */
/* timer i/o contorol register 3H */
/* timer i/o contorol register 3L */
/* timer i/o contorol register 4H */
/* timer i/o contorol register 4L */
/* timer interrupt enable register 3 */
/* timer interrupt enable register 4 */
/* timer output master enable register */
/* timer output contorol register */
/*
/* timer gate contorol register */
};
volatile struct timer31
{
short TCNT3;
short TCNT4;
short TCDR;
short TDDR;
short TGR3A;
short TGR3B;
short TGR4A;
short TGR4B;
short TCNTS;
short TCBR;
short TGR3C;
short TGR3D;
short TGR4C;
short TGR4D;
char TSR3;
char TSR4;
};
/* timer counter 3 */
/* timer counter 4 */
/* timer cycle-data register */
/* timer deadtime-data register */
/* timer general register 3A */
/* timer general register 3B */
/* timer general register 4A */
/* timer general register 4B */
/* timer sub-counter */
/* timer cycle buffer register */
/* timer general register 3C */
/* timer general register 3D */
/* timer general register 4C */
/* timer general register 4D */
/* timer status register 3 */
/* timer status register 4 */
#define T3(*(volatile struct timer3 *)0xffff8200)
#define T31(*(volatile struct timer31 *)0xffff8210)
/*----------------------------------------------------------------------*/
/* WDT
*/
/*----------------------------------------------------------------------*/
volatile struct wdt
{
char TCSR;
char TCNT;
char RSTCSR;
/* timer contorol status register */
/* timer counter */
/* riset contorol status register */
};
#define WDT(*(volatile struct wdt *)0xffff8610)
HITACHI 113
/*----------------------------------------------------------------------*/
/* SCI
*/
/*----------------------------------------------------------------------*/
volatile struct sci0
{
char SMR0;
char BRR0;
char SCR0;
char TDR0;
char SSR0;
char RDR0;
/* serial mode register 0 */
/* bit-rate register 0 */
/* sirial contorol register 0 */
/* transmit data register 0 */
/* sirial status register 0 */
/* receive data register 0 */
};
volatile struct sci1
{
char SMR1;
char BRR1;
char SCR1;
char TDR1;
char SSR1;
char RDR1;
};
/* serial mode register 1 */
/* bit-rate register 1 */
/* sirial contorol register 1 */
/* transmit data register 1 */
/* sirial status register 1 */
/* receive data register 1 */
#define SCI0 (*(volatile struct sci0 *)0xffff81a0)
#define SCI1 (*(volatile struct sci1 *)0xffff81b0)
/*----------------------------------------------------------------------*/
/* A/D
*/
/*----------------------------------------------------------------------*/
volatile struct a_d
{
char ADCSR;
char ADCR;
/* A/D contorol status register */
/* A/D contorol register */
};
volatile struct a_d0
{
short ADDRA;
short ADDRB;
short ADDRC;
short ADDRD;
short ADDRE;
short ADDRF;
short ADDRG;
short ADDRH;
};
/* A/D data register A */
/* A/D data register B */
/* A/D data register C */
/* A/D data register D */
/* A/D data register E */
/* A/D data register F */
/* A/D data register G */
/* A/D data register H */
#define A_D (*(volatile struct a_d *)0xffff83e0)
#define A_D0 (*(volatile struct a_d0 *)0xffff83f0)
114 HITACHI
/*----------------------------------------------------------------------*/
/* CMT
*/
/*----------------------------------------------------------------------*/
volatile struct cmt
{
short CMSTR;
short CMCSR0;
short CMCNT0;
short CMCOR0;
short CMCSR1;
short CMCNT1;
short CMCOR1;
/* compare/match timer start register */
/* compare/match timer contorol register 0 */
/* compare/match counter 0 */
/* compare/match constant register 0 */
/* compare/match timer contotol register */
/* compare/match counter 1 */
/* compare/match timer contorol register 1 */
};
#define CMT (*(volatile struct cmt *)0xffff83d0)
/*----------------------------------------------------------------------*/
/* PFC
*/
/*----------------------------------------------------------------------*/
volatile struct pfca
{
short PADRH;
short PADRL;
short PAIORH;
short PAIORL;
short PACRH;
short res6;
/* portA data register H */
/* portA data register L */
/* portA I/O register H */
/* portA I/O register L */
/* portA contorol register H */
short PACRL1;
short PACRL2;
/* portA contorol register L1 */
/* portA contorol register L2 */
};
volatile struct pfcb
{
short PBDR;
short PCDR;
short PBIOR;
short PCIOR;
short PBCR1;
short PBCR2;
short PCCR;
};
/* portB data register */
/* portC data register */
/* portB I/O register */
/* portC I/O register */
/* portB contorol register 1 */
/* portB contorol register 2 */
/* portC contorol register */
volatile struct pfcd
{
short PDDRH;
short PDDRL;
short PDIORH;
short PDIORL;
short PDCRH1;
short PDCRH2;
short PDCRL;
};
/* portD data register H */
/* portD data register L */
/* portD I/O register H */
/* portD I/O register L */
/* portD contorol register H1 */
/* portD contorol register H2 */
/* portD contorol register L */
volatile struct pfce
{
short PEDR;
char PFDR;
char res7;
short PEIOR;
short res8;
/* portE data register H */
/* portF data register */
/* portE I/O register */
HITACHI 115
short PECR1;
short PECR2;
/* portE contorol register 1 */
/* portE contorol register 2 */
};
volatile struct pfc0
{
short IFCR;
};
/* IRQOUT contorol register */
#define PFCA (*(volatile struct pfca *)0xffff8380)
#define PFCB (*(volatile struct pfcb *)0xffff8390)
#define PFCD (*(volatile struct pfcd *)0xffff83A0)
#define PFCE (*(volatile struct pfce *)0xffff83B0)
#define PFC0 (*(volatile struct pfc0 *)0xffff83C8)
/*----------------------------------------------------------------------*/
/* POE
*/
/*----------------------------------------------------------------------*/
volatile struct poe
{
short ICSR;
short OCSR;
/* input-level contorol status register */
/* output-level contorol status register */
};
#define POE (*(volatile struct poe *)0xffff83c0)
116 HITACHI
SH7040 Series On-Chip Supporting Modules Application Note
Publication Date: 1st Edition, September 1996
Published by:
Semiconductor and IC Div.
Hitachi, Ltd.
Edited by:
Technical Documentation Center
Hitachi Microcomputer System Ltd.
Copyright © Hitachi, Ltd., 1996. All rights reserved. Printed in Japan.
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