HD66130_技术文档

HD66130T

320-channel Low-voltage Segment Driver for Dot-Matrix STN

Liquid Crystal Display

Description

The HD66130T is a 320-channel segment driver for driving a dot-matrix STN liquid-crystal panel at a low

voltage. The driver can also correspond to 240-channel output by switching mode. It operates at a low

voltage: a liquid-crystal drive voltage of 5 V and a logic drive voltage of 3 V, and is used together with

common driver HD66131T or HD66135T. The package, which adopts a flexible TCP, can be applied to

various liquid crystal panels.

Features

•

Display duty: Up to 1/240

Liquid crystal drive voltage: 2.6 to 5.5 V

Number of liquid crystal drive circuits: 320 circuits

Operating voltage: 2.5 to 5.5 V

Number of data bits: 4 or 8 bits

Shift clock speed: 8 MHz max/5V

6.5 MHz max/3V

•

Together with the common drivers

HD66131T , HD66135T

•

Low power consumption

Switching output mode: 320 output mode

240 output mode

•

Display-off function

Flexible TCP

Automatic generation of chip-enable signals

Standby function

1

HD66130T

Pin Arrangement

Top View

Note: TCP dimensions are not defined.

Internal Block Diagram

Y1–Y320

*

V0L

VML

V1L

V0L

Liquid crystal drive circuit

Level shifter

VML

V1L

Vcc

GND2

GND1

Level

shifter

Timing

CL1

Latch circuit 2

DISP

generator

M

circuit

BS

Latch circuit 1

Data

rearrangement

circuit

D0–D7

CL2

SHL

Shift register

MODE

EIO1

EIO2

Note: Pins V0L, VML, and V1L are internally connected to pins V0R, VMR, and V1R, respectively.

2

HD66130T

1. Liquid crystal drive circuit

Selects and outputs the liquid crystal drive level V0, VM, or V1 by DISP and a combination of data for

latch circuit 2 and signal M.

2. Level shifter

Converts logic signals to liquid crystal drive signals.

3. Latch circuit 2

320-bit latch circuit, which latches the data of latch circuits 1 at the fall of CL1 and outputs the data to

the level shifter.

4. Latch circuit 1

4/8-bit parallel data latch circuit, which latches display data D0 to D7 according to signals transmitted

from the shift register.

5. Shift register

80-bit shift register, which generates data-capture signals for latch circuits 1 at the fall of CL2.

6. Data rearrangement circuit

Inverts the order of data output crosswise.

7. Timing generator circuit

The timing generator circuit generates data latch pulses for latch circuit2 and changes pulse the LCD

drive outputs to AC.

HIFAS Family timing Comparision

HD66130/131/134/135

HD66132/133

CL1

M

Input

signal

Segment

Common

Output

signal

3

HD66130T

Pin Functions

Class

Symbol Number Name

I/O

Functions

Power

supply

V_CC

GND1

GND2

343

324

340

V_CC

GND

—

V_CC–GND: Power supply for logic.

V0L, R 345, 322 V0L, R Input Liquid crystal drive level power supply

VML, R 346, 321 VML, R

V1L, R 344, 323 V1L, R

V0

VM

V1

Control

signal

CL1

CL2

M

327

328

326

Clock 1 Input Latch signal of display data: A liquid crystal drive signal

corresponding to display data is output at the fall of CL1.

Clock 2 Input Capture signal of display data: Display data is captured

at the fall of CL2.

M

Input A.C. signal of liquid crystal drive output

Display data Liquid crystal drive output Liquid crystal display

D0 to D7 336 to

329

DATA 0 Input

to

1 (Vcc level) Selected level

ON

DATA 7

0 (GND level) Not-selected level

OFF

SHL

339

338

Shift Left Input Control signal for inverting the order of data output

(see the following page)

SHL

GND

Vcc

EI/O1

EI/O2

EIO1

Enable I/O

IO1

Enable input

Enable output

Enable input

EIO2

325

Enable I/O

IO2

Enable input: The enable input of the first IC is

connected to the GND and another is connected to the

enable output of the second IC.

Enable output: Connected to the enable input of the

second IC at cascade output.

DISP

337

341

Disp off Input Grounding DISP sets liquid crystal drive output Y1–Y320

to the VM level.

BS

Bus

Input Switches the number of input bits for the display data.

Select

Vcc 8-bit input mode

GND 4-bit input mode (Captures data from D0–D3. At this

time, connect D4–D7 to the GND.)

MODE 342

MODE Input Switches the number of input bits for the display data.

Vcc 320 output mode

GND 240 output mode (Y41–Y280 are valid output. The

other 80 pins output the not-selected-level signals

synchronized every time; release these pins.)

4

HD66130T

Pin Functions (cont)

Class

Symbol Number Name

I/O

Function

Liquid crystal Y1 to

drive output Y320

1 to 320 Y1 to

Y320

Output Liquid crystal drive output: Selects and outputs level

V0 or V1 according to the combination of the M signal

and display data when DISP is connected to Vcc.

0

1

M

0

1

D

Output level

V0

V1

V0

5

HD66130T

Rearranging Output Data (SHL)

The order for the output of captured data is inverted crosswise according to the SHL signal. At this time,

the input/output pin of the enable signal can be switched.

SHL = GND, BS = GND

Y313

Y315

Y317

Y319

Y320

Y1

Y3

Y5

Y7

Y314

Y316

Y318

Y2

Y4

Y6

Y8

D3 D2 D1 D0 D3 D2 D1 D0

First data

Last data

Enable input: EIO1

Enable output: EIO2

SHL = Vcc, BS = GND

Y1 Y3 Y5

Y313

Y315

Y317

Y319

Y320

Y7

Y314

Y316

Y318

Y2

Y4

Y6

Y8

D0 D1 D2 D3 D0 D1 D2 D3

Last data

First data

Enable input: EIO2

Enable output: EIO1

SHL = GND, BS = Vcc

Y1 Y3 Y5

Y313

Y315

Y317

Y319

Y320

Y7

Y314

Y316

Y318

Y2

Y4

Y6

Y8

D7 D6 D5 D4 D3 D2 D1 D0

First data

Last data

Enable input: EIO1

Enable output: EIO2

SHL = Vcc, BS = Vcc

Y1 Y3 Y5

Y313

Y315

Y317

Y319

Y320

Y7

Y314

Y316

Y318

Y2

Y4

Y6

Y8

D0 D1 D2 D3 D4 D5 D6 D7

Last data

First data

Enable input: EIO2

Enable output: EIO1

6

HD66130T

Operation Timing

(1) 4-bit capture mode (1 line, 640 dots)

Line

CL2

1

2

79 80 81 82

159 160 161

D0

to

d316 d320

d313 d317

d4 d8

d1 d5

D3

CL1

EIO2

(No. 1)

Data capture period

for IC (No. 1)

EIO2

(No. 2)

Data capture period for IC

(No. 2)

Y1–Y320

BS = GND (4-bit capture mode)

During the data standby state when the data capture operation enable signal is low (SHL = GND: EIO1),

the next data capture clock (CL2) cancels the standby state. The 4-bit data is captured at the fall of CL2.

When 316 bits are captured, the enable signal becomes the GND level (SHL = GND: EIO2). When 320

bits are captured, the operation automatically stops (the standby state is entered). The second IC is then

activated when pin EIO2 is connected to pin EIO1 of the second IC.

Data output changes at the fall of CL1.

During SHL = GND, captured data d1 and d320 are output to Y1 and Y320, respectively. During SHL =

Vcc, data d1 and d320 are output to Y320 and Y1, respectively.

7

HD66130T

(2) 8-bit capture mode (1 line, 640 dots)

Line

CL2

1

2

39 40 41 42

79 80

d312 d320

d305 d313

d8 d16

d1 d9

D0

to

D7

CL1

EIO2

(No. 1)

Data capture period

for IC (No. 1)

EIO2

(No. 2)

Data capture period for

IC (No. 2)

Y1–Y320

BS = Vcc (8-bit capture mode)

The 8-bit display data is captured at the fall of CL2. Other basic operations are the same as those of the 4-

bit capture mode.

8

HD66130T

Application Example

VLL, R

VML, R

VHL, R

VLCDL, R

VEEL, R

DIO1

DISP

SHL

MWS4–0

M

COM1

COM2

COM3

COM4

COM5

LCD Panel

640 x 240

1/240 duty

GND

CL

Vcc

MODE

COM236

COM237

COM238

COM239

COM240

VLCD

VH (COM)

Vcc

Y320 to Y1

HD66130T

Y320 to Y1

HD66130T

V0 (SEG)

VM

V1 (SEG)

GND

VL (COM)

VEE

Controller

Notes:

1. When designing the board, connect a capacitor near the IC to stabilize power supply. Use two capacitors of about

0.1 µF for each IC (between Vcc and GND, V0 and GND, VLCD and GND, and V_EEand GND).

2. In addition, for the power supply circuit, connect a capacitor of several µF or several tens of µF between the liquid

crystal power supply and GND. For set evaluation, confirm that there is no inversion of liquid crystal drive power

supply and level power supply in the period between when the liquid crystal drive power supply is turned on and

when it is turned off.

3. Configuring the LCD panel using the HD66130 when using the select COMMON driver.

The select COMMON driver

COMMON driver

select

HD66131 (240OUT)

HD66133 (120OUT)

HD66135 (120OUT)

●

×

●

9

HD66130T

Absolute Maximum Ratings

Item

Symbol

V_CC

Rating

Unit

V

Notes

1, 4

Power supply voltage for logic circuits

Power supply voltage for LCD drive circuits

Input voltage 1

–0.3 to + 7.0

–0.3 to V_CC+ 0.3

–0.3 to V0 + 0.3

–30 to +75

V0

V

1, 4

VT1

VT2

T_opr

V

1, 2

Input voltage 2

V

1, 3, 4

Operating temperature

Storage temperature

°C

T_stg

–55 to +110

Notes: 1. Potential from the GND

2. Applied to pins SHL, EIO1, EIO2, DISP, D0 to D7, CL1, CL2, M, BS, and MODE.

3. Applied to VML, VMR, V1L, and VMR.

Operating the LSI in excess of the absolute maximum rating will result in permanent damage.

Use the LSI observing electrical characteristic conditions in normal operation. Exceeding the

conditions will cause malfunctions or will affect LSI reliability.

4. Conform to the following turn-on/off sequence of the power and signals. Otherwise, the LSI will

malfunction or will be permanently damaged. In addition, LSI reliability will be affected.

Vcc

V0

2.7 V

0ms

VM

V1

VM

V1

0ms

DISP

Input-signal

clock data

Signal-undefined Initialization period

period (at least one frame)

(0 ms: Minimum value)

10

HD66130T

4.1 Turning on the power

1) Turn on the power in the order of GND- V_CC, GND-V0, and VM/V1. Then, ground the DISP pin.

2) The LCD forcibly outputs the VM level by the DISPOFF function.

3) Even if an input signal is disturbed immediately after V_CCis applied, the DISPOFF function has priority.

4) Input the specific signal to initialize registers in the driver. The initialization period must be at least one

frame.

5) The preparation of normal display is completed. Input the V_CClevel to the DISP pin to cancel the

DISPOFF function. At this time, the level of pins V0, VM, and V1 must rise to the specific potential.

4.2 Turning off the power

The procedure is basically the reverse for turning on the power.

1) Ground the DISP pin.

2) Turn off the liquid crystal power in the order of VM/V1 and GND-V0.

3) Ground V_CCand an input signal.

At this time, the level of pins V0, VM, and V1 must fall to 0 V. Since the DISPOFF function stops when

V_CCfalls to 0 V, the LCD may output a level other than VM. Therefore, a display failure may occur when

the power is turned off or on.

11

HD66130T

Electrical Characteristics

DC Characteristics 1 (V_CC= 2.5 to 4.5V, V0–GND = 2.6 to 5.5V, Ta = –30 to +75°C)

Item

Symbol Pins

Min

Typ Max

Unit Test Condition

Notes

Input high voltage

VIH

CL1,

CL2,

SHL,

M,

0.8 × V_CC

—

V_CC

V

EIO1,

EIO2,

Input low voltage

VIL

MODE, 0

DISP,

D0 to

—

0.2 × V_CC

V

D7, BS

Output high voltage

Output low voltage

Vi–Yj on resistance

VOH

VOL

R_ON

EIO1, V_CC–0.4

—

V

I_OH= –0.4 mA

I_OL= 0.4 mA

EIO2

EIO1,

—

0.4

V

EIO2

Y1 to

0.7 2.0

2.0 3.0

0.7 2.0

5.0

kΩ

I

_ON= 150 µA

1

Y320,

V0L, R

Y1 to

—

kΩ

Y320,

VML, R

Y1 to

—

Y320,

V1L, R

Input leakage current 1

I_IL1

CL1,

–5.0

µA VIN = V_CCto GND

CL2,

SHL,

M,

EIO1,

EIO2,

MODE,

DISP,

D0 to

D7, BS

Input leakage current 2

I_IL2

VML, –25

R,

25

µA VIN = V0 to GND

V1L, R

Current consumption 1

Current consumption 2

Current consumption 3

I_CC

IV0

I_ST

V_CC

V0L, R —

V_CC

—

150 300

60 200

50 100

µA V_CC= 3.3 V

2

V0 = 2.7 V

µA f_CL2= 3.5 MHz

f

_CL1= 19.2 kHz

—

µA fM = 1.5 kHz

2, 3

12

HD66130T

DC Characteristics 2 (V_CC= 4.5 to 5.5V, V0–GND = 2.6 to 5.5V, Ta = –30 to +75°C)

Item

Symbol Pins

Min

Typ Max

Unit Test Condition

Notes

Input high voltage

VIH

CL1,

CL2,

SHL,

M,

0.8 × V_CC

—

V_CC

V

EIO1,

EIO2,

Input low voltage

VIL

MODE, 0

DISP,

D0 to

—

0.2 × V_CC

V

D7, BS

Output high voltage

Output low voltage

Vi–Yj on resistance

VOH

VOL

R_ON

EIO1, V_CC–0.4

—

V

I_OH= –0.4 mA

I_OL= 0.4 mA

EIO2

EIO1,

—

0.4

V

EIO2

Y1 to

0.7 2.0

2.0 3.0

0.7 2.0

5.0

kΩ

I

_ON= 150 µA

1

Y320,

V0L, R

Y1 to

—

kΩ

Y320,

VML, R

Y1 to

—

Y320,

V1L, R

Input leakage current 1

I_IL1

CL1,

–5.0

µA VIN = V_CCto GND

CL2,

SHL,

M,

EIO1,

EIO2,

MODE,

DISP,

D0 to

D7, BS

Input leakage current 2

I_IL2

VML, –25

R,

25

µA VIN = V0 to GND

V1L, R

Current consumption 1

Current consumption 2

Current consumption 3

I_CC

IV0

I_ST

V_CC

V0L, R —

V_CC

—

230 450

60 200

80 150

µA V_CC= 5.0 V

2

V0 = 2.7 V

µA f_CL2= 3.5 MHz

f

_CL1= 19.2 kHz

—

µA fM = 1.5 kHz

2, 3

Notes: 1. Resistance between pins Y and V when a load current flows to one of the pins from Y1 to Y320.

The following conditions are defined:

V0–GND = 5.5 V

VM = (V0 + V1)/2

13

HD66130T

V1 = GND + 1.0

The voltage range of the liquid crystal drive level power supply is described. A voltage around

the GND is applied to pin V1, and an intermediate voltage of about V0 and V1 is applied to pin

VM. Use the V1 in the range of ∆V = 0.25 x V0, in which the impedance Ron of driver output is

stable.

V0

VM

∆V = 0.25 x V0

V1

GND

Relationship between the driver output waveform and each level voltage

2. A current flowing in the input or output section is excluded. If an input signal is at an

intermediate level for the CMOS, a through-current flows in the input circuit and power supply

current increases. Therefore, VIH must be at the Vcc level and VIL must be at the GND level.

3. Current at standby

4. The voltage of each signal is shown below.

Segment

voltage

Common

voltage

Segment waveform

Common waveform

VH (23.0 V)

V0 (5.0 V)

Vcc (3.3 V)

VM (3.0 V)

Vcc (3.3 V)

VM (3.0 V)

V1 (1.0 V)

GND (0.0 V)

VL (–17.0 V)

Display-off

period

Display-off

period

Normal display period

14

HD66130T

AC Characteristics 1 (V_CC= 2.5 to 4.5V, V0–GND = 2.6 to 5.5V, Ta = –30 to +75°C)

Item

Symbol

t_CYC

t_CWH2

t_CWL2

t_CWH1

t_SCL

t_HCL

t_r

Pins

Min

152

65

80

—

Max

—

Unit

ns

Clock cycle time

Clock high pulse width 1

Clock low pulse width 1

Clock high pulse width 2

Clock setup time

Clock hold time

Clock rise time

CL2

—

CL2

—

CL1

—

CL1, CL2

D0 to D7, CL2

M, CL1

—

30

—

Clock fall time

t_f

—

Data setup time

Data hold time

t_DS

50

20

—

t_DH

—

M setup time

t_MS

—

M hold time

t_MH

M, CL1

—

Output delay time 1

t_pd1

CL1, Y1 to Y320

1000

AC Characteristics 2 (V_CC= 4.5V to 5.5V, V0–GND = 2.6 to 5.5V, Ta = –30 to +75°C)

Item

Symbol

t_CYC

t_CWH2

t_CWL2

t_CWH1

t_SCL

t_HCL

t_r

Pins

Min

125

45

80

—

Max

—

Unit

ns

Clock cycle time

Clock high pulse width 1

Clock low pulse width 1

Clock high pulse width 2

Clock setup time

Clock hold time

Clock rise time

CL2

—

CL2

—

CL1

—

CL1, CL2

D0 to D7, CL2

M, CL1

—

20

—

Clock fall time

t_f

—

Data setup time

Data hold time

t_DS

20

—

t_DH

—

M setup time

t_MS

—

M hold time

t_MH

M, CL1

—

Output delay time 1

t_pd1

CL1, Y1 to Y320

1000

Notes: 1. A load must be 10 pF or less for EI/O connection between drivers.

2. For output delay time 1 and 2, connect the load circuit shown below.

Test point

100 pF

15

HD66130T

tr

t_CWH2

tf

t_CWL2

t_CYC

0.8 Vcc

CL2

0.2 Vcc

t_DS

t_DH

0.8 Vcc

0.2 Vcc

D0–7

t_CWH1

0.8 Vcc

0.2 Vcc

CL1

CL2

t_SCL

t_HCL

0.2 Vcc

t_MS

t_MH

0.8 Vcc

0.2 Vcc

M

CL1

0.2 Vcc

t_pd1

0.8 V0

0.2 V1

Y (n)

16


型号：	HD66130
厂家：	HITACHI SEMICONDUCTOR
描述：	320-channel Low-voltage Segment Driver for Dot-Matrix STN Liquid Crystal Display 对于点阵STN液晶显示器320路低压段驱动器驱动器显示器
文件：	总16页 (文件大小：66K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HD66130 [HITACHI]

相关型号：

HD66130T

HD66131ST

HD66132T

HD66133T

HD66134ST

HD66135T

HD66137

HD66137T

HD66204

HD66204F

HD66204FL

HD66204TF