HD74AC195FP [HITACHI]
Parallel In Parallel Out, AC Series, 4-Bit, Right Direction, True Output, CMOS, PDSO16, FP-16DA;型号: | HD74AC195FP |
厂家: | HITACHI SEMICONDUCTOR |
描述: | Parallel In Parallel Out, AC Series, 4-Bit, Right Direction, True Output, CMOS, PDSO16, FP-16DA 输入元件 光电二极管 输出元件 逻辑集成电路 触发器 |
文件: | 总9页 (文件大小:63K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HD74AC195
4-bit Parallel-Access Shift Register
ADE-205-380 (Z)
1st. Edition
Sep. 2000
Description
This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a
direct overriding clear. This shift register can operate in two modes: Parallel load; Shift from Q0 towards
Q3.
Parallel loading is accomplished by applying the four bits of data, and taking the PE Input low. The data is
loaded into the associated flip-flops and appears at the outputs after the positive transition of the CP input.
During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the PE
input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to
perform as a J-K or toggle flip-flop as shown in the function table.
Features
•
•
•
•
•
Shift Right and Parallel Load Capability
J-K (D-Type) Inputs to First Stage
Complement Output from Last Stage
Asynchronous Master Reset
Outputs Source/Sink 24 mA
HD74AC195
Pin Arrangement
1
2
3
4
5
16 VCC
15 Q0
MR
J
K
14
13
Q1
Q2
D0
D1
12 Q3
11 Q3
10 CP
D2 6
7
8
D3
GND
9
PE
(Top view)
Logic Symbol
PE D0
D1
Q1
D2
D3
Q3
J
CP
Q3
K
MR Q0
Q2
Pin Names
CP
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
D0 to D3
PE
Parallel Enable Input
MR
J, K
Q0 to Q3, Q3
Asynchronous Master Reset
J-K or D Type Serial Inputs
Outputs
2
HD74AC195
Timing Diagram
CP
MR
J
K
PE
H
L
D0
D1
D2
H
L
D3
Q0
Q1
Q2
Q3
Serial Shift
Serial Shift
Clear
Load
Mode Select-Function Table
Inputs
Outputs
Operating Modes
MR
L
CP
PE
X
J
K
X
H
L
Dn
Q0
L
Q1
Q2
L
Q3
L
Q3
H
Asynchronous Reset
Shift, Set First Stage
Shift, Reset First Stage
Shift, Toggle First Stage
Shift, Retain First Stage
Parallel Load
X
X
H
L
X
X
X
X
X
dn
L
H
H
H
H
H
L
H
L
q0
q0
q0
q0
d1
q1
q1
q1
q1
d2
q2
q2
q2
q2
d3
q2
q2
q2
q2
d3
H
H
H
L
L
q0
q0
d0
H
H
X
H
X
H :
HIGH Voltage Level
LOW Voltage Level
Immaterial
L
:
:
X
Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-
HIGH transition.
:
LOW-to-HIGH clock transition.
3
HD74AC195
Logic Diagram
K
VCC
J
D3
D2
D1
D0
VCC
PE
CP
MR
Q3
Q3
Q2
Q1
Q0
DC Characteristics (unless otherwise specified)
Item
Symbol Max
Unit
Condition
Maximum quiescent supply current
ICC
80
µA
VIN = VCC or ground, VCC = 5.5 V,
Ta = Worst case
Maximum quiescent supply current
ICC
8.0
µA
VIN = VCC or ground, VCC = 5.5 V,
Ta = 25°C
4
HD74AC195
AC Characteristics: HD74AC195
Ta = +25°C
Ta = –40°C to +85°C
CL = 50 pF
CL = 50 pF
Min
65
Item
Symbol VCC (V)*1
Min
75
Typ
Max
—
Max
—
Unit
Maximum clock
frequency
fmax
tPLH
tPHL
tPLH
tPHL
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
—
MHz
100
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
—
—
85
—
Propagation delay
CP to Qn or Q3
Propagation delay
CP to Qn or Q2
Propagation delay
MR to Q2
9.0
5.5
9.0
6.5
7.5
5.5
6.0
5.0
13.0
10.0
13.0
10.0
10.5
8.0
1.0
15.0
11.5
15.0
11.5
12.0
9.5
ns
ns
ns
ns
1.0
1.0
1.0
1.0
1.0
Propagaion delay
MR to Qn
9.0
1.0
10.5
8.0
7.0
1.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements: HD74AC195
Ta = –40°C
to +85°C
Ta = +25°C
CL = 50 pF
CL = 50 pF
Item
Symbol VCC (V)*1 Typ
Guaranteed Minimum
Unit
Setup time, HIGH or LOW
J, K or Dn to CP
Hold time, HIGH or LOW
J, K or Dn to CP
Setup time, HIGH or LOW
PE to CP
tsu
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.0
5.5
4.0
2.0
1.5
5.0
4.0
0.0
0.0
0.5
0.5
5.5
4.5
7.0
5.0
3.6
2.0
7.0
5.0
0.0
0.0
0.5
0.5
7.0
5.0
ns
ns
ns
ns
ns
ns
2.0
th
–0.5
0.5
tsu
3.5
2.5
Hold time, HIGH or LOW
PE to CP
th
–2.0
–1.5
–1.5
–1.0
–3.0
–3.0
Recovery time
trec
MR to CP
Pulse width
tw
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
5
HD74AC195
Capacitance
Item
Symbol
CIN
Typ
4.5
Unit
pF
Condition
VCC = 5.5 V
VCC = 5.0 V
Input capacitance
Power dissipation capacitance
CPD
125
pF
6
HD74AC195
Package Dimensions
Unit: mm
19.20
20.00 Max
16
1
9
8
1.3
1.11 Max
7.62
+ 0.13
– 0.05
0.25
2.54 ± 0.25
0.48 ± 0.10
0° – 15°
Hitachi Code
DP-16
JEDEC
EIAJ
Mass (reference value)
Conforms
Conforms
1.07 g
Unit: mm
10.06
10.5 Max
9
8
16
1
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0° – 8°
1.27
0.70 ± 0.20
*0.42 ± 0.08
0.40 ± 0.06
0.15
M
0.12
Hitachi Code
JEDEC
FP-16DA
—
EIAJ
Conforms
0.24 g
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
7
HD74AC195
Unit: mm
9.9
10.3 Max
9
16
1
8
1.27
+ 0.10
6.10
– 0.30
1.08
0.635 Max
0° – 8°
+ 0.67
0.60
– 0.20
*0.42 ± 0.08
0.40 ± 0.06
0.15
0.25
M
Hitachi Code
JEDEC
EIAJ
FP-16DN
Conforms
Conforms
0.15 g
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
Unit: mm
5.00
5.30 Max
16
9
1
8
0.65
0.13 M
0.65 Max
1.0
+ 0.08
– 0.07
*0.22
0.20 ± 0.06
6.40 ± 0.20
0° – 8°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
TTP-16DA
—
EIAJ
—
0.05 g
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
8
HD74AC195
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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(Taipei Branch Office)
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Hung-Kuo Building,
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URL : http://www.hitachi.com.tw
Copyright Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
Colophon 2.0
9
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