HD74HC160 [HITACHI]
Synchronous Decade,4-bit Binary,Counter(Direct Clear,Synchronous Clear); 同步十年, 4位二进制,计数器(直接清除,同步清除)型号: | HD74HC160 |
厂家: | HITACHI SEMICONDUCTOR |
描述: | Synchronous Decade,4-bit Binary,Counter(Direct Clear,Synchronous Clear) |
文件: | 总16页 (文件大小:92K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HD74HC160/HD74HC161/
HD74HC162/HD74HC163
Synchronous Decade Counter (Direct Clear)
Synchronous 4-bit Binary Counter (Direct Clear)
Synchronous Decade Counter (Synchronous Clear)
Synchronous 4-bit Binary Counter (Synchronous Clear)
Description
The HD74HC160 and the HD74HC162 are 4 bit decade counters, and the HD74HC161 and the
HD74HC163 are 4 bit binary counters All flip-flops are clocked simultaneously on the low to high to
transition (positive edge) of the clock input waveform.
These counters may be preset using the load input. Presetting of all four flip-flops is synchronous to thte
rising edge of clock. When load is held low counting is disabled and the data on the A, B, C, and D inputs
is loaded into the counter on the rising edge of clock. If the load input is taken high before the positive
edge of clock the count operation will be unaffected.
All of these counters may be cleared by utilizing the clear input. The clear function on the HD74HC162
and HD74HC163 counters are synchronous to the clock. That is, the counters are cleared on the positive
edge of clock while the clear input is held low.
The HD74HC160 and HD74HC161 counters are cleared asynchronously. When the clear is taken low the
counter is cleared immediately regardless of the clock.
Two active high enable inputs Enable P and Enable T and a ripple carry output are provided to enable easy
cascading of counters. Both enable inputs must be high to count. The Enable T input also enables the
Ripple Carry output. When enabled, the Ripple Carry outputs a positive pulse when the counter overflows.
This pulse is approximately equal in duration to the high level portion of the QA outputs. The Ripple Carry
output is fed to successive cascaded stages to facilitate easy implementation of N-bit counters.
Features
•
•
•
•
High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
HD74HC160/HD74HC161/HD74HC162/HD74HC163
•
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs
Outputs
Qn
Clock
Clear*1
Load
Enable P
Enable T
L
X
L
X
X
H
L
X
X
H
X
L
Reset-clear
Load input data
Count
H
H
H
H
H
H
H
No count
No count
X
Note: 1. 162 and 163 Only-160 and 161 are Asynchronous Clear Devices
Decade Counter
HD74HC160P
HD74HC162P
Binary Counter
Asynchronous clear
Synchronous clear
HD74HC161P
HD74HC163P
Pin Arrangement
1
16 VCC
Ripple
Clear
Clock
A
CLR
2
3
4
5
6
7
8
15
CK
Ripple
Carry
Carry Output
QA
A
14 QA
13 QB
12 QC
11 QD
B
C
D
P
QB
B
Data
Inputs
Outputs
C
D
QC
QD
T
10 Enable T
9 Load
Enable P
GND
Load
(Top view)
2
HD74HC160/HD74HC161/HD74HC162/HD74HC163
DC Characteristics
Ta = –40 to
Ta = 25°C
+85°C
Item
Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
Input voltage
VIH
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
1.5
—
—
—
—
0.5
1.5
3.15
4.2
—
—
V
V
V
3.15 —
—
4.2
—
—
—
—
—
—
—
—
VIL
0.5
1.35
1.8
—
1.35 —
1.8
—
—
—
—
—
—
Output voltage
VOH
1.9 2.0
4.4 4.5
5.9 6.0
4.18 —
5.68 —
1.9
4.4
5.9
4.13
5.63
—
Vin = VIH or VIL IOH = –20 µA
—
—
—
IOH = –4 mA
IOH = –5.2 mA
—
VOL
—
—
—
—
—
—
—
0.0 0.1
0.0 0.1
0.0 0.1
0.1
0.1
0.1
0.33
0.33
V
Vin = VIH or VIL IOL = 20 µA
—
—
—
—
—
—
0.26 —
0.26 —
±0.1 —
4.0
IOL = 4 mA
IOL = 5.2 mA
Input current
Iin
±1.0 µA
40 µA
Vin = VCC or GND
Quiescent supply ICC
current
—
Vin = VCC or GND, Iout = 0 µA
3
HD74HC160/HD74HC161/HD74HC162/HD74HC163
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = –40 to
Ta = 25°C
+85°C
Item
Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
Maximum clock
frequency
fmax
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
—
—
—
4
MHz
25
29
20
23
Propagation delay tPLH
160 —
200 ns
Clock to Q
time
tPHL
18 32
—
—
40
—
—
27
34
225 —
280 ns
Clear to Q
23 45
—
—
56
(HC160, HC161 only)
—
—
38
48
150 —
190 ns
Enable T to Ripple Carry output
Clock to Ripple carry output
Data to Clock
15 30
—
—
38
—
—
26
33
200 —
250 ns
16 40
—
50
43
—
34
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Setup time
tsu
125 —
156
31
26
156
31
26
156
31
26
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
25
21
9
—
125 —
25 15
Load to Clock
21
—
125 —
Clear to Clock
25
21
0
—
—
—
–7
—
(HC162, HC163 only)
Hold time
th
ns
ns
0
0
0
0
Removal time
trem
100 —
125
25
21
20
17
7
—
4
HD74HC160/HD74HC161/HD74HC162/HD74HC163
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont)
Ta = –40 to
Ta = 25°C
+85°C
Item
Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
Pulse width
tw
2.0
4.5
6.0
2.0
4.5
6.0
—
80
16
14
—
—
—
—
—
6
—
—
—
75
15
13
10
100
20
17
—
—
—
—
95
19
16
10
ns
ns
pF
—
—
5
Output rise/fall
time
tTLH
tTHL
—
—
5
—
Input capacitance Cin
—
Function Table
Count Enable/Disable
Control Inputs
Result at Outputs
Load
Enable P
Enable T
QA to QD
Count
Ripple Carry Output
H
L
H
H
L
H
H
H
L
High when QA to QD are maximum
No count
No count
No count
No count
X
X
X
High when QA to QD are maximum
H
L
L
L
L
5
HD74HC160/HD74HC161/HD74HC162/HD74HC163
Timing Diagram
HD74HC160/HD74HC162
Sequence illustrated in waveforms.
1. Clear outputs to zero.
2. Preset to BCD seven.
3. Count to eight, nine, zero, one, two and three.
4. Inhibit
Clear(HC160)
Clear(HC162)
Load
(Asynchronous)
(Synchronous)
A
B
Data
Inputs
C
D
Clock(HC160)
Clock(HC162)
Enable P
Count
Enables
Enable T
QA
QB
QC
Outputs
QD
Ripple
Carry
Output
7
8
9
0
1
2
3
Count
Inhibit
Clear Load
6
HD74HC160/HD74HC161/HD74HC162/HD74HC163
HD74HC161/HD74HC163
Sequence illustrated in waveforms.
1. Clear outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one and two.
4. Inhibit
Clear(HC161)
Clear(HC163)
Load
(Asynchronous)
(Synchronous)
A
B
Data
Inputs
C
D
Clock(HC161)
Clock(HC163)
Enable P
Count
Enables
Enable T
QA
QB
QC
Outputs
QD
Ripple
Carry
Output
12 13 14 15
0
1
2
Count
Inhibit
Clear Load
7
HD74HC160/HD74HC161/HD74HC162/HD74HC163
Logic Diagram
HD74HC160
Decade Counter with Asynchronous Clear
T1
CLR
C
QA
QB
QC
QD
QA
C
Load
Load
P1
QA
A
B
C
D
T2
CLR
C
C
Load
Load
P2
QB
QB
T3
CLR
C
C
Load
Load
P3
QC
QC
T4
CLR
C
QD
C
Load
Load
P4
QD
V
CC
Enable P
Ripple
Carry
Output
Enable T
CLR
Clear
C
C
Clock
Load
Load
Load
8
HD74HC160/HD74HC161/HD74HC162/HD74HC163
HD74HC161
4-bit Binary Counter with Asynchronous Clear
T1
CLR
C
QA
QB
QC
QD
QA
C
Load
Load
P1
QA
A
B
C
D
T2
CLR
C
C
Load
Load
P2
QB
QB
T3
CLR
C
C
Load
Load
P3
QC
QC
T4
CLR
C
QD
C
Load
Load
P4
QD
Enable P
Enable T
Clear
Ripple
Carry
Output
CLR
C
C
Clock
Load
Load
Load
9
HD74HC160/HD74HC161/HD74HC162/HD74HC163
HD74HC162
Decade Counter with Synchronous Clear
T
Q
QA
QB
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
Q
IN
A
B
T
Q
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
Q
IN
T
Q
QC
QD
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
Q
IN
C
T
Q
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
Q
IN
D
VCC
P
T
RCO
CK
CK
CK
LD
LD
LD
LD·CLR
LD·CLR
CLR
CLR
CLR
10
HD74HC160/HD74HC161/HD74HC162/HD74HC163
HD74HC163
4-bit Binary Counter with Synchronous Clear
T
Q
QA
QB
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
Q
IN
A
B
T
Q
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
Q
IN
T
Q
QC
QD
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
Q
IN
C
T
Q
CR
CR
LD
LD
LD·CLR
LD·CLR
CLR
CLR
Q
IN
D
P
T
RCO
CK
CK
CK
LD
LD
LD
LD·CLR
LD·CLR
CLR
CLR
CLR
11
Unit: mm
19.20
20.00 Max
16
1
9
8
1.3
1.11 Max
7.62
+ 0.13
– 0.05
0.25
2.54 ± 0.25
0.48 ± 0.10
0° – 15°
Hitachi Code
DP-16
JEDEC
EIAJ
Conforms
Conforms
Weight (reference value) 1.07 g
Unit: mm
10.06
10.5 Max
9
16
1
8
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0° – 8°
1.27
0.70 ± 0.20
*0.42 ± 0.08
0.40 ± 0.06
0.15
M
0.12
Hitachi Code
JEDEC
EIAJ
FP-16DA
—
Conforms
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.24 g
Unit: mm
9.9
10.3 Max
9
16
1
8
1.27
+ 0.10
6.10
– 0.30
1.08
0.635 Max
0° – 8°
+ 0.67
0.60
– 0.20
*0.42 ± 0.08
0.40 ± 0.06
0.15
0.25
M
Hitachi Code
JEDEC
EIAJ
FP-16DN
Conforms
Conforms
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.15 g
Unit: mm
5.00
5.30 Max
16
9
1
8
0.65
0.13 M
0.65 Max
1.0
+ 0.08
– 0.07
*0.22
0.20 ± 0.06
6.40 ± 0.20
0° – 8°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
EIAJ
TTP-16DA
—
—
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.05 g
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Semiconductor & Integrated Circuits.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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For further information write to:
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(America) Inc.
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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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