HM511664CJ-8 [HITACHI]
Fast Page DRAM, 64KX16, 80ns, CMOS, PDSO40, 0.400 INCH, PLASTIC, SOJ-40;
| 型号： | HM511664CJ-8 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Fast Page DRAM, 64KX16, 80ns, CMOS, PDSO40, 0.400 INCH, PLASTIC, SOJ-40 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总26页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM511664C Series
1M FP DRAM (64-kword × 16-bit)
256 refresh
ADE-203-627A (Z)
Rev. 1.0
Dec. 20, 1997
Description
The Hitachi HM511664C Series is a CMOS dynamic RAM organized 65,536-word × 16-bit. HM511664C
Series has realized higher density, higher performance and various functions by employing 0.8 µm CMOS
process technology and some new CMOS circuit design technologies. The HM511664C Series offers Fast
Page Mode as a high speed access mode. Multiplexed address input permits the HM511664C to be
packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII.
Features
•
•
•
Single 5 V supply: 5 V ± 10%
Access time: 60 ns/70 ns/80 ns (max)
Power dissipation
Active mode: 660 mW/ 633 mW/495 mW (max)
Standby mode: 11 mW (max)
Fast page mode capability
Refresh cycles
•
•
256 refresh cycles: 4 ms
2 variations of refresh
•
•
RAS-only refresh
CAS-before-RAS refresh
2WE-byte control
HM511664C Series
Ordering Information
Type No.
Access time
Package
HM511664CJ-6
HM511664CJ-7
HM511664CJ-8
60 ns
70 ns
80 ns
400-mil 40-pin plastic SOJ (CP-40D)
HM511664CTT-6
HM511664CTT-7
HM511664CTT-8
60 ns
70 ns
80 ns
400-mil 44-pin plastic TSOPII (TTP-44/40DA)
Pin Arrangement
HM511664CJ Series
HM511664CTT Series
VCC
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
NC
VSS
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
I/O16
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
VSS
I/O16
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
NC
VCC
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
NC
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2
3
4
5
6
7
8
NC
9
10
11
12
13
14
15
16
17
18
19
20
VSS
CAS
OE
VCC
UWE
LWE
RAS
A0
VCC
UWE
LWE
RAS
A0
VSS
CAS
OE
NC
NC
NC
A7
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A1
A1
A7
A2
A2
A6
A3
A3
A6
A5
A4
A4
A5
VSS
VCC
VCC
VSS
(Top view)
(Top view)
2
HM511664C Series
Pin Description
Pin name
Function
Address input
A0 to A7
•
•
•
Row address A0 to A7
Refresh address
Column address
A0 to A7
A0 to A7
I/O1 to I/O16
RAS
Data-in/data-out
Row address strobe
Column address strobe
Read/write enable
Output enable
CAS
UWE, LWE
OE
VCC
Power supply
VSS
Ground
NC
No connection
Block Diagram
RAS
CAS UWE LWE
OE
Timing and control
Column decoder
A0
64k array
64k array
64k array
64k array
64k array
64k array
64k array
64k array
64k array
64k array
64k array
64k array
64k array
64k array
64k array
64k array
Column
address
buffers
A1
•
•
•
to
A7
I/O1
to
I/O16
I/O buffers
•
•
•
Row
address
buffers
3
HM511664C Series
Operation Table
The HM511664C series has the following 10 operation modes.
1. Read cycle
2. Early write cycle
3. Delayed write cycle
4. Read-modify-write cycle
5. RAS-only refresh cycle
6. CAS-before-RAS refresh cycle
7. Fast page mode read cycle
8. Fast page mode early write cycle
9. Fast page mode delayed write cycle
10. Fast page mode read-modify-write cycle
Inputs
RAS
CAS
UWE
D
LWE
D
Output
Open
Valid
Operation
Standby
H
H
H
L
H
H
Standby
L
L
H
L*2
H
L*2
Valid
Read cycle
Early write cycle
L
L
Open
L
L
L*2
L*2
Undefined Delayed write cycle
L
L
H to L
D
H to L
D
Valid
Open
Open
Valid
Open
Read-modify-write cycle
L
H
RAS-only refresh cycle
H to L
L
D
D
CAS-before-RAS refresh cycle
Fast page mode read cycle
Fast page mode early write cycle
L
L
L
L
H to L
H to L
H to L
H to L
H
L*2
L*2
H
L*2
L*2
Undefined Fast page mode delayed write cycle
Valid Fast page mode read modify-write cycle
H to L
H to L
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. tWCS ≥ 0 ns Early write cycle
tWCS < 0 ns Delayed write cycle
3. Mode is determined by the OR function of the UWE and LWE. (Mode is set by the earliest of
UWE and LWE active edge and reset by the latest of UWE and LWE inactive edge.) However
write OPERATION and output High-Z control are done independently by each UWE, LWE.
4
HM511664C Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +7.0
–1.0 to +7.0
50
VCC
V
Iout
PT
mA
W
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VSS
Min
0
Typ
0
Max
0
Unit
V
Notes
Supply voltage
2
VCC
4.5
2.4
–0.5
–1.0
5.0
—
5.5
6.5
0.8
0.8
V
1, 2
1
Input high voltage
Input low voltage
VIH
V
(I/O pin)
(Others)
VIL
—
V
1
VIL
—
V
1
Notes: 1. All voltage referred to VSS.
2. The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
5
HM511664C Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V) *4
HM511664C
-6
-7
-8
Parameter
Symbol Min
Max Min
Max Min
Max Unit Test conditions
Operating current*1, ICC1
*
—
120
—
115
—
90
mA
RAS cycling
CAS cycling, tRC = min
2
Standby current
ICC2
—
2
—
2
—
2
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
1
—
1
—
1
mA
CMOS interface
RAS, CAS, UWE, LWE,
OE ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh
ICC3
ICC5
ICC6
ICC7
ILI
—
120
5
—
115
5
—
90
5
mA
mA
mA
mA
µA
tRC = min
current*2
Standby current*1
—
—
—
RAS = VIH, CAS = VIL,
Dout = enable
CAS-before-RAS
—
120
120
10
—
115
115
10
—
90
90
10
10
tRC = min
refresh current*2
Fast page mode
current*1, *3
—
—
—
tPC = min
Input leakage
current
–10
–10
–10
–10
–10
–10
0 V ≤ Vin ≤ 6.5 V
Output leakage
current
ILO
10
10
µA
0 V ≤ Vout ≤ 6.5 V
Dout = disable
Output high voltage VOH
Output low voltage VOL
2.4
0
VCC
0.4
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
High Iout = –2.5 mA
Low Iout = 2.1 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed twice or less while RAS = VIL.
3. Address can be changed twice or less while CAS = VIH.
4. All the VCC pins should be supplied with the same voltage. And all the VSS pins should be
supplied with the same voltage.
6
HM511664C Series
Capacitance (Ta = +25°C, VCC = 5 V ±10%)
Parameter
Symbol
CI1
Typ
—
Max
5
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (Data-in, Data-out)
1
CI2
—
7
pF
1
CI/O
—
10
pF
1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)*1, *14, *15, *17, *18
Test Conditions
•
•
•
•
Input rise and fall time : 5 ns
Input levels: VIL = 0 V, VIH = 3.0 V
Input timing reference levels : 0.8 V, 2.4 V
Output load : 1 TTL gate + CL (50 pF) (Including scope and jig)
7
HM511664C Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM511664C
-6
-7
-8
Parameter
Symbol
tRC
Min
105
40
60
15
0
Max Min
Max Min
Max Unit Notes
Random read or write cycle time
RAS precharge time
RAS pulse width
—
—
125
50
—
—
145
60
—
—
ns
ns
tRP
tRAS
10000 70
10000 20
10000 80
10000 20
10000 ns
10000 ns
23
CAS pulse width
tCAS
22, 24
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
tASR
—
—
—
—
45
30
—
—
—
—
—
—
50
4
0
—
—
—
—
50
35
—
—
—
—
—
—
50
4
0
—
—
—
—
60
40
—
—
—
—
—
—
50
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tRAH
tASC
tCAH
tRCD
10
0
10
0
10
0
15
20
15
15
60
10
15
0
15
20
15
20
70
10
15
0
15
20
15
20
80
10
15
0
8
9
RAS to column address delay time tRAD
RAS hold time
tRSH
tCSH
tCRP
tODD
tDZO
tDZC
tT
CAS hold time
25
CAS to RAS precharge time
OE to Din delay time
OE delay time from Din
CAS setup time from Din
Transition time (rise and fall)
Refresh period
0
0
0
3
3
3
7
tREF
—
—
—
8
HM511664C Series
Read Cycle
HM511664C
-6
-7
Min
—
—
—
—
0
-8
Min Max
Parameter
Symbol Min Max
Max
70
20
35
20
—
Unit Notes
Access time from RAS
Access time from CAS
Access time from address
Access time from OE
Read command setup time
tRAC
tCAC
tAA
—
—
—
—
0
60
15
30
15
—
—
—
—
15
15
—
—
—
—
—
0
80
20
40
20
—
—
—
—
15
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2, 3
3, 4, 13
3, 5, 13
22
tOAC
tRCS
20
Read command hold time to CAS tRCH
Read command hold time to RAS tRRH
Column address to RAS lead time tRAL
0
0
—
0
16, 19
16, 19
0
0
—
0
30
0
35
0
—
40
0
Output buffer turn-off time
Output buffer turn-off time to OE
CAS to Din delay time
tOFF1
tOFF2
tCDD
15
15
—
6
6
0
0
0
15
15
15
Write Cycle
HM511664C
-6
-7
-8
Parameter
Symbol Min Max
Min
0
Max
—
—
—
—
—
—
—
0
Min Max
Unit Notes
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
tWCS
tWCH
tWP
0
—
—
—
—
—
—
—
0
0
—
—
—
—
—
—
—
0
ns
ns
ns
ns
ns
ns
ns
ns
10, 19
20
10
10
20
10
0
13
13
20
13
0
15
15
20
15
0
21
tRWL
tCWL
tDS
21
21
11, 21
11, 21
22
Data-in hold time
tDH
10
—
13
—
15
—
CAS to OE delay time
tCOD
9
HM511664C Series
Read-Modify-Write Cycle
HM511664C
-6
-7
-8
Parameter
Symbol Min Max
Min
165
90
Max
—
Min Max
Unit Notes
Read-modify-write cycle time
RAS to WE delay time
CAS to WE delay time
tRWC
tRWD
tCWD
135
77
32
47
15
—
—
—
—
—
185
102
42
—
—
—
—
—
ns
—
ns
ns
ns
ns
10, 19
10, 19
10, 19
21
38
—
Column address to WE delay time tAWD
55
—
62
OE hold time from WE
tOEH
18
—
20
Refresh Cycle
HM511664C
-6
-7
-8
Parameter
Symbol Min Max
Min
10
10
10
10
Max
—
Min Max
Unit Notes
CAS setup time (CBR refresh cycle) tCSR
CAS hold time (CBR refresh cycle) tCHR
10
10
10
10
—
—
—
—
10
10
10
10
—
—
—
—
ns
ns
ns
ns
—
RAS precharge to CAS hold time
tRPC
tCPN
—
CAS precharge time in normal
mode
—
Fast Page Mode Cycle
HM511664C
-6
-7
-8
Parameter
Symbol Min Max
Min
45
10
Max
—
Min Max
Unit Notes
Fast page mode cycle time
tPC
tCP
40
10
—
—
50
10
—
—
ns
ns
Fast page mode CAS precharge
time
—
Fast page mode RAS pulse width tRASC
60
—
35
100000 70
100000 80
100000 ns
12
Access time from CAS precharge
tACP
35
—
—
40
—
—
45
—
ns
ns
3, 13
RAS hold time from CAS
precharge
tRHCP
40
45
10
HM511664C Series
Fast Page Mode Read-Modify-Write Cycle
HM511664C
-6
-7
-8
Min Max
Parameter
Symbol Min Max
Min
95
Max
Unit Notes
Fast page mode read-modify-write tPCM
cycle time
80
—
—
100
—
ns
Fast page mode read-modify-write tCPW
cycle CAS precharge to WE delay
time
52
—
60
—
67
—
ns
10, 21
Notes: 1. AC measurements assume tT = 5 ns.
2. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
3. Measured with a load circuit equivalent to 1 TTL loads and 50 pF.
4. Assumes that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max).
5. Assumes that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max).
6. tOFF1 (max), tOFF2 (max) define the time at which the output achieves the open circuit condition and
is not referred to output voltage levels.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH and VIL.
8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
10. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only: if tWCS ≥ tWCS (min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD
(min), tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and
the data output will contain data read from the selected cell; if neither of the above sets of
conditions is satisfied, the condition of the data out (at access time) is indeterminate.
11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading
edge in a delayed write or a read-modify-write cycle.
12. tRASC defines RAS pulse width in Fast page mode cycles.
13. Access time is determined by the longest among tAA, tCAC and tACP
.
14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization
cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter
is used, a minimum of eight CAS-before-RAS refresh cycles is required.
15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to the device.
16. Either tRCH or tRRH must be satisfied for a read cycle.
17.When both UWE and LWE go low at the same time, all 16-bits data are written into the device.
UWE and LWE cannot be staggered within the same write/read cycles.
18. All the VCC and VSS pins shall be supplied with the same voltages.
19. tRCH, tRRH, tWCS, tRWD, tCWD and tAWD are determined by the earlier falling edge of UWE and LWE.
20. tWCH and tRCS are determined by the later rising edge of UWE or LWE.
21. tWP, tRWL, tCWL, tOEH, tDS, tDH and tCPW should be satisfied by both UWE and LWE.
11
HM511664C Series
22. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
23. tRAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle.
24. tCAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle.
25. tCSH(min) can be achieved when tRCD ≤ tCSH(min) – tCAS(min)
26. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
Notes concerning 2WE control
Please do not separate the UWE/LWE operation timing intentionally. However skew between UWE/LWE
are allowed under the following conditions.
(1) Each of the UWE/LWE should satisfy the timing specifications individually.
(2) Different operation mode for upper/lower byte is not allowed; such as following.
RAS
CAS
Delayed write
LWE
Early write
UWE
12
HM511664C Series
Timing Waveforms*26
Read Cycle
t
RC
t
RAS
RAS
t
RP
t
T
t
RSH
t
t
CRP
CAS
t
RCD
t
CSH
CAS
t
t
t
RAL
ASR
RAD
t
t
CAH
t
ASC
RAH
Column
Address
Row
t
t
t
RCH
RRH
RCS
UWE
LWE
t
CAC
t
t
OFF1
AA
High-Z
Dout
Dout
Din
t
RAC
t
OFF2
t
t
t
CDD
OAC
DZC
High-Z
t
ODD
t
DZO
OE
13
HM511664C Series
Early Write Cycle
t
RC
t
RAS
t
RAS
RP
t
T
t
RSH
t
t
RCD
CAS
t
CRP
t
CSH
CAS
t
ASR
t
t
t
ASC
CAH
RAH
Row
Address
Column
t
t
WCH
WCS
UWE
LWE
t
t
DH
DS
Din
Din
High-Z
Dout
14
HM511664C Series
Delayed Write Cycle
t
RC
t
t
RAS
RP
RAS
t
t
CRP
CSH
t
T
t
t
RCD
RSH
t
CAS
CAS
t
t
t
CWL
ASC
ASR
t
RWL
t
RAH
t
CAH
Column
Address
Row
t
t
RCS
WP
UWE
LWE
t
DH
t
DS
Din
Din
t
t
OEH
DZC
t
ODD
t
DZO
High-Z
Dout
*Invalid Dout
t
COD
t
OFF2
OE
* Do not enable Dout during delayed write cycle.
15
HM511664C Series
Read-Modify-Write Cycle
t
RWC
t
RP
t
RAS
RAS
t
t
CRP
T
t
RCD
t
CAS
CAS
t
RAD
t
t
ASR
ASC
t
t
RAH
CAH
Column
t
Address
Row
t
t
CWL
RWL
t
RCS
CWD
t
AWD
t
WP
UWE
LWE
t
AA
t
t
RWD
t
CAC
DH
t
RAC
t
DS
t
DZC
High-Z
Din
Din
Dout
OE
High-Z
Dout
t
OEH
t
OAC
t
t
OFF2
ODD
t
DZO
16
HM511664C Series
RAS-Only Refresh Cycle
t
RC
t
t
RP
RAS
RAS
CAS
t
t
CRP
T
t
CRP
t
RPC
t
RAH
t
ASR
Row
Address
Dout
High-Z
17
HM511664C Series
CAS-Before-RAS Refresh Cycle
t
t
RC
RC
t
t
t
t
RAS
t
RP
RP
RAS
RP
RAS
t
T
t
t
t
t
RPC
CRP
RPC
CPN
t
t
t
t
t
CHR
CSR
CHR
CPN
CSR
CAS
Address
t
OFF1
High-Z
Dout
18
HM511664C Series
Fast Page Mode Read Cycle
t
t
RP
RASC
t
RHCP
RAS
t
t
T
CRP
t
RSH
t
t
PC
CSH
t
CAS
t
t
t
t
t
CP
CAS
RCD
CP
CAS
CAS
t
RAD
t
t
RAL
CAH
t
CAH
t
CAH
t
ASC
t
t
t
RAH
t
ASC
ASR
ASC
Address
Row
Column
Column
Column
t
t
t
t
RRH
RCS
RCS
t
t
t
t
RCH
RCH
RCS
DZC
RCH
UWE
LWE
t
CDD
t
DZC
t
CDD
t
t
DZC
CDD
High-Z
High-Z
High-Z
Din
t
ODD
t
t
CAC
AA
CAC
t
t
ODD
CAC
t
t
t
AA
AA
t
t
t
ACP
ACP
RAC
t
OFF1
t
t
OFF1
OFF1
t
DZO
High-Z
Dout
Dout
Dout
Dout
t
OAC
t
ODD
t
DZO
t
DZO
t
OAC
t
t
OFF2
t
OFF2
OFF2
OE
t
OAC
19
HM511664C Series
Fast Page Mode Early Write Cycle
t
t
RP
RASC
RAS
t
t
t
PC
RSH
CAS
CSH
t
T
t
t
t
t
t
t
t
t
CRP
CAS
RCD
CP
CAS
CAH
CP
CAS
t
t
t
ASC
t
t
CAH
t
t
CAH
ASC
ASR
RAH
ASC
Address
Row
Column
Column
Column
t
t
WCS
t
t
t
WCS
WCH
WCS
WCH
t
WCH
UWE
LWE
t
t
t
DS
DS
DS
t
t
DH
DH
t
DH
Din
Din
Din
Din
High-Z
Dout
20
HM511664C Series
Fast Page Mode Delayed Write Cycle
t
t
RP
RASC
RAS
t
CSH
t
t
RSH
CAS
t
t
PC
T
t
CRP
t
t
t
t
CP
t
RCD
CAS
CP
CAS
CAS
t
t
ASC
ASR
t
CAH
t
t
ASC
t
CAH
t
RAH
t
CWL
t
CAH
ASC
Address
Column
Column
Column
Row
t
CWL
t
CWL
t
t
WP
t
RCS
t
t
RWL
WP
WP
UWE
LWE
t
t
t
RCS
t
DH
DH
t
t
RCS
DH
t
DS
t
DS
DS
Din
Din
Din
Dout
OE
Din
t
OEH
High-Z
t
ODD
21
HM511664C Series
Fast Page Mode Read-Modify-Write Cycle
t
t
RP
RASC
RAS
t
PCM
t
t
T
t
t
CAS
RCD
t
CRP
t
t
CP
CP
CAS
t
CAS
t
CAS
RAD
t
RAH
t
ACP
t
t
CAH
t
CAH
CAH
t
ASR
t
ASC
t
t
ASC
RCS
ASC
Column
Column
t
Row
Column
Address
t
t
t
CWL
RWL
WP
t
CWL
t
AWD
CPW
AWD
AWD
t
CWL
t
t
t
CWD
CWD
t
t
RCS
t
t
t
WP
t
CWD
t
t
RCS
WP
t
CPW
RWD
UWE
LWE
t
t
t
DS
ACP
DS
t
DS
t
t
t
CAC
DZC
t
CAC
DZC
t
t
t
DH
DH
DH
t
DZC
High-Z
AA
High-Z
AA
High-Z
Din
Din
Din
t
Din
t
t
t
CAC
t
t
DZO
RAC
t
t
t
t
t
OAC
OAC
OAC
Dout
OFF2
OEH
OEH
OEH
High-Z
Dout
OFF2
Dout
OFF2
Dout
t
t
t
t
t
DZO
DZO
OE
t
t
t
ODD
ODD
ODD
22
HM511664C Series
Package Dimension
HM511664CJ Series (CP-40D)
Unit: mm
25.80
26.16 Max
21
40
20
1
0.74
1.30 Max
9.40 ± 0.25
1.27
0.43 ± 0.10
0.41 ± 0.08
0.10
Hitachi Code
JEDEC
CP-40D
—
EIAJ
Conforms
Dimension including the plating thickness
Base material dimension
Weight (reference value) 1.73 g
23
HM511664C Series
Package Dimension (cont.)
HM511664CTT Series (TTP-44/40DA)
Unit: mm
18.41
18.81 Max
44
35 32
23
22
1
10 13
0.80
0.80
0.30 ± 0.10
0.25 ± 0.05
M
0.13
11.76 ± 0.20
1.005 Max
0° – 5°
0.50 ± 0.10
0.10
2.40
Hitachi Code
JEDEC
EIAJ
TTP-44/40DA
Conforms
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.43 g
24
HM511664C Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi Semiconductor
(America) Inc.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1897
U S A
Hitachi Europe GmbH
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Tel: 800-285-1601
Fax:303-297-0447
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
25
HM511664C Series
Revision Record
Rev. Date
Contents of Modification
Drawn by Approved by
0.0
0.1
Sep. 10, 1996
Initial issue
I. Ogiwara S. Suzuki
Dec. 20, 1996
Correct errors of AC Characteristics
T. Oono
S. Suzuki
tT (min): 2/2/2 ns to 3/3/3 ns
Deletion of note 23
1.0
Dec. 20, 1997
Change of Subtitle
26
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