HM5117400LS-7 [HITACHI]
4,194,304 - WORD X 4-BIT DYNAMIC RAM; 4,194,304 - 字×4位动态RAM
| 型号： | HM5117400LS-7 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 4,194,304 - WORD X 4-BIT DYNAMIC RAM |
| 文件： | 总33页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM5116400 Series
HM5117400 Series
4,194,304-word 4-bit Dynamic RAM
ADE-203-648C (Z)
Rev. 3.0
Feb. 27, 1997
Description
The Hitachi HM5116400 Series, HM5117400 Series are CMOS dynamic RAMs organized 4,194,304-word
4-bit. They employ the most advanced 0.5 m CMOS technology for high performance and low power.
The HM5116400 Series, HM5117400 Series offer Fast Page Mode as a high speed access mode. They
have package variations of standard 300-mil 26-pin plastic SOJ and standard 300-mil 26-pin plastic TSOP.
Features
•
•
•
Single 5 V ( 10%)
Access time: 50 ns/60 ns/70 ns (max)
Power dissipation
Active mode : 495 mW/440 mW/385 mW (max) (HM5116400 Series)
: 550 mW/495 mW/440 mW (max) (HM5117400 Series)
Standby mode : 11 mW (max)
: 0.83 mW (max) (L-version)
Fast page mode capability
•
•
Long refresh period
4096 refresh cycles : 64 ms (HM5116400 Series)
: 128 ms (L-version)
2048 refresh cycles : 32 ms (HM5117400 Series)
: 128 ms (L-version)
•
3 variations of refresh
-only refresh
-before-
refresh
Hidden refresh
•
•
Battery backup operation (L-version)
Test function
16-bit parallel test mode
HM5116400 Series, HM5117400 Series
Ordering Information
Type No.
Access time
Package
HM5116400S-5
HM5116400S-6
HM5116400S-7
50 ns
60 ns
70 ns
300-mil 26-pin plastic SOJ
(CP-26/24DB)
HM5116400LS-5
HM5116400LS-6
HM5116400LS-7
50 ns
60 ns
70 ns
HM5117400S-5
HM5117400S-6
HM5117400S-7
50 ns
60 ns
70 ns
HM5117400LS-5
HM5117400LS-6
HM5117400LS-7
50 ns
60 ns
70 ns
50 ns
60 ns
70 ns
300-mil 26-pin plastic TSOP II
(TTP-26/24DA)
HM5116400TS-5
HM5116400TS-6
HM5116400TS-7
HM5116400LTS-5
HM5116400LTS-6
HM5116400LTS-7
50 ns
60 ns
70 ns
HM5117400TS-5
HM5117400TS-6
HM5117400TS-7
50 ns
60 ns
70 ns
50 ns
60 ns
70 ns
HM5117400LTS-5
HM5117400LTS-6
HM5117400LTS-7
2
HM5116400 Series, HM5117400 Series
Pin Arrangement
HM5116400S/LS Series
HM5116400TS/LTS Series
VCC
I/O1
I/O2
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
VCC
I/O1
I/O2
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
A11
A9
A11
A9
A10
A0
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
A10
A0
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
9
9
A1
10
11
12
13
A1
10
11
12
13
A2
A2
A3
A3
VCC
VCC
(Top view)
(Top view)
Pin Description
Pin name
Function
Address input
— Row/Refresh address A0 to A11
A0 to A11
— Column address
Data input/Data output
Row address strobe
Column address strobe
Write enable
A0 to A9
I/O1 to I/O4
Output enable
VCC
VSS
Power supply
Ground
3
HM5116400 Series, HM5117400 Series
Pin Arrangement
HM5117400S/LS Series
HM5117400TS/LTS Series
VCC
I/O1
I/O2
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
VCC
I/O1
I/O2
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
NC
A9
NC
A9
A10
A0
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
A10
A0
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
9
9
A1
10
11
12
13
A1
10
11
12
13
A2
A2
A3
A3
VCC
VCC
(Top view)
(Top view)
Pin Description
Pin name
Function
Address input
— Row/Refresh address A0 to A10
A0 to A10
— Column address
Data input/Data output
Row address strobe
Column address strobe
Write enable
A0 to A10
I/O1 to I/O4
Output enable
VCC
VSS
NC
Power supply
Ground
No connection
HM5116400 Series, HM5117400 Series
Block Diagram (HM5116400 Series)
Timing and control
A0
Column decoder
4M array
A1
to
Column
address
buffers
•
•
•
A9
4M array
I/O1
to
I/O4
•
•
•
I/O buffers
4M array
4M array
Row
address
buffers
A10
A11
5
HM5116400 Series, HM5117400 Series
Block Diagram (HM5117400 Series)
Timing and control
A0
A1
to
Column decoder
4M array
Column
address
buffers
•
•
•
A10
4M array
4M array
I/O1
to
I/O4
I/O buffers
•
•
•
Row
address
buffers
4M array
6
HM5116400 Series, HM5117400 Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +7.0
–1.0 to +7.0
50
VCC
V
Iout
mA
W
C
PT
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
C
Recommended DC Operating Conditions (Ta = 0 to +70˚C)
Parameter
Symbol
VCC
Min
4.5
Typ
5.0
—
Max
5.5
Unit
Note
Supply voltage
Input high voltage
Input low voltage
V
V
V
1
1
1
VIH
2.4
6.5
VIL
–1.0
—
0.8
Note: 1. All voltage referred to VSS.
7
HM5116400 Series, HM5117400 Series
DC Characteristics
(Ta = 0 to +70˚C, VCC = 5 V 10%, VSS = 0 V) (HM5116400 Series)
HM5116400
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Test conditions
tRC = min
1
2
,
Operating current*
Standby current
*
ICC1
ICC2
—
—
90
2
—
—
80
2
—
—
70 mA
2
mA
mA
A
TTL interface
,
= VIH
Dout = High-Z
—
—
1
—
1
—
1
CMOS interface
,
VCC – 0.2 V
Dout = High-Z
CMOS interface
CC – 0.2 V
Standby current
(L-version)
ICC2
150 —
150 — 150
,
V
Dout = High-Z
-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
90
5
—
—
80
5
—
—
70 mA
mA
tRC = min
5
= VIH
= VIL
Dout = enable
-before-
current
Fast page mode current*1, *3 ICC7
refresh
ICC6
—
90
80
—
—
80
70
—
—
70 mA
60 mA
tRC = min
—
—
tPC = min
Battery backup current
(Standby with CBR refresh)
(L-version)
ICC10
350 —
350 — 350
A
CMOS interface
Dout = High-Z, CBR
refresh: t
RC = 31.3 s
tRAS 0.3 s
Input leakage current
Output leakage current
ILI
–10 10 –10 10 –10 10
–10 10 –10 10 –10 10
A
A
0 V Vin 7 V
ILO
0 V Vin 7 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4 VCC 2.4 VCC 2.4 VCC
V
High Iout = –5 mA
0
0.4
0
0.4
0
0.4
V
Low Iout = 4.2 mA
Notes : 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while
3. Address can be changed once or less while
= VIL.
= VIH
.
8
HM5116400 Series, HM5117400 Series
DC Characteristics
(Ta = 0 to +70˚C, VCC = 5 V 10%, VSS = 0 V) (HM5117400 Series)
HM5117400
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Test conditions
tRC = min
1
2
,
Operating current*
Standby current
*
ICC1
ICC2
—
—
100 —
90
2
—
—
80 mA
2
—
2
mA
mA
A
TTL interface
,
= VIH
Dout = High-Z
—
—
1
—
1
—
1
CMOS interface
,
VCC – 0.2 V
Dout = High-Z
CMOS interface
CC – 0.2 V
Standby current
(L-version)
ICC2
150 —
100 —
150 — 150
,
V
Dout = High-Z
-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
90
5
—
—
80 mA
mA
tRC = min
5
—
5
= VIH
= VIL
Dout = enable
-before-
current
Fast page mode current*1, *3 ICC7
refresh
ICC6
—
100 —
90
80
—
—
80 mA
70 mA
tRC = min
—
—
90
—
tPC = min
Battery backup current
(Standby with CBR refresh)
(L-version)
ICC10
350 —
350 — 350
A
CMOS interface
Dout = High-Z, CBR
refresh: t
RC = 62.5 s
tRAS 0.3 s
Input leakage current
Output leakage current
ILI
–10 10 –10 10 –10 10
–10 10 –10 10 –10 10
A
A
0 V Vin 7 V
ILO
0 V Vin 7 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4 VCC 2.4 VCC 2.4 VCC
V
High Iout = –5 mA
0
0.4
0
0.4
0
0.4
V
Low Iout = 4.2 mA
Notes : 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while
3. Address can be changed once or less while
= VIL.
= VIH
.
9
HM5116400 Series, HM5117400 Series
Capacitance (Ta = 25˚C, VCC = 5 V 10%)
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (Data-in, Data-out)
5
7
7
1
CI2
—
pF
1
CI/O
—
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. = VIH to disable Dout.
AC Characteristics (Ta = 0 to +70˚C, VCC = 5 V 10%, VSS = 0 V) *1, *2, *18, *19
Test Conditions
•
•
•
Input rise and fall time: 5 ns
Input timing reference levels: 0.8 V, 2.4 V
Output load: 2 TTL gate + C
L (100 pF) (Including scope and jig)
10
HM5116400 Series, HM5117400 Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5116400/HM5117400
-5 -6
Symbol Min Max Min Max Min Max Unit
-7
Parameter
Notes
Random read or write cycle time
precharge time
tRC
90
30
7
—
—
—
110
40
—
—
—
130
50
—
—
—
ns
ns
ns
tRP
precharge time
tCP
10
10
pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
50
13
0
10000 60
10000 15
10000 70
10000 18
10000 ns
10000 ns
pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
—
—
—
—
37
25
—
—
—
—
—
—
50
0
—
—
—
—
45
30
—
—
—
—
—
—
50
0
—
—
—
—
52
35
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
10
0
10
0
0
7
10
20
15
15
60
5
15
20
15
18
70
5
to
delay time
17
12
13
50
5
3
4
to column address delay time tRAD
hold time
hold time
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
to
precharge time
to Din delay time
delay time from Din
delay time from Din
Transition time (rise and fall)
13
0
15
0
18
0
5
6
6
7
0
0
0
3
3
3
11
HM5116400 Series, HM5117400 Series
Read Cycle
HM5116400/HM5117400
-5 -6
Symbol Min Max Min Max Min Max Unit
-7
Parameter
Notes
Access time from
Access time from
tRAC
tCAC
—
—
50
13
—
—
60
15
—
—
70
18
ns
ns
8, 9, 20
9, 10, 17,
20
Access time from address
tAA
—
25
—
30
—
35
ns
9, 11, 17,
20
Access time from
tOEA
tRCS
tRCH
tRRH
—
0
13
—
—
—
—
—
—
—
—
13
13
—
—
0
15
—
—
—
—
—
—
—
—
15
15
—
—
0
18
—
—
—
—
—
—
—
—
15
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9, 20
Read command setup time
Read command hold time to
Read command hold time to
0
0
0
12
12
0
0
0
Column address to
Column address to
to output in low-Z
lead time tRAL
25
25
0
30
30
0
35
35
0
lead time tCAL
tCLZ
tOH
Output data hold time
3
3
3
Output data hold time from
Output buffer turn-off time
Output buffer turn-off to
to Din delay time
tOHO
tOFF
tOEZ
tCDD
3
3
3
—
—
13
—
—
15
—
—
18
13
13
5
Write Cycle
HM5116400/HM5117400
-5 -6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Notes
Write command setup time
Write command hold time
Write command pulse width
tWCS
tWCH
tWP
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
14
7
10
10
15
15
0
15
10
18
18
0
7
Write command to
Write command to
Data-in setup time
Data-in hold time
lead time
lead time
tRWL
tCWL
tDS
13
13
0
15
15
tDH
7
10
15
12
HM5116400 Series, HM5117400 Series
Read-Modify-Write Cycle
HM5116400/HM5117400
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Notes
Read-modify-write cycle time
tRWC
131
73
36
48
13
—
—
—
—
—
155
85
40
55
15
—
—
—
—
—
181
98
46
63
18
—
—
—
—
—
ns
ns
ns
ns
ns
to
to
delay time
delay time
tRWD
14
14
14
tCWD
delay time tAWD
tOEH
Column address to
hold time from
Refresh Cycle
HM5116400/HM5117400
-5 -6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Notes
setup time (CBR refresh cycle) tCSR
5
7
0
7
5
—
—
—
—
—
5
—
—
—
—
—
5
—
—
—
—
—
ns
ns
ns
ns
ns
hold time (CBR refresh cycle) tCHR
setup time (CBR refresh cycle) tWRP
hold time (CBR refresh cycle) tWRH
10
0
10
0
10
5
10
5
precharge to
hold time
tRPC
Fast Page Mode Cycle
HM5116400/HM5117400
-5
Symbol Min Max
-6
-7
Parameter
Min Max
Min Max
45
100000 —
Unit
Notes
Fast page mode cycle time
tPC
pulse width tRASP
precharge tCPA
precharge tCPRH
35
—
—
30
—
40
—
—
ns
Fast page mode
Access time from
hold time from
100000 —
100000 ns
16
30
—
35
—
40
ns
ns
9, 17, 20
—
35
—
40
—
13
HM5116400 Series, HM5117400 Series
Fast Page Mode Read-Modify-Write Cycle
HM5116400/HM5117400
-5 -6
Symbol Min Max Min Max Min Max Unit
-7
Parameter
Notes
Fast page mode read-modify-write tPRWC
cycle time
76
—
85
—
96
—
ns
delay time from
precharge tCPW
53
—
60
—
68
—
ns
14
Test Mode Cycle *19
HM5116400/HM5117400
-5 -6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Notes
Test mode
Test mode
setup time
hold time
tWTS
tWTH
0
7
—
—
0
—
—
0
—
—
ns
ns
10
10
Refresh (HM5116400 Series)
Parameter
Symbol
tREF
Max
Unit
ms
Notes
Refresh
64
4096 cycles
4096 cycles
Refresh (L-version)
tREF
128
ms
Refresh (HM5117400 Series)
Parameter
Symbol
tREF
Max
32
Unit
ms
Notes
Refresh period
2048 cycles
2048 cycles
Refresh period (L-version)
tREF
128
ms
14
HM5116400 Series, HM5117400 Series
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing -only refresh or -before- refresh). If
-before- refresh cycles are
the internal refresh counter is used, a minimum of eight
required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA
.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
10.Assumes that tRCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max).
11.Assumes that tRAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max).
12.Either t
RCH or tRRH must be satisfied for a read cycles.
13.tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14.tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS
tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW
tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
15.These parameters are referred to
edge in delayed write or read-modify-write cycles.
16.tRASP defines pulse width in Fast page mode cycles.
17.Access time is determined by the longest among tAA, tCAC and tCPA
leading edge in early write cycles and to
leading
.
18.In delayed write or read-modify-write cycles,
to the device.
must disable output buffer prior to applying data
19.The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M
4 are don’t care during test mode. Test mode is set by performing a -and- -before-
(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1
to I/O4) and read out from each I/O.
If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read
cycle, then the device has passed. If they are not equal, data output pin is a low state, then the
device has failed.
Refresh during test mode operation can be performed by normal read cycles or by WCBR
refresh cycles.
To get out of test mode and enter a normal operation mode, perform either a regular
before- refresh cycle or -only refresh cycle.
-
20.In a test mode read cycle, the value of tRAC, tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
15
HM5116400 Series, HM5117400 Series
21.XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min)
///////: Invalid Dout
V
VIL (max))
IN
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
+16
HM5116400 Series, HM5117400 Series
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing -only refresh or -before- refresh). If
-before- refresh cycles are
the internal refresh counter is used, a minimum of eight
required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA
.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
10.Assumes that tRCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max).
11.Assumes that tRAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max).
12.Either t
RCH or tRRH must be satisfied for a read cycles.
13.tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14.tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS
tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW
tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
15.These parameters are referred to
edge in delayed write or read-modify-write cycles.
16.tRASP defines pulse width in Fast page mode cycles.
17.Access time is determined by the longest among tAA, tCAC and tCPA
leading edge in early write cycles and to
leading
.
18.In delayed write or read-modify-write cycles,
to the device.
must disable output buffer prior to applying data
19.The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M
4 are don’t care during test mode. Test mode is set by performing a -and- -before-
(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1
to I/O4) and read out from each I/O.
If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read
cycle, then the device has passed. If they are not equal, data output pin is a low state, then the
device has failed.
Refresh during test mode operation can be performed by normal read cycles or by WCBR
refresh cycles.
To get out of test mode and enter a normal operation mode, perform either a regular
before- refresh cycle or -only refresh cycle.
-
20.In a test mode read cycle, the value of tRAC, tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
15
HM5116400 Series, HM5117400 Series
Early Write Cycle
t
t
RC
t
RAS
RP
RAS
CAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
WCH
WCS
WE
t
t
DH
DS
Din
Din
High-Z*
Dout
t
t
(min)
WCS
WCS
*
18
HM5116400 Series, HM5117400 Series
Delayed Write Cycle*18
t
t
RC
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
CAS
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
t
CWL
RWL
WP
t
RCS
WE
Din
t
t
t
DH
DZC
DS
High-Z
Din
t
t
OEH
DZO
t
OED
OE
t
OEZ
t
CLZ
High-Z
Dout
Invalid Dout
19
HM5116400 Series, HM5117400 Series
Read-Modify-Write Cycle*18
t
t
RWC
RAS
t
RP
RAS
t
T
t
t
t
CRP
RCD
CAS
CAS
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
Address
Row
Column
t
t
t
t
CWD
AWD
RWD
CWL
RWL
t
RCS
t
t
WP
WE
Din
OE
t
t
DH
DZC
t
DS
High-Z
Din
t
OED
t
OEH
t
DZO
t
OEA
t
CAC
t
t
OEZ
t
t
AA
t
RAC
OHO
High-Z
Dout
Dout
CLZ
20
HM5116400 Series, HM5117400 Series
-Only Refresh Cycle
t
RC
t
t
RAS
RP
t
T
t
t
t
CRP
CRP
RPC
t
t
RAH
ASR
Address
Row
t
OFF
High-Z
Dout
21
HM5116400 Series, HM5117400 Series
-Before-
Refresh Cycle
t
RC
t
t
t
RP
RP
RAS
t
t
t
t
CRP
t
CSR
CHR
RPC
RPC
t
T
t
CP
t
t
t
WRH
CP
WRP
Address
t
OFF
High-Z
Dout
22
HM5116400 Series, HM5117400 Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RAS
RP
RAS
RP
RAS
RAS
t
T
t
t
t
CRP
RSH
CHR
t
RCD
CAS
Address
WE
t
t
RAL
RAD
t
t
t
t
CAH
ASR RAH
Row
ASC
Column
t
WRP
t
WRP
t
t
RRH
WRH
t
WRH
t
RCS
t
t
CDD
DZC
High-Z
Din
t
t
OED
DZO
t
OEA
OE
t
t
t
CAC
OEZ
OHO
t
AA
t
t
t
RAC
OFF
OH
t
CLZ
Dout
Dout
23
HM5116400 Series, HM5117400 Series
Fast Page Mode Read Cycle
t
RASP
t
t
RP
CPRH
RAS
CAS
t
T
t
t
t
t
CSH
PC
RSH
t
CRP
t
t
t
t
t
RCD
CAS
CP
CAS
CAL
CP
CAS
t
t
RAL
CAL
t
t
t
RAD
CAL
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
Address
Row
Column 1
Column 2
Column N
t
t
t
t
RCS
RCS
RRH
RCH
t
t
t
t
t
t
RCS
DZC
RCH
CDD
RCH
CDD
WE
Din
OE
t
t
DZC
DZC
t
CDD
High-Z
High-Z
High-Z
t
t
t
t
t
t
OED
DZO
OED
DZO OED
DZO
t
t
t
CPA
RAC
CPA
t
t
t
t
t
t
OH
AA
OH
AA
OH
AA
t
OHO
t
t
OHO
OHO
t
t
t
OEA
OEA
OEA
t
t
CAC
t
t
t
t
t
CAC
CAC
CLZ
OFF
OFF
OEZ
OFF
OEZ
t
t
t
t
CLZ
t
OEZ
CLZ
Dout 1
Dout 2
Dout N
Dout
24
HM5116400 Series, HM5117400 Series
Fast Page Mode Early Write Cycle
t
t
RASP
RP
RAS
t
T
t
t
t
RSH
CSH
PC
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
CAS
Address
WE
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
ROW
Column 1
Column 2
Column N
t
t
t
t
t
t
WCH
WCS
WCH
WCS
WCH
WCS
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
Din 1
Din 2
Din N
Din
High-Z*
Dout
t
t
(min)
WCS
*
WCS
25
HM5116400 Series, HM5117400 Series
Fast Page Mode Delayed Write Cycle*18
t
RASP
t
RP
RAS
t
t
t
t
CP
CRP
T
CP
t
t
t
t
CSH
PC
RSH
CAS
t
t
t
CAS
RCD
CAS
CAS
t
t
RAD
t
t
t
ASR
ASC
t
ASC
t
ASC
t
t
RAH
CAH
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
CWL
CWL
t
CWL
t
RWL
t
t
RCS
RCS
RCS
WE
t
t
t
WP
WP
WP
t
t
t
t
t
t
t
DZC DS
DZC DS
DZC DS
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
DZO
DZO
DZO
OED
t
t
OED
OED
t
t
t
OEH
OEH
OEH
OE
t
t
t
CLZ
CLZ
CLZ
t
t
t
OEZ
OEZ
OEZ
High-Z
Dout
Invalid Dout
Invalid Dout
Invalid Dout
26
HM5116400 Series, HM5117400 Series
Fast Page Mode Read-Modify-Write Cycle*18
t
RASP
t
RP
RAS
t
t
T
PRWC
t
t
t
t
RSH
CAS
t
CRP
CP
CP
t
t
t
CAS
RCD
CAS
CAS
t
t
RAD
t
t
t
ASC
ASR
ASC
RAH
ASC
t
t
t
t
CAH
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
t
t
t
CWL
RWD
AWD
CWL
CPW
AWD
CWL
CPW
AWD
t
RWL
t
t
t
t
t
CWD
CWD
RCS
CWD
RCS
WE
t
t
t
t
t
WP
t
DS
RCS
DZO
WP
DS
WP
t
t
t
DS
t
DZC
DZC
DZC
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
OE
t
t
t
OED
OED
OED
t
t
t
DZO
DZO
t
t
t
OEH
OEH
OEH
t
t
t
OHO
OHO
OHO
t
t
t
t
t
t
OEA
CAC
OEA
CAC
OEA
CAC
t
t
t
AA
AA
AA
t
t
CPA
CPA
t
t
RAC
t
t
t
OEZ
t
t
OEZ
OEZ
CLZ
CLZ
CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
27
HM5116400 Series, HM5117400 Series
Test Mode Cycle*19
*,**
Reset Cycle
Set Cycle**
Test Mode Cycle
Normal Mode
RAS
CAS
WE
*
CBR or RAS-only refresh
** Address, Din, OE: H or L
28
HM5116400 Series, HM5117400 Series
Test Mode Set Cycle
t
RC
t
t
t
RP
RP
RAS
RAS
CAS
t
t
t
t
t
CRP
RPC
CSR
CHR
RPC
t
T
t
t
t
t
CP
CP
WTS
WTH
WE
Address
Dout
t
OFF
High-Z
29
HM5116400 Series, HM5117400 Series
Package Dimensions
HM5116400S/LS Series
HM5117400S/LS Series (CP-26/24DB)
Unit: mm
16.90
17.27 Max
26
1
21 19
14
13
6
8
0.74
1.30 Max
1.27
0.10
6.71 ± 0.25
0.43 ± 0.10
0.41 ± 0.08
2.54
Hitachi Code
CP-26/24DB
MO-077-AA
SC-632-A
0.8 g
JEDEC Code
EIAJ Code
Weight
30
HM5116400 Series, HM5117400 Series
HM5116400TS/LTS Series
HM5117400TS/LTS Series (TTP-26/24DA)
Unit: mm
17.14
17.54 Max
26
1
21
19
14
13
6
8
1.27
0.80
M
0.21
0.42 0.08
0.40 0.06
9.22 0.20
1.15 Max
0 – 5
0.50 0.10
2.54
0.10
Hitachi Code
JEDEC Code
EIAJ Code
Weight
TTP-26/24DA
MO-132AB
—
0.30 g
31
HM5116400 Series, HM5117400 Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Tel: 415-589-8300
Fax: 535-1533
Fax: 415-583-4207
Tel: 089-9 91 80-0
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Berkshire SL6 8YA
United Kingdom
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Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 0628-585000
Fax: 0628-778322
Tel: 27359218
Fax: 27306071
32
HM5116400 Series, HM5117400 Series
Revision Record
Rev. Date
Contents of Modification
Drawn by Approved by
Y. Kasama M. Mishima
Y. Kasama Y. Matsuno
1.0
2.0
Oct. 14, 1996
Nov. 14, 1996
Initial issue
Addition of HM5116400-5 Series
Addition of HM5117400-5 Series
Power dissipation (active)
605/550 mW(max) to 550/495/440 mW (max)
(HM5117400 Series)
DC Characteristics (HM5117400 Series)
ICC1 max: 110/100 mA to 100/90/80 mA
ICC3 max: 110/100 mA to 100/90/80 mA
ICC6 max: 110/100 mA to 100/90/80 mA
3.0
Feb. 27, 1997
AC Characteristics
tRRH min: 5/5/5 ns to 0/0/0 ns
33
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