HM514260DLJ-7

更新时间:2024-11-08 18:35:02
品牌:HITACHI
描述:Fast Page DRAM, 256KX16, 70ns, CMOS, PDSO40, 0.400 INCH, PLASTIC, SOJ-40

HM514260DLJ-7 概述

Fast Page DRAM, 256KX16, 70ns, CMOS, PDSO40, 0.400 INCH, PLASTIC, SOJ-40

HM514260DLJ-7 数据手册

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HM514260D Series  
HM51S4260D Series  
262,144-word × 16-bit Dynamic RAM  
ADE-203-510A (Z)  
Rev. 1.0  
Dec. 2, 1996  
Description  
The Hitachi HM51(S)4260D is CMOS dynamic RAM organized as 262,144-word × 16-bit. HM51(S)4260D  
has realized higher density, higher performance and various functions by employing 0.8 µm CMOS process  
technology and some new CMOS circuit design technologies. The HM51(S)4260D offers Fast Page Mode as  
a high speed access mode. Multiplexed address input permits the HM51(S)4260D to be packaged in standard  
400-mil 40-pin plastic SOJ, and standard 400-mil 44-pin plastic TSOPII. Internal refresh timer enables  
HM51S4260D self refresh operation.  
Features  
Single 5 V  
Access time: 60 ns/70 ns/80 ns (max)  
Power dissipation  
Active mode:  
825 mW/770 mW/688 mW (max)  
Standby mode: 11 mW (max)  
1.1 mW (max) (L-version)  
Fast page mode capability  
512 refresh cycles:  
8 ms  
128 ms (L-version)  
2 CAS byte control  
2 variations of refresh  
RAS-only refresh  
CAS-before-RAS refresh  
Battery back up operation (L-version)  
Self refresh operation (HM51S4260D/DL)  
HM514260D, HM51S4260D Series  
Ordering Information  
Type No.  
Access time  
Package  
HM514260DJ-6  
HM514260DJ-7  
HM514260DJ-8  
60 ns  
70 ns  
80 ns  
400-mill 40-pin plastic SOJ (CP-40D)  
HM514260DLJ-6  
HM514260DLJ-7  
HM514260DLJ-8  
60 ns  
70 ns  
80 ns  
HM51S4260DJ-6  
HM51S4260DJ-7  
HM51S4260DJ-8  
60 ns  
70 ns  
80 ns  
HM51S4260DLJ-6  
HM51S4260DLJ-7  
HM51S4260DLJ-8  
60 ns  
70 ns  
80 ns  
HM514260DTT-6  
HM514260DTT-7  
HM514260DTT-8  
60 ns  
70 ns  
80 ns  
400-mill 44-pin plastic TSOP II (TTP-44/40DB)  
HM514260DLTT-6  
HM514260DLTT-7  
HM514260DLTT-8  
60 ns  
70 ns  
80 ns  
HM51S4260DTT-6  
HM51S4260DTT-7  
HM51S4260DTT-8  
60 ns  
70 ns  
80 ns  
HM51S4260DLTT-6  
HM51S4260DLTT-7  
HM51S4260DLTT-8  
60 ns  
70 ns  
80 ns  
2
HM514260D, HM51S4260D Series  
Pin Arrangement  
HM514260DTT/DLTT Series  
HM51S4260DTT/DLTT Series  
HM514260DJ/DLJ Series  
HM51S4260DJ/DLJ Series  
VCC  
I/O0  
I/O1  
I/O2  
I/O3  
VCC  
I/O4  
I/O5  
I/O6  
I/O7  
1
2
3
4
5
6
7
8
9
10  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
VSS  
VSS  
VCC  
I/O0  
I/O1  
I/O2  
I/O3  
VCC  
I/O4  
I/O5  
I/O6  
I/O7  
NC  
1
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
I/O15  
I/O14  
I/O13  
I/O12  
VSS  
I/O15  
I/O14  
I/O13  
I/O12  
VSS  
2
3
4
5
I/O11  
I/O10  
I/O9  
6
I/O11  
I/O10  
I/O9  
I/O8  
NC  
7
8
I/O8  
9
10  
11  
12  
13  
LCAS  
UCAS  
OE  
NC  
NC  
WE  
RAS  
NC  
A0  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
NC  
NC  
LCAS  
UCAS  
OE  
WE  
RAS 14  
NC  
A8  
15  
16  
17  
18  
19  
20  
A7  
A8  
A0  
A6  
A7  
A1  
A5  
A1  
A6  
A2  
A4  
A2  
A5  
A3  
VSS  
A3  
A4  
VCC  
VCC  
V
SS  
(Top view)  
(Top view)  
Pin Description  
Pin name  
Function  
A0 to A8  
Address input  
– Row address  
A0 to A8  
– Column address  
– Refresh address  
A0 to A8  
A0 to A8  
I/O0 to I/O15  
Data-in/data-out  
Row address strobe  
Column address strobe  
Read/write enable  
Output enable  
RAS  
UCAS, LCAS  
WE  
OE  
VCC  
VSS  
NC  
Power (+5 V)  
Ground  
No connection  
3
HM514260D, HM51S4260D Series  
Block Diagram  
I/O4  
buffer  
I/O11  
buffer  
I/O3  
I/O3  
I/O2  
I/O2  
I/O1  
I/O1  
I/O0  
I/O0  
I/O15  
I/O14  
I/O13 I/O12  
I/O13 I/O12  
I/O4  
I/O5  
I/O6  
I/O7  
I/O11  
I/O10  
I/O9  
I/O15  
buffer  
I/O14  
buffer  
buffer buffer  
buffer buffer  
buffer buffer  
I/O5  
buffer  
I/O10  
buffer  
I/O6  
buffer  
I/O9  
buffer  
I/O7  
buffer  
I/O8  
buffer  
I/O8  
Selector  
Selector  
Selector  
Selector  
Row  
driver  
Row  
driver  
Row  
driver  
Row Row  
driver driver  
Row  
driver  
Row  
driver  
Row  
driver  
WE  
RAS  
UCAS  
Row Decoder & Peripheral Circuit  
LCAS  
OE  
Row  
driver  
Row Row  
driver driver  
Row  
driver  
Row  
driver  
Row Row  
driver driver  
Row  
driver  
Column address buffer  
CA0 to CA8  
Row address buffer  
RA0 to RA8  
Address A0 to A8  
4
HM514260D, HM51S4260D Series  
Operation Mode  
The HM51(S)4260D series has the following 11 operation modes.  
1. Read cycle  
2. Early write cycle  
3. Delayed write cycle  
4. Read-modify-write cycle  
5. RAS-only refresh cycle  
6. CAS-before-RAS refresh cycle  
7. Self refresh cycle(HM51S4260D)  
8. Fast page mode read cycle  
9. Fast page mode early write cycle  
10. Fast page mode delayed write cycle  
11. Fast page mode read-modify-write cycle  
Inputs  
RAS  
LCAS  
UCAS  
WE  
D
OE  
Output  
Open  
Operation  
H
H
H
D
Standby  
H
L
L
H
L
Valid  
Standby  
L
L
L
H
L
Valid  
Read cycle  
L
L
L
L*2  
L*2  
H to L  
D
D
Open  
Early write cycle  
L
L
L
H
Undefined  
Valid  
Delayed write cycle  
Read-modify-write cycle  
RAS-only refresh cycle  
CAS-before-RAS refresh cycle or  
Self refresh cycle (HM51S4260D)  
L
L
L
L to H  
L
H
H
D
D
Open  
H to L  
H
L
D
Open  
L
H
L
L
L
L
L
L
L
H to L  
H to L  
H to L  
H to L  
L
H to L  
H to L  
H to L  
H to L  
L
H
L
Valid  
Fast page mode read cycle  
L*2  
L*2  
H to L  
H
D
Open  
Fast page mode early write cycle  
Fast page mode delayed write cycle  
Fast page mode read-modify-write cycle  
Read cycle (Output disabled)  
H
Undefined  
Valid  
L to H  
H
Open  
Notes: 1. H: High(inactive) L: Low(active) D: H or L  
2. tWCS 0 ns  
Early write cycle  
tWCS < 0 ns  
Delayed write cycle  
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of  
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However  
write OPERATION and output HIZ control are done independently by each UCAS, LCAS.  
ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected.  
5
HM514260D, HM51S4260D Series  
Absolute Maximum Ratings  
Parameter  
Symbol  
VT  
Value  
Unit  
V
Voltage on any pin relative to VSS  
Supply voltage relative to VSS  
Short circuit output current  
Power dissipation  
–1.0 to +7.0  
–1.0 to +7.0  
50  
VCC  
V
Iout  
PT  
mA  
W
1.0  
Operating temperature  
Storage temperature  
Topr  
Tstg  
0 to +70  
–55 to +125  
°C  
°C  
Recommended DC Operating Conditions (Ta = 0 to +70°C)  
Parameter  
Symbol  
VSS  
Min  
0
Typ  
0
Max  
0
Unit  
V
Notes  
Supply voltage  
2
VCC  
4.5  
2.4  
–1.0  
5.0  
5.5  
6.5  
0.8  
V
1, 2  
1
Input high voltage  
Input low voltage  
VIH  
V
VIL  
V
1
Notes: 1. All voltage referred to VSS  
2. The supply voltage with all VCC pins must be on the same level.  
The supply voltage with all VSS pins must be on the same level.  
6
HM514260D, HM51S4260D Series  
DC Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 10%, VSS = 0 V)  
HM514260D, HM51S4260D  
-6 -7 -8  
Symbol Min Max Min Max Min Max Unit Test conditions  
Parameter  
Operating  
ICC1  
150  
140  
125 mA RAS, UCAS or LCAS cycling  
RC = min  
current*1, *2  
t
Standby current  
ICC2  
2
2
2
mA TTL interface  
RAS, UCAS, LCAS = VIH  
Dout = High-Z  
1
1
1
mA CMOS interface  
RAS, UCAS, LCAS, WE,  
OE VCC – 0.2 V  
Dout = High-Z  
Standby current  
(L-version)  
ICC2  
200  
200  
200 µA  
CMOS interface  
RAS, UCAS, LCAS, OE,  
WE VCC – 0.2 V  
Dout = High-Z  
RAS-only refresh  
ICC3  
140  
5
130  
5
110 mA tRC = min  
current*2  
Standby current*1 ICC5  
5
mA RAS = VIH, UCAS, LCAS = VIL  
Dout = enable  
CAS-before-RAS  
ICC6  
ICC7  
ICC10  
140  
150  
300  
130  
130  
300  
110 mA tRC = min  
refresh current*2  
Fast page mode  
current*1, *3  
120 mA tPC = min  
Battery backup  
current*4 (Standby  
with CBR refresh)  
(L-version)  
300 µA  
Standby: CMOS interface  
Dout = High-Z  
CBR refresh: tRC = 250 µs  
tRAS 1 µs, UCAS, LCAS = VIL  
WE, OE = VIH  
Self-refresh mode ICC11  
current  
(HM51S4260D)  
1
1
1
mA CMOS interface  
RAS, UCAS, LCAS 0.2 V,  
Dout = High-Z  
Self-refresh mode ICC11  
current  
(HM51S4260DL)  
200  
200  
200 µA  
CMOS interface  
RAS, UCAS, LCAS 0.2 V,  
Dout = High-Z  
7
HM514260D, HM51S4260D Series  
DC Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 10%, VSS = 0 V) (cont)  
HM514260D, HM51S4260D  
-6  
-7  
-8  
Parameter  
Symbol Min Max Min Max Min Max Unit Test conditions  
Input leakage  
current  
ILI  
–10 10  
–10 10  
–10 10  
–10 10  
–10 10  
–10 10  
µA  
µA  
0 V Vin 6.5 V  
Output leakage  
current  
ILO  
0 V Vout 6.5 V, Dout = disable  
Output high voltage VOH  
Output low voltage VOL  
2.4 VCC 2.4 VCC 2.4 VCC  
0.4 0.4 0.4  
V
V
High Iout = –5.0 mA  
Low Iout = 4.2 mA  
0
0
0
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output  
open condition.  
2. Address can be changed once or less while RAS = VIL.  
3. Address can be changed once or less while UCAS and LCAS = VIH.  
4. VIH VCC – 0.2 V, 0 VIL 0.2 V, Address can be changed once or less while RAS = VIL  
5. All the VCC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied with  
the same voltage.  
Capacitance (Ta = +25°C, VCC = 5 V ± 10%)  
Parameter  
Symbol  
CI1  
Typ  
Max  
5
Unit  
pF  
Notes  
Input capacitance (Address)  
Input capacitance (Clocks)  
Output capacitance (Data-in, Data-out)  
1
CI2  
7
pF  
1
CI/O  
10  
pF  
1, 2  
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.  
2. UCAS and LCAS = VIH to disable Dout  
8
HM514260D, HM51S4260D Series  
AC Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 10%, VSS = 0 V) *1, *14, *15, *17, *18  
Test Conditions  
Input rise and fall time: 5 ns  
Input timing reference levels: 0.8 V, 2.4 V  
Input levels: 0 V, 3 V  
Output load: 2 TTL gate + CL (100 pF) (Including scope and jig)  
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)  
HM514260D, HM51S4260D  
-6  
-7  
-8  
Parameter  
Symbol Min Max  
Min Max  
Min Max  
Unit Notes  
Random read or write cycle time  
RAS precharge time  
tRC  
110  
40  
60  
15  
0
130  
50  
150  
60  
ns  
ns  
tRP  
RAS pulse width  
tRAS  
tCAS  
tASR  
tRAH  
tASC  
tCAH  
tRCD  
tRAD  
tRSH  
tCSH  
tCRP  
tODD  
tDZO  
tDZC  
tT  
10000 70  
10000 20  
10000 80  
10000 20  
10000 ns  
10000 ns  
CAS pulse width  
23  
Row address setup time  
Row address hold time  
Column address setup time  
Column address hold time  
RAS to CAS delay time  
RAS to column address delay time  
RAS hold time  
45  
30  
50  
8
0
50  
35  
50  
8
0
60  
40  
50  
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ms  
10  
0
10  
0
10  
0
19  
19  
8
15  
20  
15  
15  
60  
10  
15  
0
15  
20  
15  
20  
70  
15  
20  
0
15  
20  
15  
20  
80  
15  
20  
0
9
CAS hold time  
CAS to RAS precharge time  
OE to Din delay time  
OE delay time from Din  
CAS setup time from Din  
Transition time (rise and fall)  
Refresh period  
20  
7
0
0
0
3
3
3
tREF  
tREF  
Refresh period (L-version)  
128  
128  
128  
9
HM514260D, HM51S4260D Series  
Read Cycle  
HM514260D, HM51S4260D  
-6  
Symbol Min Max  
-7  
-8  
Parameter  
Min Max  
Min Max  
Unit Notes  
Access time from RAS  
Access time from CAS  
tRAC  
tCAC  
60  
15  
70  
20  
80  
20  
ns  
ns  
2, 3  
3, 4,  
13  
Access time from address  
tAA  
30  
35  
40  
ns  
3, 5,  
13  
Access time from OE  
tOAC  
tRCS  
tRCH  
tRRH  
tRAL  
0
15  
15  
15  
0
20  
15  
15  
0
20  
15  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
23  
Read command setup time  
Read command hold time to CAS  
Read command hold time to RAS  
Column address to RAS lead time  
Output buffer turn-off time  
Output buffer turn-off to OE  
CAS to Din delay time  
19  
0
0
0
16, 20  
16  
0
0
0
30  
0
35  
0
40  
0
tOFF1  
tOFF2  
tCDD  
6
6
0
0
0
15  
15  
15  
Write Cycle  
HM514260D, HM51S4260D  
-6  
Symbol Min Max  
-7  
-8  
Parameter  
Min Max  
Min Max  
Unit Notes  
Write command setup time  
Write command hold time  
Write command pulse width  
Write command to RAS lead time  
Write command to CAS lead time  
Data-in setup time  
tWCS  
tWCH  
tWP  
0
0
0
0
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10, 19  
19  
15  
10  
15  
15  
0
15  
10  
20  
20  
0
15  
10  
20  
20  
0
tRWL  
tCWL  
tDS  
21  
11, 21  
11, 21  
23  
Data-in hold time  
tDH  
15  
15  
15  
CAS to OE delay time  
tCOD  
10  
HM514260D, HM51S4260D Series  
Read-Modify-Write Cycle  
HM514260D, HM51S4260D  
-6  
-7  
-8  
Parameter  
Symbol Min Max  
Min Max  
Min Max  
Unit Notes  
Read-modify-write cycle time  
RAS to WE delay time  
CAS to WE delay time  
Column address to WE delay time  
OE hold time from WE  
tRWC  
tRWD  
tCWD  
tAWD  
tOEH  
150  
80  
35  
50  
15  
180  
95  
45  
60  
20  
200  
105  
45  
ns  
ns  
ns  
ns  
ns  
10  
10  
65  
10, 13  
20  
Refresh Cycle  
HM514260D, HM51S4260D  
-6  
Symbol Min Max  
-7  
-8  
Parameter  
Min Max  
Min Max  
Unit Notes  
CAS setup time (CBR refresh cycle)  
CAS hold time (CBR refresh cycle)  
RAS precharge to CAS hold time  
CAS precharge time in normal mode  
tCSR  
tCHR  
tRPC  
tCPN  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
19  
20  
19  
22  
Fast Page Mode Cycle  
HM514260D, HM51S4260D  
-6  
Symbol Min Max  
-7  
-8  
Parameter  
Min Max  
Min Max  
Unit Notes  
Fast page mode cycle time  
Fast page mode CAS precharge time  
Fast page mode RAS pulse width  
Access time from CAS precharge  
tPC  
40  
10  
45  
10  
50  
10  
ns  
tCP  
ns  
22  
12  
tRASC  
tACP  
100000 —  
100000 —  
100000 ns  
35  
40  
45  
ns  
3, 13,  
20  
RAS hold time from CAS precharge  
tRHCP  
35  
40  
45  
ns  
11  
HM514260D, HM51S4260D Series  
Fast Page Mode Read-Modify-Write Cycle  
HM514260D, HM51S4260D  
-6  
Symbol Min Max  
-7  
-8  
Parameter  
Min Max  
Min Max  
Unit Notes  
Fast page mode read-modify-write cycle tCPW  
55  
65  
70  
ns  
CAS precharge to WE delay time  
Fast page mode read-modify-write cycle tPCM  
time  
80  
95  
100  
ns  
Self Refresh Mode  
HM51S4260D  
-6  
-7  
-8  
Parameter  
Symbol Min Max  
Min Max  
Min Max  
Unit Notes  
RAS pulse width (self-refresh)  
tRASS  
100  
100  
100  
µs  
24, 25,  
26, 27  
RAS precharge time (self-refresh)  
CAS hold time (self-refresh)  
tRPS  
tCHS  
110  
–50  
130  
–50  
150  
–50  
ns  
ns  
21  
Notes: 1. AC measurements assume tT = 5 ns, VIH = 3.0 V, VIL = 0.0 V.  
2. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum  
recommended value shown in this table, tRAC exceeds the value shown.  
3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.  
4. Assumes that tRCD tRCD (max) and tRAD tRAD (max).  
5. Assumes that tRCD tRCD (max) and tRAD tRAD (max).  
6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not  
referred to output voltage levels.  
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition  
times are measured between VIH and VIL.  
8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a  
reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is  
controlled exclusively by tCAC  
.
9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a  
reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is  
controlled exclusively by tAA.  
10. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet  
as electrical characteristics only: if tWCS tWCS (min), the cycle is an early write cycle and the data out  
pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD  
t
CWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output  
will contain data read from the selected cell; if neither of the above sets of conditions is satisfied,  
the condition of the data out (at access time) is indeterminate.  
11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge  
in a delayed write or a read-modify-write cycle.  
12  
HM514260D, HM51S4260D Series  
12. tRASC defines RAS pulse width in fast page mode cycles.  
13. Access time is determined by the longest among tAA, tCAC and tACP  
.
14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization  
cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is  
used, a minimum of eight CAS-before-RAS refresh cycles is required.  
15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to  
the device.  
16. Either tRCH or tRRH must be satisfied for a read cycle.  
17. When both UCAS and LCAS go low at the same time, all 16-bits data are written into the device.  
UCAS and LCAS cannot be staggered within the same write/read cycles.  
18. All the VCC and VSS pins shall be supplied with the same voltages.  
19. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS.  
20. tCRP, tCHR, tACP tRCH and tCPW are determined by the later rising edge of UCAS or LCAS.  
21. tCWL, tDH, tDS and tCHS should be satisfied by both UCAS and LCAS.  
22. tCPN and tCP are determined by the time that both UCAS and LCAS are high.  
23. When output buffers are enabled once, sustain the low impedance state until valid data is obtained.  
When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS  
line noise, which causes to degrade VIH min/VIL max level.  
24. Please do not use tRASS timing, 10 µs tRASS 100 µs. During this period, the device is in transition  
state from normal operation mode to self refresh mode. If tRASS > 100 µs, then RAS precharge time  
should use tRPS instead of tRP.  
25. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR  
refresh should be executed within 15.6 µs immediately after exiting from and before entering into  
self refresh mode.  
26. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles  
of distributed CBR refresh with 15.6 µs interval should be executed within 8 ms immediately  
after exiting from and before entering into the self refresh mode.  
27. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self  
refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode  
again.  
28. XXX: H or L (H: VIH (Min) VIN VIH (Max), L: VIL (Min) V VIL (Max))  
IN  
///////: Invalid Dout  
When the address, clock and input pins are not described on timing waveforms, their pins must be  
applied VIH or VIL.  
13  
HM514260D, HM51S4260D Series  
Notes concerning 2CAS control  
Please do not separate the UCAS/LCAS operation timing intentionally. However skew between  
UCAS/LCAS are allowed under the following conditions.  
1. Each of the UCAS/LCAS should satisfy the timing specifications individually.  
2. Different operation mode for upper/lower byte is not allowed; such as following.  
RAS  
Delayed write  
UCAS  
Early write  
LCAS  
WE  
3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP tUL) is  
satisfied, fast page mode can be performed.  
RAS  
UCAS  
LCAS  
t
UL  
4. Byte control operation by remaining UCAS or LCAS high is guaranteedi  
14  
HM514260D, HM51S4260D Series  
Timing Waveforms*28  
Read Cycle  
t
RC  
t
RAS  
RAS  
t
RP  
t
T
t
RSH  
t
t
CRP  
CAS  
t
RCD  
t
CSH  
UCAS  
LCAS  
t
t
t
RAL  
ASR  
RAD  
t
t
CAH  
t
ASC  
RAH  
Column  
Address  
Row  
t
t
t
RCH  
RRH  
RCS  
WE  
t
CAC  
t
t
OFF1  
AA  
High-Z  
Dout  
Dout  
Din  
t
RAC  
t
OFF2  
t
t
t
CDD  
OAC  
DZC  
High-Z  
t
ODD  
t
DZO  
OE  
15  
HM514260D, HM51S4260D Series  
Early Write Cycle  
t
RC  
t
RAS  
t
RAS  
RP  
t
T
t
RSH  
t
t
RCD  
CAS  
t
CRP  
t
CSH  
UCAS  
LCAS  
t
ASR  
t
t
t
ASC  
CAH  
RAH  
Row  
Address  
Column  
t
t
WCH  
WCS  
WE  
t
t
DH  
DS  
Din  
Din  
High-Z  
Dout  
16  
HM514260D, HM51S4260D Series  
Delayed Write Cycle  
t
RC  
t
t
RAS  
RP  
RAS  
t
t
CRP  
CSH  
t
T
t
t
RCD  
RSH  
t
UCAS  
LCAS  
CAS  
t
t
t
CWL  
ASC  
ASR  
t
RWL  
t
RAH  
t
CAH  
Column  
Address  
Row  
t
t
RCS  
WP  
WE  
t
DH  
t
DS  
Din  
Din  
t
t
OEH  
DZC  
t
ODD  
t
DZO  
High-Z  
Dout  
*Invalid Dout  
t
COD  
t
OFF2  
OE  
* Do not enable Dout during delayed write cycle.  
17  
HM514260D, HM51S4260D Series  
Read-Modify-Write Cycle  
t
RWC  
t
RP  
RAS  
t
T
t
t
t
CRP  
RCD  
CAS  
UCAS  
LCAS  
t
RAD  
t
ASR  
t
CAH  
t
ASC  
t
RAH  
Address  
Column  
t
Row  
t
CWL  
CWD  
t
RCS  
t
t
RWL  
AWD  
t
WP  
WE  
t
AA  
t
RWD  
t
CAC  
t
t
DH  
t
DS  
RAC  
t
DZC  
High-Z  
Din  
Din  
Dout  
Dout  
t
OAC  
t
t
OEH  
OFF2  
ODD  
t
t
DZO  
OE  
18  
HM514260D, HM51S4260D Series  
RAS-Only Refresh Cycle  
t
RC  
t
t
RP  
RAS  
RAS  
t
t
CRP  
T
t
CRP  
t
RPC  
UCAS  
LCAS  
t
RAH  
t
ASR  
Row  
Address  
Dout  
High-Z  
19  
HM514260D, HM51S4260D Series  
CAS-Before-RAS Refresh Cycle  
t
t
RC  
RC  
t
t
t
t
RAS  
t
*
*
RP  
RAS  
RP  
RP  
RAS  
t
T
t
t
t
t
RPC  
CRP  
RPC  
CPN  
t
t
t
t
t
CHR  
CSR  
CHR  
CPN  
CSR  
UCAS  
LCAS  
Address  
t
OFF1  
High-Z  
Dout  
_
Do not extend t  
> t  
(max).  
RAS  
RAS  
*
Untested self refresh mode may be  
activated and loss of data may be  
resulted (HM514260D/DL).  
20  
HM514260D, HM51S4260D Series  
Fast Page Mode Read Cycle  
t
t
RP  
RASC  
t
RHCP  
RAS  
t
t
T
CRP  
t
RSH  
t
t
PC  
CSH  
t
CAS  
t
t
t
t
t
CP  
CAS  
RCD  
CP  
CAS  
UCAS  
LCAS  
t
RAD  
t
t
RAL  
CAH  
t
CAH  
t
CAH  
t
ASC  
t
t
t
RAH  
t
ASC  
ASR  
ASC  
Address  
WE  
Row  
Column  
Column  
Column  
t
t
t
t
RRH  
RCS  
RCS  
t
t
t
t
RCH  
RCH  
RCS  
DZC  
RCH  
t
CDD  
t
DZC  
t
CDD  
t
t
DZC  
CDD  
High-Z  
High-Z  
High-Z  
Din  
t
ODD  
t
t
CAC  
AA  
CAC  
t
t
ODD  
CAC  
t
t
t
AA  
AA  
t
t
t
ACP  
ACP  
RAC  
t
OFF1  
t
t
OFF1  
OFF1  
t
DZO  
High-Z  
Dout  
Dout  
Dout  
Dout  
t
OAC  
t
ODD  
t
DZO  
t
DZO  
t
OAC  
t
t
OFF2  
t
OFF2  
OFF2  
OE  
t
OAC  
21  
HM514260D, HM51S4260D Series  
Fast Page Mode Early Write Cycle  
t
t
RP  
RASC  
RAS  
t
t
t
PC  
RSH  
CAS  
CSH  
t
T
t
t
t
t
t
t
t
t
CRP  
CAS  
RCD  
CP  
CAS  
CAH  
CP  
UCAS  
LCAS  
t
t
t
ASC  
t
t
CAH  
t
t
CAH  
ASC  
ASR  
RAH  
ASC  
Address  
Row  
Column  
Column  
Column  
t
t
WCS  
t
t
t
WCS  
WCH  
WCS  
WCH  
t
WCH  
WE  
t
t
t
DS  
DS  
DS  
t
t
DH  
DH  
t
DH  
Din  
Din  
Din  
Din  
High-Z  
Dout  
22  
HM514260D, HM51S4260D Series  
Fast Page Mode Delayed Write Cycle  
t
t
RP  
RASC  
RAS  
t
CSH  
t
t
RSH  
CAS  
t
t
PC  
T
t
CRP  
t
t
t
t
CP  
t
RCD  
CAS  
CP  
CAS  
UCAS  
LCAS  
t
t
ASC  
ASR  
t
CAH  
t
t
ASC  
t
CAH  
t
RAH  
t
CWL  
t
CAH  
ASC  
Address  
Column  
Column  
Column  
Row  
t
CWL  
t
CWL  
t
t
WP  
t
RCS  
t
t
RWL  
WP  
WP  
WE  
t
t
t
RCS  
t
DH  
DH  
t
t
RCS  
DH  
t
DS  
t
DS  
DS  
Din  
Din  
Din  
Dout  
OE  
Din  
t
OEH  
High-Z  
t
ODD  
23  
HM514260D, HM51S4260D Series  
Fast Page Mode Read-Modify-Write Cycle  
t
t
RP  
RASC  
RAS  
t
t
RCD  
PCM  
t
T
t
CRP  
t
t
CP  
CP  
t
t
t
CAS  
CAS  
CAS  
UCAS  
LCAS  
t
RAD  
t
t
RAH  
ACP  
t
t
CAH  
t
t
CAH  
CAH  
t
ASR  
t
ASC  
ASC  
t
ASC  
Column  
Column  
t
CPW  
Row  
Column  
Address  
t
CWL  
RWL  
WP  
t
t
AWD  
AWD  
t
t
CWL  
CWL  
t
t
t
t
AWD  
CWD  
CWD  
t
t
RCS  
RCS  
t
t
t
t
WP  
RCS  
CWD  
t
t
CPW  
RWD  
t
WP  
WE  
t
t
ACP  
DS  
t
t
DS  
DS  
t
CAC  
t
t
DZC  
t
CAC  
DZC  
t
t
t
DH  
t
DH  
DH  
DZC  
High-Z  
High-Z  
AA  
High-Z  
Din  
t
Din  
Din  
t
Din  
t
AA  
t
t
CAC  
t
t
DZO  
RAC  
t
OAC  
t
t
t
OAC  
OAC  
Dout  
OFF2  
OEH  
OEH  
OEH  
Dout  
Dout  
OFF2  
Dout  
t
t
t
OFF2  
t
t
DZO  
DZO  
OE  
t
t
ODD  
t
ODD  
ODD  
24  
HM514260D, HM51S4260D Series  
Self Refresh Cycle*24, 25, 26, 27  
t
t
t
RASS  
RP  
RPS  
RAS  
t
T
t
t
CRP  
RPC  
t
t
CSR  
CPN  
t
CHS  
UCAS  
LCAS  
Address  
t
OFF1  
High-Z  
Dout  
25  
HM514260D, HM51S4260D Series  
Package Dimensions  
HM514260DJ/DLJ Series  
HM51S260DJ/DLJ Series (CP-40D)  
Unit: mm  
25.80  
26.16 Max  
40  
21  
20  
1
0.74  
1.30 Max  
9.40 ± 0.25  
1.27  
0.43 ± 0.10  
0.41 ± 0.08  
0.10  
Hitachi Code  
JEDEC Code  
EIAJ Code  
Weight  
CP-40D  
SC-640  
1.73 g  
26  
HM514260D, HM51S4260D Series  
HM514260DTT/DLTT Series  
HM51S4260DTT/DLTT Series (TTP-44/40DB)  
Unit: mm  
18.41  
18.81 Max  
44  
35 32  
23  
22  
1
10 13  
0.80  
0.80  
M
0.13  
0.27 ± 0.07  
0.25 ± 0.05  
11.76 ± 0.20  
0 – 5°  
1.005 Max  
0.50 ± 0.10  
0.10  
2.40  
Hitachi Code  
JEDEC Code  
EIAJ Code  
Weight  
TTP-44/40DB  
MO-133BA  
SC-504-8C  
0.43 g  
27  
HM514260D, HM51S4260D Series  
When using this document, keep the following in mind:  
1. This document may, wholly or partially, be subject to change without notice.  
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of  
this document without Hitachi’s permission.  
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other  
reasons during operation of the user’s unit according to this document.  
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and  
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual  
property claims or other problems that may result from applications based on the examples described  
herein.  
5. No license is granted by implication or otherwise under any patents or other rights of any third party or  
Hitachi, Ltd.  
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL  
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such  
use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested  
to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL  
APPLICATIONS.  
Hitachi, Ltd.  
Semiconductor & IC Div.  
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan  
Tel: Tokyo (03) 3270-2111  
Fax: (03) 3270-5109  
For further information write to:  
Hitachi America, Ltd.  
Semiconductor & IC Div.  
2000 Sierra Point Parkway  
Brisbane, CA. 94005-1835  
U S A  
Hitachi Europe GmbH  
Electronic Components Group  
Continental Europe  
Dornacher Straße 3  
D-85622 Feldkirchen  
München  
Hitachi Europe Ltd.  
Electronic Components Div.  
Northern Europe Headquarters  
Whitebrook Park  
Lower Cookham Road  
Maidenhead  
Hitachi Asia Pte. Ltd.  
16 Collyer Quay #20-00  
Hitachi Tower  
Singapore 0104  
Tel: 535-2100  
Tel: 415-589-8300  
Fax: 535-1533  
Fax: 415-583-4207  
Tel: 089-9 91 80-0  
Fax: 089-9 29 30 00  
Berkshire SL6 8YA  
United Kingdom  
Hitachi Asia (Hong Kong) Ltd.  
Unit 706, North Tower,  
World Finance Centre,  
Harbour City, Canton Road  
Tsim Sha Tsui, Kowloon  
Hong Kong  
Tel: 0628-585000  
Fax: 0628-778322  
Tel: 27359218  
Fax: 27306071  
28  
HM514260D, HM51S4260D Series  
Revision Record  
Rev.  
0.0  
Date  
Contents of Modification  
Initial issue  
Drawn by  
Approved by  
Apr. 3, 1996  
Dec. 2, 1996  
H. Hisakawa S. Suzuki  
1.0  
Deletion of preliminary  
AC Characteristics  
Addition of note 24  
Change of note 28  
Addition of note 4 to Notes concerning 2CAS control  
Timing Waveforms  
Deletion of notes about undefined pins  
29  

HM514260DLJ-7 相关器件

型号 制造商 描述 价格 文档
HM514260DLJ-8 HITACHI Fast Page DRAM, 256KX16, 80ns, CMOS, PDSO40, 0.400 INCH, PLASTIC, SOJ-40 获取价格
HM514260DLJI-7 ETC x16 Fast Page Mode DRAM 获取价格
HM514260DLJI-8 ETC x16 Fast Page Mode DRAM 获取价格
HM514260DLTT-6 HITACHI Fast Page DRAM, 256KX16, 60ns, CMOS, PDSO40, 0.400 INCH, PLASTIC, TSOP2-44/40 获取价格
HM514260DLTT-6R ETC x16 Fast Page Mode DRAM 获取价格
HM514260DLTT-7 ETC x16 Fast Page Mode DRAM 获取价格
HM514260DLTT-8 ETC x16 Fast Page Mode DRAM 获取价格
HM514260DTT-6 HITACHI Fast Page DRAM, 256KX16, 60ns, CMOS, PDSO40, 0.400 INCH, PLASTIC, TSOP2-44/40 获取价格
HM514260DTT-6R ETC x16 Fast Page Mode DRAM 获取价格
HM514260DTT-7 HITACHI Fast Page DRAM, 256KX16, 70ns, CMOS, PDSO40, 0.400 INCH, PLASTIC, TSOP2-44/40 获取价格

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