HM514265DLJ-6R [HITACHI]
EDO DRAM, 256KX16, 60ns, CMOS, PDSO40, 0.400 INCH, PLASTIC, SOJ-40;
| 型号： | HM514265DLJ-6R |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | EDO DRAM, 256KX16, 60ns, CMOS, PDSO40, 0.400 INCH, PLASTIC, SOJ-40 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总33页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM514265D Series
HM51S4265D Series
262144-word × 16-bit Dynamic RAM
ADE-203-581A (Z)
Rev. 1.0
Nov. 28, 1996
Description
The Hitachi HM51(S)4265D Series is a CMOS dynamic RAM organized 262,144-word × 16-bit.
HM51(S)4265D Series has realized higher density, higher performance and various functions by employing
0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4265D
Series offers Extended Data Out (EDO) Page Mode as a high speed access mode. Multiplexed address input
permits the HM51(S)4265D to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-
pin plastic TSOPII. Internal refresh timer enables HM51S4265D Series self reflesh operation.
Features
•
Single 5 V (±5%) (HM51(S)4265D-5/6R)
(±10%) (HM51(S)4265D-6/7/8)
•
•
Access time: 50 ns/60 ns/70 ns/80 ns (max)
Power dissipation
Active mode: 945 mW/945 mW/990 mW/825 mW/715 mW (max)
Standby mode: 10.5 mW (max) (HM51(S)4265D-5/6R)
11 mW (max) (HM51(S)4265D-6/7/8)
1.05 mW (max) (L-version) (HM51(S)4265DL-5/6R)
1.1 mW (max) (L-version) (HM51(S)4265DL-6/7/8)
EDO page mode capability
•
•
512 refresh cycles : 8 ms
128 ms (L-version)
•
2 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
•
•
•
2CAS-byte control
Battery backup operation (L-version)
Self refresh operation (HM51S4265D Series)
HM514265D Series, HM51S4265D Series
Ordering Information
Type No.
Access time
Package
HM514265DJ-5
HM514265DJ-6
HM514265DJ-6R
HM514265DJ-7
HM514265DJ-8
50 ns
60 ns
60 ns
70 ns
80 ns
400-mil 40-pin plastic SOJ (CP-40D)
HM514265DLJ-5
HM514265DLJ-6
HM514265DLJ-6R
HM514265DLJ-7
HM514265DLJ-8
50 ns
60 ns
60 ns
70 ns
80 ns
HM51S4265DJ-5
HM51S4265DJ-6
HM51S4265DJ-6R
HM51S4265DJ-7
HM51S4265DJ-8
50 ns
60 ns
60 ns
70 ns
80 ns
HM51S4265DLJ-5
HM51S4265DLJ-6
HM51S4265DLJ-6R
HM51S4265DLJ-7
HM51S4265DLJ-8
50 ns
60 ns
60 ns
70 ns
80 ns
HM514265DTT-5
HM514265DTT-6
HM514265DTT-6R
HM514265DTT-7
HM514265DTT-8
50 ns
60 ns
60 ns
70 ns
80 ns
400-mil 44-pin plastic TSOPII (TTP-44/40DB)
HM514265DLTT-5
HM514265DLTT-6
HM514265DLTT-6R
HM514265DLTT-7
HM514265DLTT-8
50 ns
60 ns
60 ns
70 ns
80 ns
HM51S4265DTT-5
HM51S4265DTT-6
HM51S4265DTT-6R
HM51S4265DTT-7
HM51S4265DTT-8
50 ns
60 ns
60 ns
70 ns
80 ns
HM51S4265DLTT-5
HM51S4265DLTT-6
HM51S4265DLTT-6R
HM51S4265DLTT-7
HM51S4265DLTT-8
50 ns
60 ns
60 ns
70 ns
80 ns
2
HM514265D Series, HM51S4265D Series
Pin Arrangement
HM514265DTT/DLTT Series
HM51S4265DTT/DLTT Series
HM514265DJ/DLJ Series
HM51S4265DJ/DLJ Series
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
VSS
VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
I/O15
I/O14
I/O13
I/O12
VSS
I/O15
I/O14
I/O13
I/O12
VSS
2
3
4
5
I/O11
I/O10
I/O9
6
I/O11
I/O10
I/O9
I/O8
NC
7
8
I/O8
9
10
11
12
13
LCAS
UCAS
OE
NC
NC
WE
RAS
NC
A0
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
NC
NC
LCAS
UCAS
OE
WE
RAS 14
NC
A8
15
16
17
18
19
20
A7
A8
A0
A6
A7
A1
A5
A1
A6
A2
A4
A2
A5
A3
VSS
A3
A4
VCC
VCC
V
SS
(Top view)
(Top view)
Pin Description
Pin name
Function
Address input
— Row/Refresh address A0 to A8
A0 to A8
— Column address
Data-in/data-out
Row address strobe
Column address strobe
Read/write enable
Output enable
A0 to A8
I/O0 to I/O15
RAS
UCAS, LCAS
WE
OE
VCC
VSS
NC
Power supply
Ground
No connection
3
HM514265D Series, HM51S4265D Series
Block Diagram
I/O4
buffer
I/O11
buffer
I/O3
I/O3
I/O2
I/O2
I/O1
I/O1
I/O0
I/O0
I/O15
I/O14
I/O13 I/O12
I/O13 I/O12
I/O4
I/O5
I/O6
I/O7
I/O11
I/O10
I/O9
I/O15
buffer
I/O14
buffer
buffer buffer
buffer buffer
buffer buffer
I/O5
buffer
I/O10
buffer
I/O6
buffer
I/O9
buffer
I/O7
buffer
I/O8
buffer
I/O8
Selector
Selector
Selector
Selector
Row
driver
Row
driver
Row
driver
Row Row
driver driver
Row
driver
Row
driver
Row
driver
WE
RAS
UCAS
Row Decoder & Peripheral Circuit
LCAS
OE
Row
driver
Row Row
driver driver
Row
driver
Row
driver
Row Row
driver driver
Row
driver
Column address buffer
CA0 to CA8
Row address buffer
RA0 to RA8
Address A0 to A8
4
HM514265D Series, HM51S4265D Series
Operation Mode
The HM51(S)4265D series has the following 11 operation modes.
1. Read cycle
2. Early write cycle
3. Delayed write cycle
4. Read-modify-write cycle
5. RAS-only refresh cycle
6. CAS-before-RAS refresh cycle
7. Self refresh cycle (HM51S4265D)
8. EDO page mode read cycle
9. EDO page mode early write cycle
10. EDO page mode delayed write cycle
11. EDO page mode read-modify-write cycle
Inputs
RAS
LCAS
UCAS
WE
D
OE
Output
Open
Operation
H
H
H
D
Standby
H
L
L
H
L
Valid
Standby
L
L
L
H
L
Valid
Read cycle
L
L
L
L*2
L*2
H to L
D
D
Open
Early write cycle
L
L
L
H
Undefined
Valid
Delayed write cycle
Read-modify-write cycle
RAS-only refresh cycle
CAS-before-RAS refresh cycle
Self refresh cycle (HM51S4265D)
L
L
L
L to H
L
H
H
D
D
Open
H to L
H
L
D
Open
L
H
L
L
L
L
L
L
L
H to L
H to L
H to L
H to L
L
H to L
H to L
H to L
H to L
L
H
L
Valid
EDO page mode read cycle
L*2
L*2
H to L
H
D
Open
EDO page mode early write cycle
EDO page mode delayed write cycle
EDO page mode read-modify-write cycle
Read cycle (Output disabled)
H
Undefined
Valid
L to H
H
Open
Notes: 1. H: High(inactive) L: Low(active) D: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ V ≤ VIL
IN
(max))
2. tWCS ≥ 0 ns
Early write cycle
tWCS < 0 ns
Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output HIZ control are done independently by each UCAS, LCAS.
ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected.
5
HM514265D Series, HM51S4265D Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +7.0
–1.0 to +7.0
50
VCC
V
Iout
PT
mA
W
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Min
0
Typ
0
Max
0
Unit
Notes
2
Supply voltage
VSS
V
V
V
V
V
VCC (HM51(S)4265D-5/6R)
4.75
4.5
2.4
–1.0
5.0
5.0
—
5.25
5.5
6.5
0.8
1, 2
1, 2
1
VCC (HM51(S)4265D-6/7/8)
Input high voltage
Input low voltage
VIH
VIL
—
1
Notes: 1. All voltage referred to VSS.
2. The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
6
HM514265D Series, HM51S4265D Series
DC Characteristics
(Ta = 0 to 70°C, VCC = 5 V ±5%, VSS = 0 V) (HM51(S)4265D-5/6R)*5
(Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)(HM51(S)4265D-6/7/8) *5
HM514265D, HM51S4265D
-5
-6/6R
-7
-8
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Test conditions
Operating current*1, ICC1
*
—
—
—
160
2
—
—
—
150
2
—
—
—
140
2
—
—
—
125 mA RAS cycling
UCAS or LCAS cycling
RC = min
2
t
Standby current
ICC2
2
mA TTL interface
RAS, UCAS, LCAS = VIH
Dout = High-Z
1
1
1
1
mA CMOS interface
RAS, UCAS, LCAS, WE,
OE ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
—
200
—
200
—
200
—
200 µA CMOS interface
RAS, UCAS, LCAS, WE,
OE ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh
ICC3
ICC6
ICC4
ICC10
—
—
—
—
150
150
180
300
—
—
—
—
140
140
180
300
—
—
—
—
130
130
150
300
—
—
—
—
110 mA tRC = min
current*2
CAS-before-RAS
110 mA tRC = min
130 mA tHPC = min
refresh current*2
EDO page mode
current*1, *3
Battery backup
current*4
300 µA Standby: CMOS interface
Dout = High-Z
(Standby with CBR
refresh) (L-version)
CBR refresh: tRC = 250 µs
t
RAS ≤ 1 µs,
UCAS, LCAS = VIL
WE, OE = VIH
Self-refresh mode ICC11
current
(HM51S4265D)
—
—
1
—
—
1
—
—
1
—
—
1
mA CMOS interface, RAS,
UCAS, LCAS ≤ 0.2 V,
Dout = High-Z
Self-refresh mode ICC11
current
(HM51S4265DL)
200
200
200
200 µA CMOS interface, RAS,
UCAS, LCAS ≤ 0.2 V,
Dout = High-Z
Input leakage
current
ILI
–10 10
–10 10
–10 10
–10 10
–10 10
–10 10
–10 10
µA 0 V ≤ Vin ≤ 7 V
Output leakage
current
ILO
–10 10
µA 0 V ≤ Vout ≤ 7 V
Dout = disable
7
HM514265D Series, HM51S4265D Series
DC Characteristics
(Ta = 0 to 70°C, VCC = 5 V ±5%, VSS = 0 V) (HM51(S)4265D-5/6R)*5
(Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)(HM51(S)4265D-6/7/8) *5 (cont.)
HM514265D, HM51S4265D
-5
-6/6R
-7
-8
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Test conditions
Output high voltage VOH
Output low voltage VOL
2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC
0.4 0.4 0.4 0.4
V
V
High Iout = –2 mA
Low Iout = 2 mA
0
0
0
0
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output
open condition.
2. Address can be changed twice or less while RAS = VIL.
3. Address can be changed once or less within one EDO page cycle.
4. VIH ≥ VCC – 0.2 V, 0 ≤ VIL ≤ 0.2 V, Address can be changed once or less while RAS = VIL.
5. All the VCC pins should be supplied with the same voltage. And all the VSS pins should be supplied
with the same voltage.
Capacitance (Ta = +25°C, VCC = 5 V ±5%) (HM51(S)4265D-5/6R)
(Ta = +25°C, VCC = 5 V ±10%) (HM51(S)4265D-6/7/8)
Parameter
Symbol
CI1
Typ
—
Max
5
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (Data-in, Data-out)
1
CI2
—
7
pF
1
CI/O
—
10
pF
1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. RAS, UCAS and LCAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±5%, VSS = 0 V)
(HM51(S)4265D-5/6R)*1, *14, *15, *17, *18
(Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)
(HM51(S)4265D-6/7/8)*1, *14, *15, *17, *18
Test Conditions
•
•
•
•
•
Input rise and fall time : 2 ns
Input levels: VIL = 0 V, VIH = 3.0 V
Input timing reference levels : 0.8 V, 2.4 V
Output timing reference levels : 0.8 V, 2.0 V·
Output load : 1 TTL gate + CL (50 pF) (Including scope and jig)
8
HM514265D Series, HM51S4265D Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM514265D, HM51S4265D
-5
-6/-6R
Min
-7
-8
Parameter
Symbol Min
Max
Max
Min
124
Max
Min Max
Unit Notes
Random read or
write cycle time
tRC
84
—
104
—
—
144
—
ns
RAS precharge time
RAS pulse width
CAS pulse width
tRP
30
50
8
—
40
—
50
—
60
—
ns
tRAS
tCAS
tASR
10000 60
10000 10
10000 70
10000 13
10000 80
10000 15
10000 ns
10000 ns
27
28
Row address setup
time
0
—
0
—
0
—
0
—
ns
Row address hold time tRAH
8
0
—
—
10
0
—
—
10
0
—
—
10
0
—
—
ns
ns
Column address setup tASC
time
19
19
Column address
hold time
tCAH
8
—
10
—
13
—
15
—
ns
RAS to CAS delay time tRCD
18
10
35
25
20
15
45
30
20
15
50
35
20
15
60
40
ns
ns
8
9
RAS to column
tRAD
address delay time
RAS hold time
CAS hold time
tRSH
tCSH
13
40
10
—
—
—
15
48
10
—
—
—
18
58
10
—
—
—
20
68
10
—
—
—
ns
ns
ns
29
20
CAS to RAS precharge tCRP
time
OE to Din delay time
tODD
13
0
—
—
—
15
0
—
—
—
18
0
—
—
—
20
0
—
—
—
ns
ns
ns
OE delay time from Din tDZO
CAS setup time
from Din
tDZC
tT
0
0
0
0
Transition time
(rise and fall)
2
50
2
50
2
50
2
50
ns
7
Refresh period
tREF
tREF
—
—
8
—
—
8
—
—
8
—
—
8
ms
ms
Refresh period
(L-version)
128
128
128
128
9
HM514265D Series, HM51S4265D Series
Read Cycle
HM514265D, HM51S4265D
-5
-6/-6R
-7
-8
Parameter
Symbol Min Max Min
Max Min
Max Min Max Unit Notes
Access time from RAS
Access time from CAS
tRAC
tCAC
—
—
—
—
0
50
15
25
15
—
—
—
—
—
0
60
15
30
15
—
—
—
—
—
0
70
20
35
20
—
—
—
—
—
0
80
20
40
20
—
ns
ns
ns
ns
ns
2, 3
3, 4, 13
3, 5, 13
3, 23
19
Access time from address tAA
Access time from OE
tOAC
tRCS
Read command setup
time
Read command hold time tRCH
to CAS
0
—
—
—
—
0
—
—
—
—
0
—
—
—
—
0
—
—
—
—
ns
ns
ns
ns
16, 20
16
Read command hold time tRRH
to RAS
0
0
0
0
Column address to
RAS lead time
tRAL
tCAL
25
13
30
18
35
23
40
28
Column address to
CAS lead time
Output buffer turn-off time tOFF1
—
—
13
13
—
—
15
15
—
—
15
15
—
—
15
15
ns
ns
6, 25
6
Output buffer turn-off time tOFF2
to OE
CAS to Din delay time
RAS to Din delay time
WE to Din delay time
OE pulse width
tCDD
tRDD
tWDD
tOEP
tOFR
tWEZ
tOH
13
13
13
13
—
—
5
—
—
—
—
13
13
—
—
15
15
15
15
—
—
5
—
—
—
—
15
15
—
—
18
18
18
20
—
—
5
—
—
—
—
15
15
—
—
20
20
20
20
—
—
5
—
—
—
—
15
15
—
—
ns
ns
ns
ns
ns
ns
ns
ns
23
Turn-off to RAS
6, 25
6
Turn-off to WE
Output data hold time
Output data hold time
tOHR
5
5
5
5
from RAS
Read command hold time tRCHR
from RAS
50
15
25
—
—
—
60
15
30
—
—
—
70
18
35
—
—
—
80
20
40
—
—
—
ns
ns
ns
Read command hold time tRCHC
from CAS
Read command hold time tRCHA
from column address
10
HM514265D Series, HM51S4265D Series
Write Cycle
HM514265D, HM51S4265D
-5 -6/-6R
Symbol Min Max Min Max Min
-7
-8
Parameter
Max Min
Max Unit Notes
Write command setup time tWCS
Write command hold time tWCH
Write command pulse width tWP
0
8
8
8
—
—
—
—
0
—
—
—
—
0
—
—
—
—
0
—
—
—
—
ns
ns
ns
ns
10, 19
19
10
10
10
13
10
13
15
10
15
Write command to RAS
tRWL
lead time
Write command to CAS
lead time
tCWL
8
—
10
—
13
—
15
—
ns
21
Data-in setup time
Data-in hold time
tDS
tDH
0
8
—
—
0
—
—
0
—
—
0
—
—
ns
ns
11, 21
11, 21
10
13
15
Read-Modify-Write Cycle
HM514265D, HM51S4265D
-5 -6/-6R
-7
-8
Parameter
Symbol Min Max Min Max Min
Max Min Max Unit Notes
Read-modify-write cycle
time
tRWC
109
—
133
—
159
—
183
—
ns
RAS to WE delay time
CAS to WE delay time
tRWD
tCWD
tAWD
65
30
42
—
—
—
77
32
47
—
—
—
90
38
55
—
—
—
102
42
—
—
—
ns
ns
ns
10
10
10
Column address to WE
delay time
62
OE hold time from WE
tOEH
13
—
15
—
18
—
20
—
ns
11
HM514265D Series, HM51S4265D Series
Refresh Cycle
HM514265D, HM51S4265D
-5 -6/-6R
Symbol Min Max Min Max Min Max Min
-7
-8
Parameter
Max Unit Notes
CAS setup time
tCSR
tCHR
tRPC
tCPN
10
10
10
8
—
—
—
—
10
10
10
10
—
—
—
—
10
10
10
13
—
—
—
—
10
10
10
15
—
—
—
—
ns
ns
ns
ns
19
20
19
22
(CBR refresh cycle)
CAS hold time
(CBR refresh cycle)
RAS precharge to CAS
hold time
CAS precharge time in
normal mode
EDO Page Mode Cycle
HM514265D, HM51S4265D
-5
Symbol Min
-6/-6R
-7
Min Max
-8
Min Max
Parameter
Max
Min Max
Unit Notes
EDO page mode
cycle time
tHPC
20
—
25
—
30
—
35
—
ns
24
EDO page mode CAS tCP
precharge time
8
—
10
—
13
—
15
—
ns
EDO page mode RAS tRASC
—
—
30
5
100000 —
100000 —
100000 —
100000 ns
12
pulse width
Access time from CAS tACP
precharge
28
—
—
—
—
—
—
35
5
35
—
—
—
—
—
—
40
5
40
—
—
—
—
—
—
45
5
45
—
—
—
—
—
ns
ns
ns
ns
ns
ns
3, 13,
17
RAS hold time from
CAS precharge
tRHCP
tDOH
tCOL
Output data hold
time from CAS low
26
CAS hold time
referred OE
8
10
5
13
5
20
5
CAS to OE setup
tCOP
tRCHP
5
time
Read command
hold time from
CAS precharge
30
35
40
45
12
HM514265D Series, HM51S4265D Series
EDO Page Mode Read-Modify-Write Cycle
HM514265D, HM51S4265D
-5 -6/-6R
Symbol Min Max Min
-7
-8
Parameter
Max Min Max Min Max Unit
Notes
EDO page mode read-
modify-write cycle time
tHPCM
57
—
66
—
77
60
—
—
86
67
—
—
ns
ns
EDO page mode read-
modify-write cycle CAS
precharge to WE delay
time
tCPW
45
—
52
—
10
Self Refresh Mode
HM51S4265D
-5
-6/-6R
-7
Max Min
-8
Parameter
Symbol Min
Max Min
Max Min
Max Unit Notes
RAS pulse width
tRASS
tRPS
tCHS
100
—
—
—
100
110
–50
—
—
—
100
130
–50
—
—
—
100
150
–50
—
—
—
ns
ns
ns
30, 31,
32
(self refresh)
RAS precharge time
(self refresh)
90
CAS hold time
(self refresh)
–50
21
Notes: 1. AC measurements assume tT = 2 ns, VIH = 3.0 V, VIL = 0.0 V
2. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
3. Measured with a load circuit equivalent to 1 TTL loads and 50 pF.
4. Assumes that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max).
5. Assumes that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max).
6. tOFF1 (max), tOFF2 (max), tOFR (max) and tWEZ (max) define the time at which the output achieves the
open circuit condition and is not referred to output voltage levels.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH and VIL.
8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
10. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only: if tWCS ≥ tWCS (min), the cycle is an early write cycle and the data out
pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD
≥
t
CWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output
will contain data read from the selected cell; if neither of the above sets of conditions is satisfied,
the condition of the data out (at access time) is indeterminate.
13
HM514265D Series, HM51S4265D Series
11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge
in a delayed write or a read-modify-write cycle.
12. tRASC defines RAS pulse width in EDO page mode cycles.
13. Access time is determined by the longest among tAA, tCAC and tACP
.
14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization
cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is
used, a minimum of eight CAS-before-RAS refresh cycles is required.
15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
16. Either tRCH or tRRH must be satisfied for a read cycle.
17. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device.
UCAS and LCAS cannot be staggered within the same write/read cycles.
18. All the VCC and VSS pins shall be supplied with the same voltages.
19. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS.
20. tCRP, tCHR, tACP, tRCH and tCPW are determined by the later rising edge of UCAS or LCAS.
21. tCWL, tDH, tDS and tCHS should be satisfied by both UCAS and LCAS.
22. tCPN and tCP are determined by the time that both UCAS and LCAS are high.
23. When output buffers are enabled once, sustain the low impedance state until valid data is obtained.
When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS
line noise, which causes to degrade VIH min/VIL max level.
24. tHPC (min) can be achieved during a series of EDO page mode early write cycles or EDO page
mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle
(EDO page mode mix cycle (1), (2)), minimum value of CAS cycle tHPC (tCAS + tCP + 2tT) becomes
greater than the specified tHPC (min) value.
25. tOFF1 and tOFR are determined by the later rising edge of RAS or CAS.
26. tDOH defines the time at which the output level satisfies the output timing reference levels.
Measured with the test conditions.
27. tRAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle.
28. tCAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle.
29. tCSH (min) can be achieved when tRCD ≤ tCSH (min) – tCAS (min).
30. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition
state from normal operation mode to self refresh mode. If tRASS > 100 µs, then RAS precharge time
should use tRPS instead of tRP.
31. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed within 15.6 µs immediately after exiting from and before entering into
self refresh mode.
32. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of
distributed CBR refresh with 15.6 µs interval should be executed within 8 ms immediately after
exiting from and before entering into the self refresh mode.
33. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self
refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
34. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ V ≤ VIL (max))
IN
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL.
14
HM514265D Series, HM51S4265D Series
Notes concerning 2CAS control
1. Each of the UCAS/LCAS should satisfy the timing specifications individually.
2. Different operation mode for upper/lower byte is not allowed; such as following.
RAS
Delayed write
Early write
UCAS
LCAS
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is
satisfied, fast page mode can be performed.
RAS
UCAS
LCAS
t
UL
4. Byte control operation by remaining UCAS or LCAS high is guaranteed.
15
HM514265D Series, HM51S4265D Series
Timing Waveforms*34
Read Cycle
t
t
RC
RAS
RAS
t
RP
t
CRP
t
T
t
RSH
t
RCD
t
t
CAS
CSH
UCAS
LCAS
t
t
RAD
RAL
t
t
CAH
ASR tRAH
tASC
Row
Column
Address
t
t
RCHA
RDD
t
CAL
t
t
OH
RCS
t
OHR
t
RCHR
t
t
RCH
RCHC
t
RRH
WE
t
t
OFR
CAC
t
AA
t
OFF1
Dout
t
Dout
t
RAC
OFF2
t
WEZ
t
t
DZC
OAC
t
CDD
High-Z
Din
t
WDD
t
t
ODD
DZO
t
OEP
OE
16
HM514265D Series, HM51S4265D Series
Early Write Cycle
t
RC
t
RAS
t
RAS
RP
t
T
t
RSH
t
t
RCD
CAS
t
CRP
t
CSH
UCAS
LCAS
t
ASR
t
t
t
ASC
CAH
RAH
Row
Address
Column
t
t
WCH
WCS
WE
t
t
DH
DS
Din
Din
High-Z
Dout
17
HM514265D Series, HM51S4265D Series
Delayed Write Cycle
t
t
RC
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
RCD
RSH
t
t
CAS
T
UCAS
LCAS
t
t
ASC
CWL
t
t
ASR
RAH
t
RWL
t
CAH
Row
Column
Address
t
t
RCS
WP
WE
t
DS
t
DH
High-Z
Din
Din
t
DZC
t
ODD
t
OEH
t
DZO
Dout
Invalid Dout*
t
OFF2
OE
*
* Do not enable Dout during delayed write cycle.
18
HM514265D Series, HM51S4265D Series
Read-Modify-Write Cycle
t
t
RWC
RAS
t
RP
RAS
t
T
t
t
t
CRP
RCD
CAS
UCAS
LCAS
t
RAD
t
ASR
t
t
t
ASC
CAH
RAH
Address
Row
Column
t
t
CWL
CWD
t
RCS
t
t
RWL
AWD
t
WP
WE
t
AA
t
RWD
t
CAC
t
t
DH
t
DS
RAC
t
DZC
High-Z
Din
Din
Dout
Dout
t
OAC
t
t
OEH
OFF2
ODD
t
t
DZO
t
OEP
OE
19
HM514265D Series, HM51S4265D Series
RAS-Only Refresh Cycle
t
RC
t
t
RP
RAS
RAS
t
T
t
CRP
t
t
RPC
CRP
UCAS
LCAS
t
t
RAH
ASR
Address
Dout
Row
High-Z
20
HM514265D Series, HM51S4265D Series
CAS-Before-RAS Refresh Cycle
t
t
RC
RC
t
t
t
t
RAS
t
*
*
RP
RAS
RP
RP
RAS
t
T
t
t
t
RPC
CRP
RPC
t
t
t
t
t
t
CHR
CPN
CSR
CHR
CPN
CSR
UCAS
LCAS
Address
t
OFF1
High-Z
Dout
_
Do not extend t
> t
(max).
RAS
RAS
*
Untested self refresh mode may be
activated and loss of data may be
resulted (HM514265D/DL).
21
HM514265D Series, HM51S4265D Series
EDO Page Mode Read Cycle (tHPC minimum cycle operation)
t
RASC
t
t
RP
RHCP
RAS
t
T
t
t
t
t
CSH
HPC
RSH
t
CRP
t
t
t
t
t
RCD
CAS
CP
CAS
CP
CAS
UCAS
LCAS
t
CAL
t
ASR
t
t
t
CAL
t
CAL
CAH
t
t
RAL
t
CAH
RAD
t
t
t
RAH
CAH
t
ASC
ASC
ASC
Address
Row
Column 1
Column 2
Column 3
t
RCHA
t
RRH
t
RCHP
t
t
RCS
RCH
t
RCHC
WE
t
WEZ
t
DZC
t
CDD
High-Z
Din
t
CAC
t
t
CAC
OFR
t
t
CAC
AA
t
OH
t
t
t
t
AA
AA
t
ODD
t
t
t
ACP
ACP
OHR
RAC
DZO
t
OFF1
t
t
DOH
DOH
Dout 1
Dout
Dout 2
Dout 3
t
t
OAC
OFF2
OE
22
HM514265D Series, HM51S4265D Series
EDO Page Mode Read Cycle (High-Z control by WE and OE)
t
RP
t
t
HPC
t
RASC
RAS
t
t
t
CRP
HPC
t
HPC
t
RHCP
CP
t
t
T
CSH
t
CP
t
t
CP
t
UCAS
LCAS
t
CAS
CAS
CAS
CAS
t
RCHP
tRCS
tRCS
t
t
t
tRCH
RCHR
RRH
RCH
WE
t
RCHC
t
RCHC
t
RCHA
CAH
t
RAL
t
tASC
t
tASC tCAH
tASC tCAH
WDD
t
tCAH
RAH tASC
tASR
Address
Row
Column 1
Column 2
t
Column 3
t
Column 4
t
CAL
t
t
t
RDD
CDD
CAL
CAL
CAL
t
DZC
High-Z
Din
t
t
t
COP
COL
DZO
t
ODD
OE
t
t
OFR
ACP
t
ACP
t
OAC
t
t
t
ACP
AA
t
OHR
OFF2
AA
t
OFF2
t
AA
t
t
t
CAC
AA
RAC
t
CAC
t
OFF2
t
t
t
CAC
CAC
WEZ
t
t
t
OFF1
OH
tOAC
t
DOH
t
OAC
Dout
Dout 1
Dout 2
Dout 2
Dout 4
Dout 3
23
HM514265D Series, HM51S4265D Series
EDO Page Mode Early Write Cycle (tHPC minimum cycle operation)
t
t
RP
RASC
RAS
t
T
t
RSH
t
t
t
HPC
CSH
RCD
t
t
t
t
t
t
CRP
CAS
CAS
CP
CAS
CP
UCAS
LCAS
t
t
t
t
t
ASC
t
CAH
t
t
ASC
ASR
CAH
CAH
ASC
RAH
Address
Row
Column
Column
Column
t
t
t
t
t
WCS
WCH
WCS
WCH
WCH
t
WCS
WE
t
t
DH
DH
t
t
t
t
DS
DS
DS
DH
Din
Din
Din
Din
High-Z
Dout
24
HM514265D Series, HM51S4265D Series
EDO Page Mode Delayed Write Cycle
t
t
t
RASC
RP
RAS
t
T
t
t
t
RSH
CSH
t
HPC
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
UCAS
LCAS
t
t
ASC
ASR
t
CAH
t
ASC
t
t
CAH
RAH
t
ASC
t
CAH
Address
Row
Column
Column
Column
t
t
t
t
CWL
CWL
CWL
t
t
t
RCS
WP
WP
t
WP
RWL
WE
t
t
t
DH
RCS
DH
t
t
DH
RCS
t
DS
t
t
DS
DS
Din
Din
Din
Din
t
OEH
High-Z
Dout
t
ODD
OE
25
HM514265D Series, HM51S4265D Series
EDO Page Mode Read-Modify-Write Cycle
t
t
RP
RASC
RAS
t
t
RCD
HPCM
t
T
t
CRP
t
t
CP
CP
t
t
t
CAS
CAS
CAS
UCAS
LCAS
t
RAD
t
t
RAH
ACP
t
t
CAH
t
t
CAH
CAH
t
ASR
t
ASC
ASC
t
ASC
Column
Column
t
CPW
Row
Column
Address
t
t
CWL
RWL
WP
t
t
CWL
t
t
AWD
AWD
t
CWL
t
t
t
AWD
CWD
CWD
t
t
RCS
RCS
t
WP
t
t
RCS
CWD
t
t
CPW
RWD
t
WP
WE
t
t
ACP
DS
t
t
DS
DS
t
CAC
t
DZC
t
DZC
t
t
DH
t
DH
t
t
DZC
DH
CAC
High-Z
High-Z
AA
High-Z
Din
t
Din
Din
t
Din
t
AA
t
t
CAC
t
t
DZO
RAC
t
AA
t
OAC
t
t
t
OAC
OAC
OEH
OEH
OEH
Dout
Dout
OFF2
Dout
OFF2
Dout
t
t
t
OFF2
t
t
DZO
DZO
OE
t
t
ODD
t
ODD
ODD
t
OEP
t
OEP
t
OEP
26
HM514265D Series, HM51S4265D Series
EDO Page Mode Mix Cycle (1)*24
t
RP
t
RASC
RAS
t
t
CRP
CSH
t
T
t
t
t
CP
CP
CP
t
UCAS
LCAS
t
t
t
CAS
CAS
CAS
CAS
t
RCHP
t
t
t
tWCS tWCH
RRH
RCH
RCHC
t
t
CPW
AWD
tWP
WE
t
RCHA
RAL
tCAH
t
tASC
tRAH
tASC
t
tASC tCAH
Column 2
tCAH
CAH
tASC
tASR
Address
Row
Column 1
Column 3
Column 4
t
CAL
t
t
t
t
RDD
CAL
CAL
CAL
t
CDD
t
t
t
DH
DH
DS
t
DS
High-Z
Din
Din 1
Din 3
t
ODD
t
WDD
OE
t
DZO
t
t
OFR
WEZ
ACP
t
t
ACP
t
t
ACP
t
AA
AA
t
t
OFF2
t
OFF2
AA
t
t
OAC
CAC
OAC
t
t
CAC
CAC
t
t
t
OFF1
OH
t
DOH
Dout
Dout 2
Dout 4
Dout 3
27
HM514265D Series, HM51S4265D Series
EDO Page Mode Mix Cycle (2)*24
t
RP
t
RASC
RAS
t
CRP
t
t
T
t
CSH
t
CP
t
CP
CP
t
UCAS
LCAS
t
t
t
CAS
CAS
CAS
CAS
t
RCHP
t
t
t
t
tRCS
tWCS tWCH
t
RRH
RCH
RCHR
CWL
tRCH
RCHC
tWP
WE
t
RCHA
RAL
t
CPW
t
tASC
tRAH
t
CAH
tASC tCAH
tASC tCAH
Column 3
tCAH
tASC
tASR
Address
Row
Column 1
Column 2
t
Column 4
t
t
CAL
t
RDD
t
CAL
CAL
CAL
t
CDD
t
t
t
t
DS
DS
DH
DH
High-Z
Din
Din 2
Din 3
t
DZO
t
t
ODD
ODD
t
t
WDD
DZO
OE
t
t
t
t
OFR
WEZ
OAC
t
ACP
AA
t
ACP
t
t
OAC
AA
t
t
AA
t
t
OFF2
OFF2
CAC
t
t
CAC
OAC
OFF2
t
t
RAC
CAC
t
t
t
OFF1
OH
Dout
Dout 1
Dout 4
Dout 3
28
HM514265D Series, HM51S4265D Series
Self Refresh Cycle *30, 31, 32, 33
t
t
t
RASS
RP
RPS
RAS
t
T
t
t
t
CRP
RPC
CPN
t
CSR
t
CHS
UCAS
LCAS
Address
t
OFF1
High-Z
Dout
29
HM514265D Series, HM51S4265D Series
Package Dimension
HM514265DJ/DLJ Series
HM51S4265DJ/DLJ Series (CP-40D)
Unit: mm
25.80
26.16 Max
21
40
20
1
0.74
1.30 Max
9.40 ± 0.25
1.27
0.43 ± 0.10
0.41 ± 0.08
0.10
Hitachi Code
JEDEC Code
EIAJ Code
Weight
CP-40D
—
SC-640
1.73 g
30
HM514265D Series, HM51S4265D Series
HM514265DTT/DLTT Series
HM51S4265DTT/DLTT Series (TTP-44/40DB)
Unit: mm
18.41
18.81 Max
44
35 32
23
22
1
10 13
0.80
0.80
M
0.13
0.27 ± 0.07
0.25 ± 0.05
11.76 ± 0.20
0 – 5°
1.005 Max
0.50 ± 0.10
0.10
2.40
Hitachi Code
JEDEC Code
EIAJ Code
Weight
TTP-44/40DB
MO-133BA
SC-504-8C
0.43 g
31
HM514265D Series, HM51S4265D Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other
reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such
use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested
to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Tel: 415-589-8300
Fax: 535-1533
Fax: 415-583-4207
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Berkshire SL6 8YA
United Kingdom
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 0628-585000
Fax: 0628-778322
Tel: 27359218
Fax: 27306071
32
HM514265D Series, HM51S4265D Series
Revision Record
Rev. Date
Contents of Modification
Drawn by Approved by
0.0
1.0
May. 20, 1996
Nov. 28, 1996
Initial issue
H. Hisakawa S. Suzuki
Deletion of preliminary
AC Characteristics
Change of note 34
Addition of note 4 to Notes concerning 2CAS control
Timing Waveforms
Deletion of notes about undefined pins
33
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