HM51W17400LS-7 [HITACHI]
4,194,304-word x 4-bit Dynamic RAM; 4,194,304字×4位动态随机存储器
| 型号： | HM51W17400LS-7 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 4,194,304-word x 4-bit Dynamic RAM |
| 文件： | 总33页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM51W16400 Series
HM51W17400 Series
4,194,304-word × 4-bit Dynamic RAM
ADE-203-649C (Z)
Rev. 3.0
Feb. 27, 1997
Description
The Hitachi HM51W16400 Series, HM51W17400 Series are CMOS dynamic RAMs organized 4,194,304-
word × 4-bit. They employ the most advanced 0.5 µm CMOS technology for high performance and low
power. The HM51W16400 Series, HM51W17400 Series offer Fast Page Mode as a high speed access
mode. They have package variations of standard 300-mil 26-pin plastic SOJ and standard 300-mil 26-pin
plastic TSOP.
Features
•
•
•
Single 3.3 V (±0.3 V)
Access time: 50 ns/60 ns/70 ns (max)
Power dissipation
Active mode : 324 mW/288mW/252 mW (max) (HM51W16400 Series)
: 360 mW/324 mW/288 mW (max) (HM51W17400 Series)
Standby mode : 7.2 mW (max)
: 0.36 mW (max) (L-version)
•
•
Fast page mode capability
Long refresh period
4096 refresh cycles : 64 ms (HM51W16400 Series)
: 128 ms (L-version)
2048 refresh cycles : 32 ms (HM51W17400 Series)
: 128 ms (L-version)
HM51W16400 Series, HM51W17400 Series
•
4 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
Self refresh (L-version)
Battery backup operation (L-version)
Test function
•
•
16-bit parallel test mode
Ordering Information
Type No.
Access time
Package
HM51W16400S-5
HM51W16400S-6
HM51W16400S-7
50 ns
60 ns
70 ns
300-mil 26-pin plastic SOJ
(CP-26/24DB)
HM51W16400LS-5
HM51W16400LS-6
HM51W16400LS-7
50 ns
60 ns
70 ns
HM51W17400S-5
HM51W17400S-6
HM51W17400S-7
50 ns
60 ns
70 ns
HM51W17400LS-5
HM51W17400LS-6
HM51W17400LS-7
50 ns
60 ns
70 ns
HM51W16400TS-5
HM51W16400TS-6
HM51W16400TS-7
50 ns
60 ns
70 ns
300-mil 26-pin plastic TSOP II
(TTP-26/24DA)
HM51W16400LTS-5
HM51W16400LTS-6
HM51W16400LTS-7
50 ns
60 ns
70 ns
HM51W17400TS-5
HM51W17400TS-6
HM51W17400TS-7
50 ns
60 ns
70 ns
HM51W17400LTS-5
HM51W17400LTS-6
HM51W17400LTS-7
50 ns
60 ns
70 ns
2
HM51W16400 Series, HM51W17400 Series
Pin Arrangement
HM51W16400S/LS Series
HM51W16400TS/LTS Series
VCC
I/O1
I/O2
WE
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
CAS
OE
VCC
I/O1
I/O2
WE
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
CAS
OE
RAS
A11
RAS
A11
A9
A9
A10
A0
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
A10
A0
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
9
9
A1
10
11
12
13
A1
10
11
12
13
A2
A2
A3
A3
VCC
VCC
(Top view)
(Top view)
Pin Description
Pin name
Function
Address input
— Row/Refresh address A0 to A11
A0 to A11
— Column address
Data input/Data output
Row address strobe
Column address strobe
Read/Write enable
Output enable
A0 to A9
I/O1 to I/O4
RAS
CAS
WE
OE
VCC
Power supply
VSS
Ground
3
HM51W16400 Series, HM51W17400 Series
Pin Arrangement
HM51W17400S/LS Series
HM51W17400TS/LTS Series
VCC
I/O1
I/O2
WE
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
CAS
OE
VCC
I/O1
I/O2
WE
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
CAS
OE
RAS
NC
RAS
NC
A9
A9
A10
A0
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
A10
A0
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
9
9
A1
10
11
12
13
A1
10
11
12
13
A2
A2
A3
A3
VCC
VCC
(Top view)
(Top view)
Pin Description
Pin name
Function
Address input
— Row/Refresh address A0 to A10
A0 to A10
— Column address
Data input/Data output
Row address strobe
Column address strobe
Read/Write enable
Output enable
A0 to A10
I/O1 to I/O4
RAS
CAS
WE
OE
VCC
Power supply
VSS
Ground
NC
No connection
4
HM51W16400 Series, HM51W17400 Series
Block Diagram (HM51W16400 Series)
RAS
CAS
WE
OE
Timing and control
A0
A1
to
Column decoder
4M array
Column
address
buffers
•
•
•
A9
4M array
4M array
4M array
I/O1
to
I/O4
•
•
•
I/O buffers
Row
address
buffers
A10
A11
5
HM51W16400 Series, HM51W17400 Series
Block Diagram (HM51W17400 Series)
RAS
CAS
WE
OE
Timing and control
A0
A1
to
Column decoder
4M array
Column
address
buffers
•
•
•
A10
4M array
4M array
4M array
I/O1
to
I/O4
I/O buffers
•
•
•
Row
address
buffers
6
HM51W16400 Series, HM51W17400 Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–0.5 to VCC + 0.5 (≤ +4.6 V (max))
VCC
–0.5 to +4.6
50
V
Iout
PT
mA
W
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +70˚C)
Parameter
Symbol
VCC
Min
3.0
Typ
3.3
—
Max
Unit
V
Notes
Supply voltage
Input high voltage
Input low voltage
3.6
1, 2
1
VIH
2.0
VCC + 0.3
0.8
V
VIL
–0.3
—
V
1
Note: 1. All voltage referred to VSS.
7
HM51W16400 Series, HM51W17400 Series
DC Characteristics
(Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W16400 Series)
HM51W16400
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Test conditions
1
2
,
Operating current* *
Standby current
ICC1
ICC2
—
—
90
2
—
—
80
2
—
—
70 mA
tRC = min
2
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
—
1
—
1
—
1
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
100 —
100 — 100 µA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
90
5
—
—
80
5
—
—
70 mA
mA
tRC = min
5
RAS = VIH
CAS = VIL
Dout = enable
CAS-before-RAS refresh
ICC6
—
90
80
—
—
80
70
—
—
70 mA
60 mA
tRC = min
tPC = min
current
Fast page mode current*1, *3 ICC7
—
—
Battery backup current
(Standby with CBR refresh)
(L-version)
ICC10
300 —
300 — 300 µA
CMOS interface
Dout = High-Z, CBR
refresh: tRC = 31.3 µs
tRAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
200 —
200 — 200 µA
CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Input leakage current
Output leakage current
ILI
–10 10 –10 10 –10 10 µA
–10 10 –10 10 –10 10 µA
0 V ≤ Vin ≤ 4.6 V
ILO
0 V ≤ Vin ≤ 4.6 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4 VCC 2.4 VCC 2.4 VCC
0.4 0.4 0.4
V
V
High Iout = –2 mA
0
0
0
Low Iout = 2 mA
Notes : 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
8
HM51W16400 Series, HM51W17400 Series
DC Characteristics
(Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W17400 Series)
HM51W17400
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Test conditions
1
2
,
Operating current* *
Standby current
ICC1
ICC2
—
—
100 —
90
2
—
—
80 mA
tRC = min
2
—
2
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
—
1
—
1
—
1
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
100 —
100 —
100 — 100 µA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
90
5
—
—
80 mA
mA
tRC = min
5
—
5
RAS = VIH
CAS = VIL
Dout = enable
CAS-before-RAS refresh
ICC6
—
100 —
90
90
80
—
—
80 mA
70 mA
tRC = min
tPC = min
current
Fast page mode current*1, *3 ICC7
—
—
—
Battery backup current
(Standby with CBR refresh)
(L-version)
ICC10
300 —
300 — 300 µA
CMOS interface
Dout = High-Z, CBR
refresh: tRC = 62.5 µs
tRAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
200 —
200 — 200 µA
CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Input leakage current
Output leakage current
ILI
–10 10 –10 10 –10 10 µA
–10 10 –10 10 –10 10 µA
0 V ≤ Vin ≤ 4.6 V
ILO
0 V ≤ Vin ≤ 4.6 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4 VCC 2.4 VCC 2.4 VCC
0.4 0.4 0.4
V
V
High Iout = –2 mA
0
0
0
Low Iout = 2 mA
Notes : 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
9
HM51W16400 Series, HM51W17400 Series
Capacitance (Ta = 25˚C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (Data-in, Data-out)
5
7
7
1
CI2
—
pF
1
CI/O
—
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
10
HM51W16400 Series, HM51W17400 Series
AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *18, *19
Test Conditions
•
•
•
•
Input rise and fall time: 5 ns
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM51W16400/HM51W17400
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Notes
Random read or write cycle time
RAS precharge time
CAS precharge time
RAS pulse width
tRC
90
30
8
—
—
—
110
40
—
—
—
130
50
—
—
—
ns
ns
ns
tRP
tCP
10
10
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
50
13
0
10000 60
10000 15
10000 70
10000 18
10000 ns
10000 ns
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
—
—
—
—
37
25
—
—
—
—
—
—
50
0
—
—
—
—
45
30
—
—
—
—
—
—
50
0
—
—
—
—
52
35
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
10
0
10
0
0
8
10
20
15
15
60
5
15
20
15
18
70
5
18
13
13
50
5
3
4
RAS to column address delay time tRAD
RAS hold time
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
CAS hold time
CAS to RAS precharge time
OE to Din delay time
OE delay time from Din
CAS delay time from Din
Transition time (rise and fall)
13
0
15
0
18
0
5
6
6
7
0
0
0
3
3
3
11
HM51W16400 Series, HM51W17400 Series
Read Cycle
HM51W16400/HM51W17400
-5 -6 -7
Symbol Min Max Min Max Min
Parameter
Max Unit
Notes
Access time from RAS
Access time from CAS
tRAC
tCAC
—
—
50
13
—
—
60
15
—
—
70
18
ns
ns
8, 9, 20
9, 10, 17,
20
Access time from address
tAA
—
25
—
30
—
35
ns
9, 11, 17,
20
Access time from OE
tOEA
tRCS
tRCH
tRRH
—
0
13
—
—
—
—
—
—
—
—
13
13
—
—
0
15
—
—
—
—
—
—
—
—
15
15
—
—
0
18
—
—
—
—
—
—
—
—
15
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9, 20
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
0
0
0
12
12
0
0
0
Column address to RAS lead time tRAL
Column address to CAS lead time tCAL
25
25
0
30
30
0
35
35
0
CAS to output in low-Z
tCLZ
tOH
Output data hold time
3
3
3
Output data hold time from OE
Output buffer turn-off time
Output buffer turn-off to OE
CAS to Din delay time
tOHO
tOFF
tOEZ
tCDD
3
3
3
—
—
13
—
—
15
—
—
18
13
13
5
Write Cycle
HM51W16400/HM51W17400
-5
Symbol Min
-6
-7
Parameter
Max Min
Max Min
Max Unit
Notes
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
tWCS
tWCH
tWP
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
14
8
10
10
15
15
0
15
10
18
18
0
8
tRWL
tCWL
tDS
13
13
0
15
15
Data-in hold time
tDH
8
10
15
12
HM51W16400 Series, HM51W17400 Series
Read-Modify-Write Cycle
HM51W16400/HM51W17400
-5
-6
-7
Parameter
Symbol Min
Max Min
Max Min
Max Unit
Notes
Read-modify-write cycle time
RAS to WE delay time
CAS to WE delay time
tRWC
tRWD
tCWD
131
73
36
48
13
—
—
—
—
—
155
85
40
55
15
—
—
—
—
—
181
98
46
63
18
—
—
—
—
—
ns
ns
ns
ns
ns
14
14
14
Column address to WE delay time tAWD
OE hold time from WE
tOEH
Refresh Cycle
HM51W16400/HM51W17400
-5
Symbol Min
-6
-7
Parameter
Max Min
Max Min
Max Unit
Notes
CAS setup time (CBR refresh cycle) tCSR
CAS hold time (CBR refresh cycle) tCHR
WE setup time (CBR refresh cycle) tWRP
5
8
0
8
5
—
—
—
—
—
5
—
—
—
—
—
5
—
—
—
—
—
ns
ns
ns
ns
ns
10
0
10
0
WE hold time (CBR refresh cycle)
RAS precharge to CAS hold time
tWRH
tRPC
10
5
10
5
Fast Page Mode Cycle
HM51W16400/HM51W17400
-5
Symbol Min Max
-6
-7
Min Max
45
100000 —
Parameter
Min Max
Unit
Notes
Fast page mode cycle time
Fast page mode RAS pulse width
Access time from CAS precharge
tPC
35
—
—
30
—
40
100000 —
—
—
ns
tRASP
tCPA
100000 ns
16
30
—
—
35
—
—
40
—
ns
ns
9, 17, 20
RAS hold time from CAS precharge tCPRH
35
40
13
HM51W16400 Series, HM51W17400 Series
Fast Page Mode Read-Modify-Write Cycle
HM51W16400/HM51W17400
-5 -6 -7
Symbol Min Max Min Max Min
Parameter
Max Unit
Notes
Fast page mode read-modify-write tPRWC
cycle time
76
—
85
—
96
—
ns
WE delay time from CAS precharge tCPW
53
—
60
—
68
—
ns
14
Test Mode Cycle *19
HM51W16400/HM51W17400
-5
Symbol Min
-6
-7
Parameter
Max Min
Max Min
Max Unit
Notes
Test mode WE setup time
Test mode WE hold time
tWTS
tWTH
0
8
—
—
0
—
—
0
—
—
ns
ns
10
10
Refresh (HM51W16400 Series)
Parameter
Symbol
tREF
Max
Unit
ms
Notes
Refresh
64
4096 cycles
4096 cycles
Refresh (L-version)
tREF
128
ms
Refresh (HM51W17400 Series)
Parameter
Symbol
tREF
Max
32
Unit
ms
Notes
Refresh period
2048 cycles
2048 cycles
Refresh period (L-version)
tREF
128
ms
14
HM51W16400 Series, HM51W17400 Series
Self Refresh Mode (L-version)
HM51W16400L/HM51W17400L
-5
-6
-7
Parameter
Symbol Min
Max Min
Max Min
Max Unit Notes
RAS pulse width (self refresh)
tRASS
100
—
100
—
100
—
µs
21, 22, 23,
24
RAS precharge time (self refresh)
CAS hold time (self refresh)
tRPS
tCHS
90
—
—
110
–50
—
—
130
–50
—
—
ns
ns
–50
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If
the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are
required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. (VOH = 2.0 V, VOL = 0.8 V)
10. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW
≥
tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at
access time) is indeterminate.
15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge
in delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in Fast page mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA
.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to the device.
15
HM51W16400 Series, HM51W17400 Series
19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M
× 4 are don’t care during test mode. Test mode is set by performing a WE-and-CAS-before-RAS
(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1
to I/O4) and read out from each I/O.
If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read
cycle, then the device has passed. If they are not equal, data output pin is a low state, then the
device has failed.
Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh
cycles.
To get out of test mode and enter a normal operation mode, perform either a regular CAS-before-
RAS refresh cycle or RAS-only refresh cycle.
20. In a test mode read cycle, the value of tRAC, tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
21. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in
transition state from normal operation mode to self refresh mode. If tRASS > 100 µs, then RAS
precharge time should use tRPS instead of tRP.
22. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed with in 15.6 µs immediately after exiting from and before entering into
self refresh mode.
23. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 2048
cycles (4096 cycles: HM51W16400 Series, 2048 cycles: HM51W 17400 Series) of distributed
CBR refresh with 15.6 µs interval should be executed with in 64 or 32 ms (64 ms: HM51W16400
Series, 32 ms: HM51W17400 Series) immediately after exiting from and before entering into the
self refresh mode.
24. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
25. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
16
HM51W16400 Series, HM51W17400 Series
Timing Waveforms*25
Read Cycle
t
t
RC
t
RAS
RP
RAS
t
t
CSH
CRP
t
t
t
RCD
RSH
CAS
t
T
CAS
t
t
t
RAD
RAL
CAL
t
tASC
t
CAH
ASR
tRAH
Column
Address
Row
t
RRH
t
RCH
t
RCS
WE
t
t
CDD
DZC
High-Z
Din
t
t
t
OED
DZO
OEA
OE
t
OEZ
t
t
CAC
OHO
t
AA
t
OFF
t
RAC
t
t
OH
CLZ
Dout
Dout
17
HM51W16400 Series, HM51W17400 Series
Early Write Cycle
t
t
RC
t
RAS
RP
RAS
CAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
WCH
WCS
WE
t
t
DH
DS
Din
Din
High-Z*
Dout
t
t
(min)
WCS
WCS
*
18
HM51W16400 Series, HM51W17400 Series
Delayed Write Cycle *18
t
t
RC
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
CAS
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
t
CWL
RWL
WP
t
RCS
WE
Din
t
t
t
DH
DZC
DS
High-Z
Din
t
t
OEH
DZO
t
OED
OE
t
OEZ
t
CLZ
High-Z
Dout
Invalid Dout
19
HM51W16400 Series, HM51W17400 Series
Read-Modify-Write Cycle*18
t
t
RWC
RAS
t
RP
RAS
CAS
t
T
t
t
t
CRP
RCD
CAS
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
Address
Row
Column
t
t
t
t
CWD
CWL
RWL
t
RCS
t
AWD
RWD
t
WP
WE
Din
OE
t
t
DH
DZC
t
DS
High-Z
Din
t
OED
t
OEH
t
DZO
t
OEA
t
CAC
t
t
OEZ
t
t
AA
t
RAC
OHO
High-Z
Dout
Dout
CLZ
20
HM51W16400 Series, HM51W17400 Series
RAS-Only Refresh Cycle
t
RC
t
t
RAS
RP
RAS
t
T
t
t
t
CRP
CRP
RPC
CAS
t
t
RAH
ASR
Address
Row
t
OFF
High-Z
Dout
21
HM51W16400 Series, HM51W17400 Series
CAS-Before-RAS Refresh Cycle
t
RC
t
t
t
RP
RP
RAS
RAS
CAS
t
t
t
t
CRP
t
CSR
CHR
RPC
RPC
t
T
t
CP
t
t
t
WRH
CP
WRP
WE
Address
t
OFF
High-Z
Dout
22
HM51W16400 Series, HM51W17400 Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RAS
RP
RAS
RP
RAS
RAS
t
T
t
t
t
CRP
RSH
CHR
t
RCD
CAS
Address
WE
t
t
RAL
RAD
t
t
t
t
CAH
ASR RAH
Row
ASC
Column
t
WRP
t
WRP
t
t
RRH
WRH
t
WRH
t
RCS
t
t
CDD
DZC
High-Z
Din
t
t
OED
DZO
t
OEA
OE
t
t
t
CAC
OEZ
t
AA
OHO
t
t
t
RAC
OFF
OH
t
CLZ
Dout
Dout
23
HM51W16400 Series, HM51W17400 Series
Fast Page Mode Read Cycle
t
RASP
t
t
RP
CPRH
RAS
CAS
t
T
t
t
t
t
CSH
PC
RSH
t
CRP
t
t
t
t
t
RCD
CAS
CP
CAS
CAL
CP
CAS
t
t
RAL
CAL
t
t
t
RAD
CAL
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
Address
Row
Column 1
Column 2
Column N
t
t
t
t
RCS
RCS
RRH
RCH
t
t
t
t
t
t
RCS
DZC
RCH
CDD
RCH
CDD
WE
Din
OE
t
t
DZC
DZC
t
CDD
High-Z
High-Z
High-Z
t
t
t
t
t
t
OED
DZO
OED
DZO OED
DZO
t
t
t
CPA
RAC
CPA
t
t
t
t
t
t
OH
AA
OH
AA
OH
AA
t
OHO
t
t
OHO
OHO
t
t
t
OEA
OEA
OEA
t
t
CAC
t
t
t
t
t
CAC
CAC
CLZ
OFF
OFF
OEZ
OFF
OEZ
t
t
t
t
CLZ
t
OEZ
CLZ
Dout 1
Dout 2
Dout N
Dout
24
HM51W16400 Series, HM51W17400 Series
Fast Page Mode Early Write Cycle
t
t
RASP
RP
RAS
t
T
t
t
t
RSH
CSH
PC
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
CAS
Address
WE
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
ROW
Column 1
Column 2
Column N
t
t
t
t
t
t
WCH
WCS
WCH
WCS
WCH
WCS
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
Din 1
Din 2
Din N
Din
High-Z*
Dout
t
t
(min)
WCS
*
WCS
25
HM51W16400 Series, HM51W17400 Series
Fast Page Mode Delayed Write Cycle *18
t
RASP
t
RP
RAS
t
t
t
t
CP
CRP
T
CP
t
t
t
t
CSH
PC
RSH
CAS
t
t
t
CAS
RCD
CAS
CAS
t
t
RAD
t
t
t
ASR
ASC
t
ASC
t
ASC
t
t
RAH
CAH
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
CWL
CWL
t
CWL
t
RWL
t
t
RCS
RCS
RCS
WE
t
t
t
WP
WP
WP
t
t
t
t
t
t
t
DZC DS
DZC DS
DZC DS
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
DZO
DZO
DZO
OED
t
t
OED
OED
t
t
t
OEH
OEH
OEH
OE
t
t
t
CLZ
CLZ
CLZ
t
t
t
OEZ
OEZ
OEZ
High-Z
Dout
Invalid Dout
Invalid Dout
Invalid Dout
26
HM51W16400 Series, HM51W17400 Series
Fast Page Mode Read-Modify-Write Cycle*18
t
RASP
t
RP
RAS
t
t
T
PRWC
t
t
t
t
RSH
CAS
t
CRP
CP
CP
t
t
t
CAS
RCD
CAS
CAS
t
t
RAD
t
t
t
ASC
t
CAH
ASR
ASC
RAH
ASC
t
t
t
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
t
t
t
CWL
RWD
AWD
CWL
CPW
AWD
CWL
CPW
AWD
t
RWL
t
t
t
t
t
CWD
CWD
RCS
CWD
RCS
WE
t
t
t
t
t
WP
t
DS
RCS
DZO
WP
DS
WP
t
t
t
DS
t
DZC
DZC
DZC
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
OE
t
t
t
OED
OED
OED
t
t
t
DZO
DZO
t
t
t
OEH
OEH
OEH
t
t
t
OHO
OHO
OHO
t
t
t
t
t
t
OEA
CAC
OEA
CAC
OEA
CAC
t
t
t
AA
AA
AA
t
t
CPA
CPA
t
t
RAC
t
t
t
OEZ
t
t
OEZ
OEZ
CLZ
CLZ
CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
27
HM51W16400 Series, HM51W17400 Series
Test Mode Cycle *19
*,**
Reset Cycle
Set Cycle**
Test Mode Cycle
Normal Mode
RAS
CAS
WE
*
CBR or RAS-only refresh
** Address, Din, OE: H or L
Test Mode Set Cycle
t
RC
t
t
t
RP
RP
RAS
RAS
CAS
t
t
t
t
t
CRP
RPC
CSR
CHR
RPC
t
T
t
t
t
t
CP
CP
WTS
WTH
WE
Address
Dout
t
OFF
High-Z
28
HM51W16400 Series, HM51W17400 Series
Self Refresh Cycle (L-version)*21,*22,*23,*24
t
t
t
RASS
RP
RPS
RAS
t
T
t
RPC
t
CRP
t
t
CSR
CP
t
CHS
CAS
WE
t
t
WRH
WRP
t
OFF
High-Z
Dout
29
HM51W16400 Series, HM51W17400 Series
Package Dimensions
HM51W16400S/LS Series
HM51W17400S/LS Series (CP-26/24DB)
Unit: mm
16.90
17.27 Max
26
1
21 19
14
13
6
8
0.74
1.30 Max
1.27
0.10
6.71 ± 0.25
0.43 ± 0.10
0.41 ± 0.08
2.54
Hitachi Code
CP-26/24DB
MO-077-AA
SC-632-A
0.8 g
JEDEC Code
EIAJ Code
Weight
30
HM51W16400 Series, HM51W17400 Series
HM51W16400TS/LTS Series
HM51W17400TS/LTS Series (TTP-26/24DA)
Unit: mm
17.14
17.54 Max
26
1
21 19
14
13
6
8
1.27
0.80
0.21 M
0.42 ± 0.08
0.40 ± 0.06
9.22 ± 0.20
1.15 Max
2.54
0.10
0 – 5°
0.50 ± 0.10
Hitachi Code
TTP-26/24DA
JEDEC Code
EIAJ Code
Weight
MO-132AB
—
0.30 g
31
HM51W16400 Series, HM51W17400 Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
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16 Collyer Quay #20-00
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Singapore 0104
Tel: 535-2100
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Tel: 089-9 91 80-0
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Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 0628-585000
Fax: 0628-778322
Tel: 27359218
Fax: 27306071
32
HM51W16400 Series, HM51W17400 Series
Revision Record
Rev. Date
Contents of Modification
Initial issue
Drawn by
Approved by
1.0
2.0
Oct. 14, 1996
Nov. 14, 1996
Y. Kasama M. Mishima
Y. Kasama Y. Matsuno
Addition of HM51W16400-5 Series
Addition of HM51W17400-5 Series
Power dissipation (active)
396/360 mW(max) to 360/324/288 mW (max)
(HM51W17400 Series)
DC Characteristics (HM51W17400 Series)
ICC1 max: 110/100 mA to 100/90/80 mA
ICC3 max: 110/100 mA to 100/90/80 mA
ICC6 max: 110/100 mA to 100/90/80 mA
3.0
Feb. 27, 1997
AC Characteristics
tRRH min: 5/5/5 ns to 0/0/0 ns
33
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