HM51W17800BJ-7 [HITACHI]
Fast Page DRAM, 2MX8, 70ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, SOJ-28;
| 型号： | HM51W17800BJ-7 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Fast Page DRAM, 2MX8, 70ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, SOJ-28 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总28页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM51W17800B Series
2,097,152-word × 8-bit Dynamic Random Access Memory
ADE-203-275C (Z)
Rev. 3.0
Jul. 5, 1996
Description
The Hitachi HM51W17800B is a CMOS dynamic RAM organized 2,097,152-word × 8-bit. It employs
the most advanced CMOS technology for high performance and low power. The HM51W17800B offers
Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM51W17800B to
be packaged in standard 28-pin plastic SOJ and 28-pin TSOP.
Features
•
•
Single 3.3 V (±0.3 V)
High speed
Access time: 60 ns/70 ns/80 ns (max)
Low power dissipation
•
Active mode: 432 mW/396 mW/360 mW(max)
Standby mode : 7.2 mW (max)
: 0.54 mW (max) (L-version)
Fast page mode capability
Long refresh period
•
•
2048 refresh cycles : 32 ms
: 128 ms (L-version)
•
•
4 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
Self refresh (L-version)
Battery backup operation (L-version)
This specification is fully compatible with the 16-Mbit DRAM specifications from TEXAS
INSTRUMENTS.
HM51W17800B Series
Ordering Information
Type No.
Access time
Package
HM51W17800BJ-6
HM51W17800BJ-7
HM51W17800BJ-8
60 ns
70 ns
80 ns
400-mil 28-pin plastic SOJ (CP-28DA)
HM51W17800BLJ-6
HM51W17800BLJ-7
HM51W17800BLJ-8
60 ns
70 ns
80 ns
HM51W17800BS-6*1
HM51W17800BS-7*1
HM51W17800BS-8*1
HM51W17800BLS-6*1
HM51W17800BLS-7*1
HM51W17800BLS-8*1
60 ns
70 ns
80 ns
300-mil 28-pin plastic SOJ (CP-28DNA)
400-mil 28-pin plastic TSOP II (TTP-28DA)
300-mil 28-pin plastic TSOP II (TTP-28DB)
60 ns
70 ns
80 ns
HM51W17800BTT-6
HM51W17800BTT-7
HM51W17800BTT-8
60 ns
70 ns
80 ns
HM51W17800BLTT-6
HM51W17800BLTT-7
HM51W17800BLTT-8
HM51W17800BTS-6*1
HM51W17800BTS-7*1
HM51W17800BTS-8*1
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
HM51W17800BLTS-6*1
HM51W17800BLTS-7*1
HM51W17800BLTS-8*1
60 ns
70 ns
80 ns
Note: 1. Under development
2
HM51W17800B Series
Pin Arrangement
HM51W17800BJ/BLJ Series
HM51W17800BS/BLS Series
HM51W17800BTT/BLTT Series
HM51W17800BTS/BLTS Series
VSS
I/O7
I/O6
I/O5
I/O4
CAS
OE
A9
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
I/O0
I/O1
I/O2
I/O3
WE
RAS
NC
VCC
I/O0
I/O1
I/O2
I/O3
WE
RAS
NC
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
I/O7
I/O6
I/O5
I/O4
CAS
OE
A9
3
3
4
4
5
5
6
6
7
7
8
8
A10
A0
9
A8
A8
9
A10
A0
10
11
12
13
14
A7
A7
10
11
12
13
14
A1
A6
A6
A1
A2
A5
A5
A2
A3
A4
A4
A3
VCC
VSS
VSS
VCC
(Top view)
(Top view)
Pin Description
Pin name
Function
Address input
Row/Refresh address A0 to A10
A0 to A10
Column address
Data input/data output
Row address strobe
Column address strobe
Read/Write enable
Output enable
A0 to A9
I/O0 to I/O7
RAS
CAS
WE
OE
VCC
Power supply
VSS
Ground
NC
No connection
3
HM51W17800B Series
Block Diagram
CAS
WE
OE
RAS
RAS
CAS
WE
OE
control
circuit
control
circuit
control
circuit
control
circuit
Sense amp. & I/O bus
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
I/O5 buffer
I/O4 buffer
I/O7
I/O6
I/O7 buffer
I/O6 buffer
I/O5
I/O4
Sense amp. & I/O bus
Sense amp. & I/O bus
Column decoder & driver
Column decoder & driver
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
I/O3
I/O2
I/O3 buffer
I/O2 buffer
I/O1 buffer
I/O0 buffer
I/O1
I/O0
Sense amp. & I/O bus
Sense amp. & I/O bus
Column address buffer
A0 to A9
Row address buffer
A0 to A10
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
4
HM51W17800B Series
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
VT
–0.5 to + 4.6
–0.5 to + 4.6
50
V
VCC
Iout
PT
V
mA
W
°C
°C
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
3.0
Typ
3.3
—
Max
Unit
V
Notes
Supply voltage
3.6
1, 2
1
Input high voltage
Input low voltage
VIH
2.0
VCC + 0.3
0.8
V
VIL
–0.3
—
V
1
Notes: 1. All voltage referred to VSS
5
HM51W17800B Series
DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HM51W17800B
-6
-7
-8
Parameter
Symbol Min Max Min Max Min Max Unit Test conditions
Operating current*1, *2
ICC1
ICC2
—
—
120
2
—
—
110 —
100 mA tRC = min
Standby current
2
—
2
mA TTL interface
RAS, CAS = VIH
Dout = High-Z
—
—
1
—
—
1
—
1
mA CMOS interface
RAS, CAS ≥ VCC – 0.2V
Dout = High-Z
Standby current (L-version)
ICC2
150
150 —
110 —
150 µA CMOS interface
RAS, CAS ≥ VCC – 0.2V
Dout = High-Z
RAS-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
120
5
—
—
100 mA tRC = min
5
—
5
mA RAS = VIH
CAS = VIL
Dout = enable
CAS-before-RAS refresh current ICC6
—
—
—
120
100
400
—
—
—
110 —
90 —
100 mA tRC = min
85 mA tPC = min
Fast page mode current*1, *3
ICC7
Battery backup current*4
(Standby with CBR refresh)
(L-version)
ICC10
400 —
400 µA CMOS interface
Dout = High-Z
CBR refresh: tRC = 62.5 µs
RAS ≤ 0.3 µs
t
Self refresh mode current
(L-version)
ICC11
—
250
—
250 —
250 µA CMOS interface
RAS, CAS ≤ 0.2V
Dout = High-Z
Input leakage current
Output leakage current
ILI
–10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 4.6 V
ILO
–10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 4.6 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4 VCC 2.4 VCC 2.4 VCC
0.4 0.4 0.4
V
V
High Iout = –2 mA
Low Iout = 2 mA
0
0
0
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4. CAS = L (≤ 0.2 V) while RAS = L (≤ 0.2 V).
6
HM51W17800B Series
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (Data-in, Data-out)
5
7
7
1
CI2
—
pF
1
CI/O
—
pF
1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)*1, *2, *18
Test Conditions
•
•
•
•
Input rise and fall time: 5 ns
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM51W17800B
-6
-7
-8
Parameter
Symbol Min
Max Min
Max Min
Max
—
Unit Notes
Random read or write cycle time
RAS precharge time
tRC
110
40
10
60
15
0
—
—
—
130
50
—
—
—
150
60
ns
ns
ns
tRP
—
CAS precharge time
tCP
10
10
—
RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
10000 70
10000 18
10000 80
10000 20
10000 ns
10000 ns
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
—
—
—
—
45
30
—
—
—
—
—
—
50
0
—
—
—
—
52
35
—
—
—
—
—
—
50
0
—
—
—
—
60
40
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
0
10
0
10
0
10
20
15
15
60
5
15
20
15
18
70
5
15
20
15
20
80
5
3
4
CAS hold time
CAS to RAS precharge time
OE to Din delay time
OE delay time from Din
CAS delay time from Din
Transition time (rise and fall)
15
0
18
0
20
0
5
6
6
7
0
0
0
3
3
3
7
HM51W17800B Series
Read Cycle
HM51W17800B
-6
-7
Max Min
-8
Parameter
Symbol Min
Max Min
Max
80
Unit Notes
Access time from RAS
Access time from CAS
tRAC
tCAC
—
—
60
15
—
—
70
18
—
—
ns
ns
8, 9
20
9, 10,
17
Access time from address
tAA
—
30
—
35
—
40
ns
9, 11,
17
Access time from OE
tOEA
tRCS
tRCH
tRRH
tRAL
tCAL
tCLZ
tOH
—
0
15
—
—
—
—
—
—
—
—
15
15
—
—
0
18
—
—
—
—
—
—
—
—
15
15
—
—
0
20
—
—
—
—
—
—
—
—
15
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Column address to RAS lead time
Column address to CAS lead time
CAS to output in low-Z
0
0
0
12
12
0
0
0
30
30
0
35
35
0
40
40
0
Output data hold time
3
3
3
Output data hold time from OE
Output buffer turn-off time
Output buffer turn-off to OE
CAS to Din delay time
tOHO
tOFF
tOEZ
tCDD
3
3
3
—
—
15
—
—
18
—
—
20
13
13
5
Write Cycle
HM51W17800B
-6 -7
Symbol Min Max Min
-8
Parameter
Max Min
Max
—
Unit Notes
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
tWCS
tWCH
tWP
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
0
ns
ns
ns
ns
ns
ns
ns
14
10
10
15
15
0
15
10
18
18
0
15
10
20
20
0
—
—
tRWL
tCWL
tDS
—
—
—
15
15
Data-in hold time
tDH
10
15
15
—
8
HM51W17800B Series
Read-Modify-Write Cycle
HM51W17800B
-6
-7
Max Min
-8
Parameter
Symbol Min
Max Min
Max
—
Unit Notes
Read-modify-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
OE hold time from WE
tRWC
tRWD
tCWD
tAWD
tOEH
155
85
40
55
15
—
—
—
—
—
181
98
46
63
18
—
—
—
—
—
205
110
50
ns
—
ns
ns
ns
ns
14
14
14
—
70
—
20
—
Refresh Cycle
HM51W17800B
-6 -7
Symbol Min Max Min
-8
Parameter
Max Min
Max
—
Unit Notes
CAS setup time (CBR refresh cycle)
CAS hold time (CBR refresh cycle)
WE setup time (CBR refresh cycle)
WE hold time (CBR refresh cycle)
RAS precharge to CAS hold time
tCSR
tCHR
tWRP
tWRH
tRPC
5
—
—
—
—
—
5
—
—
—
—
—
5
ns
ns
ns
ns
ns
10
0
10
0
10
0
—
—
10
0
10
0
10
0
—
—
Fast Page Mode Cycle
HM51W17800B
-6
-7
-8
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit Notes
Fast page mode cycle time
tPC
40
—
—
35
—
45
—
50
—
ns
Fast page mode RAS pulse width tRASP
Access time from CAS precharge tCPA
100000 —
100000 —
100000 ns
16
35
—
—
40
—
—
45
—
ns
ns
9, 17
RAS hold time from CAS precharge tCPRH
40
45
Fast Page Mode Read-Modify-Write Cycle
HM51W17800B
-6 -7
Symbol Min Max Min
-8
Max Min
Parameter
Max
Unit Notes
Fast page mode read- modify-write
cycle time
tPRWC
85
—
96
—
105
—
ns
WE delay time from CAS precharge
tCPW
60
—
68
—
75
—
ns
14
9
HM51W17800B Series
Refresh
Parameter
Symbol
tREF
Max
32
Unit
ms
Note
Refresh period
2048 cycles
2048 cycles
Refresh period (L-version)
tREF
128
ms
10
HM51W17800B Series
Self Refresh Mode (L-version)
HM51W17800BL
-6
-7
-8
Parameter
Symbol Min
Max Min
Max Min
Max
—
Unit Notes
RAS pulse width (self refresh)
RAS precharge time (self refresh)
CAS hold time (self refresh)
tRASS
tRPS
tCHS
100
110
–50
—
—
—
100
130
–50
—
—
—
100
150
–50
µs
ns
ns
—
—
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight
initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS
refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh
cycles are required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as
a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as
a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. (VOH = 2.0 V, VOL = 0.8 V)
10. Assumes that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max).
11. Assumes that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if
t
RWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and
tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output will contain data read from
the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data
out (at access time) is indeterminate.
15. These parameters are referred to CAS leading edge in early write cycles and to WE leading
edge in delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in Fast page mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA
.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
19. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in
transition state from normal operation mode to self refresh mode. If tRASS ≥ 100 µs, then RAS
precharge time should use tRPS instaed of tRP.
20. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycles, 2048
cycles of distributed CBR refresh with 15.6 Ms interval should be executed within 32 ms
immediately after exiting from and before entering into the self refresh mode.
11
HM51W17800B Series
21. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed within 15.6 µs immediately after exiting from and before entering
into self refresh mode.
22. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self refresh mode, all memory cells need to be refreshed before re-entering the self refresh
mode again.
23.
H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ V ≤ VIL (max))
IN
Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
12
HM51W17800B Series
Timing Waveforms*23
Read Cycle
t
t
RC
t
RAS
RP
RAS
t
t
CSH
CRP
t
t
t
RCD
RSH
CAS
t
T
CAS
t
t
t
RAD
RAL
CAL
t
t
t
CAH
ASR
ASC
t
RAH
Column
Address
Row
t
RRH
t
RCH
t
RCS
WE
t
t
CDD
DZC
High-Z
Din
t
t
t
OED
DZO
OEA
OE
t
OEZ
t
t
CAC
OHO
t
AA
t
OFF
t
RAC
t
t
OH
CLZ
Dout
Dout
Early Write Cycle
13
HM51W17800B Series
t
t
RC
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
CAS
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
WCH
WCS
WE
t
t
DH
DS
Din
Din
High-Z*
Dout
t
t
(min)
WCS
WCS
*
14
HM51W17800B Series
Delayed Write Cycle*18
t
t
RC
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
CAS
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
t
CWL
RWL
WP
t
RCS
WE
t
t
t
DH
DZC
DS
High-Z
Din
Din
t
t
OEH
DZO
t
OED
OE
t
OEZ
t
CLZ
High-Z
Dout
Invalid Dout
Read-Modify-Write Cycle*18
15
HM51W17800B Series
t
t
RWC
RAS
t
RP
RAS
t
T
t
t
t
CRP
RCD
CAS
CAS
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
Address
Row
Column
t
t
t
t
t
CWD
CWL
t
RCS
AWD
RWD
RWL
t
WP
WE
Din
OE
t
t
DH
DZC
t
DS
High-Z
Din
t
OED
t
OEH
t
DZO
t
OEA
t
CAC
t
t
OEZ
t
t
AA
t
RAC
OHO
High-Z
Dout
Dout
CLZ
16
HM51W17800B Series
RAS
-Only Refresh Cycle
t
RC
t
t
RP
RAS
RAS
t
T
t
t
t
CRP
CRP
RPC
CAS
t
t
ASR
RAH
Row
Address
Dout
t
OFF
High-Z
17
HM51W17800B Series
CAS
RAS
-Before- Refresh Cycle
t
t
RC
RC
t
t
t
t
t
RP
RP
RAS
RP
RAS
RAS
t
T
t
t
t
t
t
CRP
RPC
CP
RPC
CP
t
t
t
t
CHR
CSR
CHR
CSR
CAS
WE
t
t
t
t
WRH
WRP
WRH
WRP
Address
Dout
t
OFF
High-Z
18
HM51W17800B Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RAS
RP
RAS
RP
RAS
RAS
t
T
t
t
t
CRP
RSH
CHR
t
RCD
CAS
Address
WE
t
t
RAL
RAD
t
t
t
t
CAH
ASR RAH
Row
ASC
Column
t
WRP
t
WRP
t
t
RRH
WRH
t
WRH
t
RCS
t
t
CDD
DZC
High-Z
Din
t
t
OED
DZO
t
OEA
OE
t
t
t
CAC
OEZ
t
AA
OHO
t
t
t
RAC
OFF
OH
t
CLZ
Dout
Dout
19
HM51W17800B Series
Fast Page Mode Read Cycle
t
RASP
t
t
RP
CPRH
RAS
t
T
t
t
t
t
CSH
PC
RSH
t
CRP
t
t
t
t
t
RCD
CAS
CP
CAS
CAL
CP
CAS
CAS
t
t
RAL
CAL
t
t
t
RAD
CAL
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
Address
Row
Column 1
Column 2
Column N
t
t
t
t
RCS
RCS
RRH
RCH
t
t
t
t
t
t
RCS
DZC
RCH
CDD
RCH
CDD
WE
Din
OE
t
t
DZC
DZC
t
CDD
High-Z
High-Z
High-Z
t
t
t
t
t
t
OED
DZO
OED
DZO OED
DZO
t
t
t
CPA
RAC
CPA
t
t
t
t
t
t
OH
AA
OH
AA
OH
AA
t
OHO
t
t
OHO
OHO
t
t
t
OEA
OEA
OEA
t
t
CAC
t
t
t
t
t
CAC
CAC
CLZ
OFF
OFF
OEZ
OFF
OEZ
t
t
t
t
CLZ
t
OEZ
CLZ
Dout 1
Dout 2
Dout N
Dout
Fast Page Mode Early Write Cycle
20
HM51W17800B Series
t
t
RP
RASP
RAS
CAS
t
T
t
t
t
RSH
CSH
PC
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
WCH
WCS
WCH
WCS
WCH
WCS
WE
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
Din 1
Din 2
Din N
Din
High-Z*
Dout
t
t
(min)
*
WCS
WCS
21
HM51W17800B Series
Fast Page Mode Delayed Write Cycle*18
t
RASP
t
RP
RAS
t
t
t
t
CP
CRP
T
CP
t
t
t
t
CSH
PC
RSH
CAS
t
t
t
CAS
RCD
CAS
CAS
t
t
RAD
t
t
t
ASR
ASC
t
ASC
t
ASC
t
t
RAH
CAH
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
CWL
CWL
t
CWL
t
RWL
t
t
RCS
RCS
RCS
WE
t
t
t
WP
WP
WP
t
t
t
t
t
t
t
DZC DS
DZC DS
DZC DS
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
DZO
DZO
DZO
OED
t
t
OED
OED
t
t
t
OEH
OEH
OEH
OE
t
t
t
CLZ
CLZ
CLZ
t
t
t
OEZ
OEZ
OEZ
High-Z*
Dout
Invalid Dout
Invalid Dout
Invalid Dout
22
HM51W17800B Series
Fast Page Mode Read-Modify-Write Cycle*18
t
RASP
t
RP
RAS
t
t
T
PRWC
t
t
t
t
RSH
CAS
t
CRP
CP
CP
t
t
t
CAS
RCD
CAS
CAS
t
t
RAD
t
t
t
ASC
t
CAH
ASR
ASC
RAH
ASC
t
t
t
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
t
t
t
CWL
RWD
AWD
CWL
CPW
AWD
CWL
CPW
AWD
t
RWL
t
t
t
t
t
CWD
CWD
RCS
CWD
RCS
WE
t
t
t
t
t
WP
t
DS
RCS
DZO
WP
DS
WP
t
t
t
DS
t
DZC
DZC
DZC
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
OE
t
t
t
OED
OED
OED
t
t
t
DZO
DZO
t
t
t
OEH
OEH
OEH
t
t
t
OHO
OHO
OHO
t
t
t
t
t
t
OEA
CAC
OEA
CAC
OEA
CAC
t
t
t
AA
AA
AA
t
t
CPA
CPA
t
t
RAC
t
t
t
OEZ
t
t
OEZ
OEZ
CLZ
CLZ
CLZ
High-Z*
Dout
Dout 1
Dout 2
Dout N
23
HM51W17800B Series
Self Refresh Cycle (L-version)*19, 20, 21, 22
t
t
t
RASS
RP
RPS
RAS
t
T
t
t
t
CRP
RPC
CP
t
CSR
t
CHS
CAS
WE
t
t
WRH
WRP
t
OFF
High-Z
Dout
24
HM51W17800B Series
Package Dimensions
HM51W17800BJ/BLJ Serie s(CP-28DA)
Unit: mm
18.17
18.54 Max
28
15
14
1
0.74
1.30 Max
1.27
0.10
9.40 ± 0.25
0.43 ± 0.10
HM51W17800BS/BLS Serie s(CP-28DNA)
Unit: mm
18.41
18.84 Max
15
28
1
14
0.74
1.165 Max
1.27
0.10
6.79 ± 0.18
0.43 ± 0.10
25
HM51W17800B Series
Package Dimension s(cont)
HM51W17800BTT/BLTT Series (TTP-28DA)
Unit: mm
18.41
18.81 Max
28
15
14
1
1.27
0.21 M
0.40 ± 0.10
11.76 ± 0.2
0 – 5°
0.10
0.68
0.50 ± 0.10
1.15 Max
HM51W17800BTS/BLTS Serie s(TTP-28DB)
Unit: mm
18.41
18.81 Max
28
15
14
1
1.27
0.21 M
0.40 ± 0.10
9.22 ± 0.2
0 – 5°
0.10
0.63
0.50 ± 0.10
1.15 Max
26
HM51W17800B Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part
of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any
intellectual property claims or other problems that may result from applications based on the examples
described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party
or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
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16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Tel: 415-589-8300
Fax: 535-1533
Fax: 415-583-4207
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Berkshire SL6 8YA
United Kingdom
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Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 0628-585000
Fax: 0628-778322
Tel: 27359218
Fax: 27306071
27
HM51W17800B Series
Revision Record
Rev. Date
Contents of Modification
Drawn by
Approved by
0.0
0.1
Jul. 13, 1994
Initial issue
Y. Takahashi K. Hayakawa
Y. Takahashi K. Hayakawa
Nov. 11, 1994
DC characteristics
Addition of note 4
0.2
1.0
Dec. 2, 1994
Jun. 29, 1995
Change of Block Diagram
Y. Takahashi K. Hayakawa
DC characteristics
K. Goto
K. Hayakawa
I
I
CC2 max: 100/100/100 µA to 150/150/150 µA
CC11 max: 200/200/200 µA to 250/250/250 µA
RAS-only refresh cycle
CAS-before-RAS refresh cycle
Self refreh cycle
2.0
3.0
Sep. 20, 1995
Jul. 5, 1996
Power dissipation
Standby mode (L-version): 0.36 mW max
to 0.54 mW max
Y. Takahashi K. Hayakawa
Addition of HM51W17800BTS/BLTS Series (TTP-
28DB)
Addition of HM51W17800BS/BLS Series (CP-28DNA)
AC characteristics
Change of notes18 and 23
Timing waveforms
Change of early write cycle and EDO page mode
early write cycle
Deletion of note: tOEH ≥ tCWE
28
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