HM530281RTT-45 [HITACHI]
331,776-word x 8-bit Frame Memory; 331776字×8位的帧存储器
| 型号： | HM530281RTT-45 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 331,776-word x 8-bit Frame Memory |
| 文件： | 总47页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM530281R Series
331,776-word × 8-bit Frame Memory
ADE-203-251B
Rev. 1.0
June 6, 1997
Description
The HM530281R series memory products provide completely asynchronous I/O and operate at the high
speed of 50 MHz. The HM530281R series memory products provide reset, jump, and line increment/hold
pointer control functions that can be used in synchronization with independent clocks on each of the I/O
ports. Memory can be accessed immediately without any waiting period after the execution of these
functions. In addition to the FIFO function, the 281R series products support an address structure that is
compatible with HDTV, NTSC, and PAL standards, and can be used in a wide range of applications, such
as noise reducers, TBC (time-based correction), inter-frame YC separation, and special function modes
(e.g., multi-freeze, P-in-P) in the digital TV, VCR, and video camera application. They are also appropriate
for use as inter-system speed conversion buffer memories in communications systems, as cache memories
of HDD and MOD, and as frame buffer of VGA.
Features
•
•
Organization: 331,776-word × 8-bit
Completely asynchronous operation of the serial read port and write port.
Internal generation of read and write addresses
Internal memory operation control provided on-chip
High speed read/write cycle time: 50 MHz
Reset, jump functions
•
•
Independent execution for read and write ports
Can be executed with arbitrary timing
Allow immediate access after execution (read/write) (for the jump function, when the address setup
is complete)
Jump address specifiable in 32-word units
2 dimensional address
•
•
•
Line increment/hold address pointer control function
Window scan function
Datasheet Title
•
Can handle HDTV, NTSC, and PAL standards
Line length: Up to 1152 bits (Arbitrary line lengths can also be handled by using the line reset
function.)
Line count: Up to 324 lines
•
•
Built-in self-refresh eliminates the need for external refresh control.
Power supply voltage: VCC = 5.0 V ± 10%.
Ordering Information
Type No.
Cycle Time
Memory Organization
Package
*2
HM530281RTT-20
HM530281RTT-25
HM530281RTT-34
HM530281RTT-45
20 ns
25 ns
34 ns
45 ns
331,776 words × 8 bits
44-pin TSOP (TTP-44DB)
*3
1152 dots × 288 lines × 8 bits
1024 dots × 324 lines × 8 bits
Notes: 1. Selectable following two kinds of addressing mode by mode pins
2. 1 dimensional addressing mode
3. 2 dimensional addressing mode
Pin Arrangement
Din0
Din1
Din2
Din3
Din4
Din5
Din6
Din7
VSS
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
Dout0
Dout1
Dout2
Dout3
Dout4
Dout5
Dout6
Dout7
VSS
2
3
4
5
6
7
8
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC
CC
OE
WE
CGW
WCK
CGR
RCK
WRS
RRS
WLRS
WCLR
WWND
WAS
RLRS
RCLR
RWND
RAS
WAD
RAD
TEST1
TEST2
TEST3
MODE0
MODE1
TEST0
(Top view)
2
Datasheet Title
Pin Description
Functions
Symbol
Din0 to Din7
Dout0 to Dout7
WCK
2 dimensional address
Data input
1 dimensional address
Data input
Data output
Data output
Write clock
Write clock
RCK
Read clock
Read clock
WRS
Write reset
Write reset
RRS
Read reset
Read reset
WE
Write enable
Write enable
Output enable
Write clock gate
Read clock gate
Write address set
Write address
Read address set
Read address
VCC or GND
OE
Output enable
Write clock gate
Read clock gate
Write address set
Write address
Read address set
Read address
Write line reset
Read line reset
Write window mode
Read window mode
Write clear
CGW
CGR
WAS
WAD
RAS
RAD
WLRS
RLRS
VCC or GND
WWND
RWND
WCLR
RCLR
VCC or GND
VCC or GND
VCC or GND
Read clear
VCC or GND
MODE 0 to 1
VCC
Mode selection input
Power supply
Ground
Mode selection input
Power supply
Ground
VSS
TEST0 to TEST3
Connect to ground
Connect to ground
3
Datasheet Title
Block Diagram
32-word
8
32-word
8
32-word
8
32-word
×
8
×
×
×
Memory
array
× 8
× 8
Din
Dout
OE
1
×
×
×
*
*
1152 dot 288 line
8
8
×
1
×
1024 dot 324 line
WE
1
×
10368 dot 32 word 8*
Write
counter
Memory
controller
Read
counter
RCK
CGR
WCK
CGW
RRS
RAS
RAD
Refresh
counter
WRS
WAS
WAD
RLRS
RWND
RCLR
WLRS
WWND
WCLR
Note : 1. Selected by the mode pin
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
*1
Pin voltage
–1.0 to +7.0
1.0
Power dissipation
PT
W
Operating temperature
Storage temperature
Topr
Tstg
Tbias
0 to +70
°C
°C
°C
–55 to +125
–10 to +85
Storage temperature (when biased)
Note: 1. The permissible values with respect to VSS.
4
Datasheet Title
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
4.5
0
Typ
5
Max
Unit
V
Power supply voltage
5.5
0
VSS
0
V
Input voltages
VIH
2.7
–0.5
—
—
6.5
0.6
V
*1
VIL
V
Note: 1. When the pulse width is under 10 ns, VIL min = –3.0 V.
DC Characteristics (VCC = 5.0 V ± 10%, VSS = 0 V, Ta = 0 to +70°C)
HM530281-20 HM530281-25 HM530281-34 HM530281-45
Test
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Conditions
Operating ICCA
power
supply
—
—
110 135
15 25
—
—
90 120
15 25
—
—
70 95
15 25
—
—
55 75 mA Iout = 0,
WCC = tRCC
Min
t
=
current
Standby
power
ICCS
15 25 mA VCC = 5.5 V
WCK, RCK =
supply
current
“L” fix
Input
leakage
current
ILI
–10 —
–10 —
10 –10
10 –10
—
—
10 –10
10 –10
—
—
10 –10
10 –10
—
—
10 mA VCC = 5.5 V,
Vin = VSS to
VCC
Output
leakage
current
ILO
10 mA OE = Vin
Vout = VSS to
VCC
Output
voltages
VOL
VOH
—
—
—
0.4
—
—
—
—
0.4
—
—
—
—
0.4
—
—
—
—
0.4
V
IOL = 2.1 mA
2.4
2.4
2.4
2.4
—
V
IOH = –1.0 mA
Capacitance*1
Test
Parameter
Symbol
Cin
Typ
Max
Units
pF
Conditions
Input capacitance
Output capacitance
—
—
5
7
Vin = 0 V
Cout
pF
Vout = 0 V
Note: 1. These parameters are sampled values, not values measured for all units.
5
Datasheet Title
AC Characteristics
Test Conditions
•
•
•
•
Input pulse level: VSS to 3.0 V
Input rise/fall time: 3 ns
I/O timing reference level: 1.5 V
Output load: 1 TTL + 50 pF (including jig and scope capacitances)
HM530281R-20 HM530281R-25 HM530281R-34 HM530281R-45
Parameter
Symbol Min
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18
—
—
18
15
—
—
—
—
Min
25
10
10
8
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
23
—
—
20
18
—
—
—
—
Min
34
12
12
10
10
5
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25
—
—
25
20
—
—
—
—
Min
45
15
15
10
10
5
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
—
—
25
20
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write clock cycle time
tWCC
20
8
Write clock pulse width (high) tWC
Write clock pulse width (low) tWCP
8
WRS setup time
WRS hold time
tWRS
tWRH
tDS
7
7
8
Data input setup time
Data input hold time
CGW setup time
CGW hold time
5
5
tDH
6
6
6
6
tWGS
tWGH
tWES
tWEH
tRCC
7
8
10
10
5
10
10
5
7
8
WE setup time
5
5
WE hold time
6
6
6
6
Read clock cycle time
20
8
25
10
10
8
34
12
12
10
10
—
6
45
15
15
10
10
—
6
Read clock pulse width (high) tRC
Read clock pulse width (low) tRCP
8
RRS setup time
tRRS
tRRH
tRAC
tOH
7
RRS hold time
7
8
Access time from RCK
Output hold time
Output enable time
Output enable access time
Output disable time
CGR setup time
—
6
—
6
tOLZ
tOAC
tOHZ
tRGS
tRGH
tWSS
tWSH
0
0
0
0
—
0
—
0
—
0
—
0
7
8
10
10
10
10
10
10
10
10
CGR hold time
7
8
WAS setup time
WAS hold time
7
8
7
8
6
Datasheet Title
AC Characteristics (cont)
HM530281R-20 HM530281R-25 HM530281R-34 HM530281R-45
Parameter
Symbol Min
Max
—
Min
8
Max
—
Min
10
10
5
Max
—
Min
10
10
5
Max
—
Unit
ns
RAS setup time
RAS hold time
tRSS
tRSH
tWAS
7
7
5
—
8
—
—
—
ns
Write address input setup
time
—
5
—
—
—
ns
Write address input hold time tWAH
Read address input setup time t RAS
Read address input hold time tRAH
6
5
6
7
7
7
7
7
7
7
7
7
7
7
7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
5
6
8
8
8
8
8
8
8
8
8
8
8
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
6
6
WLRS setup time
WLRS hold time
RLRS setup time
RLRS hold time
WCLR setup time
WCLR hold time
RCLR setup time
RCLR hold time
WWND setup time
WWND hold time
RWND setup time
RWND hold time
tWLS
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
tWLH
tRLS
tRLH
tWCLS
tWCLH
tRCLS
tRCLH
tWWDS
tWWDH
tRWDS
tRWDH
7
Datasheet Title
Input and Output Pin Functions
DIN0 to DIN7 (data input) Input: The DIN pins input 8 bits of data. Data is input on the rising edge of the
cycle of WCK that follows a low level on both CGW and WE.
DOUT0 to DOUT7 (data output) Output: The DOUT pins output 8 bits of data. Data output is synchronized
with the RCK clock, and the access time is specified from the rising edge of the RCK cycle.
WCK (write clock) Input: WCK is the write clock input pin. The input of write data is synchronized
with this clock. Write data is input on the rising edge of the cycle of WCK that follows a low level on both
CGW and WE, and when CGW is low, the internal write address pointer is incremented at the same time.
Input of the write jump address is also synchronized with this clock. The 14 bits or 15 bits of the write
jump address are read in sequentially from the WCK cycle that set WAS low, irrespective of write data
acquisition.
RCK (read clock) Input: RCK is the read clock input pin. Read data is output in synchronization with
this clock when both CGR and OE are low, and when CGR is low, the internal read address pointer is
incremented at the same time. Input of the read jump address is also synchronized with this clock. The
read jump address is read in sequentially starting at the RCK cycle in which RAS was set low,
independently of read data output.
WRS (write address pointer reset) Input: WRS is a reset signal input that resets the write address
pointer to 0 when WAS and WLRS are high, resets to the head of the line currently being written when
WAS is high and WLRS is low, and jumps to the preset write jump address when WAS is low. *1 Only the
falling edge of this reset input is detected, and, on the first WCK cycle following that falling edge, a write
cycle to the set address is started immediately.
RRS (read address pointer reset) Input: RRS is a reset signal input that resets the read address pointer to
0 when RAS and RLRS are high, resets to the start of the line currently being read when RAS is high and
RLRS is low, and jumps to the read jump address when RAS is low.*1 Only the falling edge of this reset
input is detected, and, on the first RCK cycle following that falling edge, a read cycle at the set address is
started immediately.
WE (write enable) Input: WE is an input signal that controls the enabling/disabling of the data input pins.
When WE is low, input data is acquired on the WCK cycle, and when WE is high, data input is disabled
and the previous memory data is maintained. Note that the write address pointer is incremented by the
WCK write clock without regard for the level of WE.
OE (output enable) Input: OE is an input signal that enables/disables the data output pins. When OE is
low, data output is enabled, and when high, data output is disabled and the output pins go to the high
impedance state. Note that the read address pointer is incremented by the RCK read clock without regard
for the level of OE. Therefore, data can be jumped over during read simply by disabling output with OE.
CGW (clock gate for write) Input: CGW is an input signal that enables/disables incrementing of the
internal write address pointer. When C G W is low, the write address pointer is incremented in
synchronization with the WCK write clock, and when high, incrementing is stopped. Therefore time axis
compression can be easily implemented without stopping the write clock by using CGW.
8
Datasheet Title
CGR (clock gate for read) Input: CGR is an input signal that enables/disables incrementing of the
internal read address pointer. When CGR is low, the read address pointer is incremented in
synchronization with the RCK read clock, and when high, incrementing is stopped. Therefore time axis
expansion can be easily implemented without stopping the read clock by using CGR.
WAS (write address set and jump) Input: WAS is an input signal that initiates write jump address input
when WRS is high and jumps to the previously input write jump address when WRS is low. The falling
edge of this input signal is detected, and either a write jump address input is initiated or a jump to the
previously input write jump address is executed on the first WCK cycle following the fall of WAS.
WAD (write jump address) Input: WAD is the input pin for the write jump address. The 14/15 bits of
the write jump address are read in sequentially from the high order bit, starting at the WCK cycle (when
WRS was high) in which WAS was set low.*2
RAS (read address set and jump) Input: RAS is an input signal that initiates read jump address input
when RRS is high and jumps to the previously input read jump address when RRS is low. The falling edge
of this input signal is detected, and either the read jump address input is initiated or the jump to the
previously input read jump address is executed on the first WCK cycle following the fall on RAS.
RAD (read jump address) Input: RAD is the input pin for the read jump address. The 14/15 bits of the
write jump address are read in sequentially from the high order bit, starting at the RCK cycle (when RRS
was high) in which RAS was set low.*2
9
Datasheet Title
WLRS (write line reset) Input (in 2 dimensional addressing mode): WLRS is an input pin for resetting
the write address pointer to the start of the line from an arbitrary dot for each line.*3 Only the falling edge
of this signal is detected, and, on the first WCK cycle following that falling edge, the write address pointer
is set to the head of the next line when WRS is high, and to head of the current line when WRS is low.*3
RLRS (read line reset) Input (in 2 dimensional addressing mode): RLRS is an input pin for resetting
the read address pointer to the start of the line from an arbitrary dot for each line.*3 Only the falling edge of
this signal is detected, and, on the first RCK cycle following that falling edge, the write address pointer is
set to the head of the next line when RRS is high, and to head of the current line when RRS is low.*3
WWND (write window scan) Input (in 2 dimensional addressing mode): WWND is an input signal
that specifies the use of the window scan function. When executing a write jump with WRS and WAS low,
if WWND is set low at the same time, a scan of the window region that takes that write jump address as its
starting point will begin (see note below).
RWND (read window scan) Input (in 2 dimensional addressing mode): RWND is an input signal that
specifies the use of the window scan function. when executing a read jump with RRS and RAS low, if
RWND is set low at the same time, a scan of the window region that takes that read jump address as its
starting point will begin.*4
WCLR (write clear) Input: WCLR is an input signal that, independently of the levels on WRS, WAS,
WLRS and WWND resets the write address pointer to 0 and clears the window scan function. This
function is executed immediately in the WCK cycle in which WCLR was set low. This clear operation
should also be performed after applying power to the HM530281R.
RCLR (read clear) Input: RCLR is an input signal that, independently of the levels on RRS, RAS, RLRS
and RWND resets the read address pointer to 0 and clears the window scan function. This function is
executed immediately in the RCK cycle in which RCLR was set low. This clear operation should also be
performed after applying power to the HM530281R.
Notes: 1. The reset destination in window scan mode changes as follows.
Reset to 0: Reset to the window start.
Reset to line start: Reset to the point at the left edge of the window for the line
2.
Addressing Mode Address Structure
Input Address
1 dim. add. (FIFO) 0 to 10,367 blocks
Address bits A13 to A0
2 dim. add. (1)
32 horizontal blocks by 324 vertical lines Line address bits V8 to V0,
horizontal address bits H4 to H0
2 dim. add. (2)
36 horizontal blocks by 288 vertical lines. Line address bits V8 to V0,
horizontal address bits H5 to H0
3. When window scan mode is set, the reset is to the point at the left edge of the window for the
line.
4. When window scan is set, the horizontal address of the pointer reset destination when
increment/hold is executed will be the left edge of the window. Also, when a reset is executed,
the pointer will be reset to the starting point of the window.
Thus it is possible to scan arbitrary window regions within the screen independently for read
and write by using these line reset and reset functions.
10
Datasheet Title
Memory Structure
The memory is organized as 331,776-word of 8-bit each, and these words can be accessed sequentially,
since the address pointer can be incremented by inputting a clock signal. Addresses are allocated
corresponding to 32 word blocks.
The mode pins switch between the three addressing modes shown below.
Mode 0
Mode 1
Addressing Mode Address Structure
Capacity
0
1
0
0
1 dim. add. (FIFO) 0 to 10,367 blocks
331,776 words
1024 dots by 324 lines
2 dim. add. (1)
32 horizontal blocks by 324
vertical lines
0
1
2 dim. add. (2)
36 horizontal blocks by 288
vertical lines
1152 dots by 288 lines
Notes: 1. In 1 dimensional addressing mode, blocks 0 to 10367 are accessed cyclically.
2. In the 2 dimensional addressing modes, the line head can be reset at an arbitrary dot on each
line.
Operations
Write
Write operation: When the WE and CGW inputs are low, 8 bits of write data are input in synchronization
with the WCK clock. The input data is read in to the word indicated by the address pointer on the next
rising edge of the WCK cycle. This allows read data and write data to be handled with the same clock, and
cascade connections to be easily implemented.
Write reset operations: When CGW is low, by setting WRS low, the write address pointer can be set
immediately on that WCK cycle to the address 0 block head. This operation can be executed independently
of the input level of WE. (See ‘Notes on usage’ 15 on the operation when CGW is high.)
Write address pointer increment operations:
The write address pointer is incremented in
synchronization with WCK when CGW is low. It is possible to apply a write mask in WCK clock units by
setting the WE input high. In this case, the previous memory data will be retained. The write address
pointer increment function can be stopped by setting the CGW input high. This allows time axis
compression to be implemented easily. (See ‘Notes on usage’ 7, 9 and 10 for interval specifications of
*1
write system reset operations. )
Note: 1. The write system reset operation stands for write reset, write jump, write window reset, write
line reset and write clear.
11
Datasheet Title
WE and CGW Input Level, Write Address Pointer, and Data Input State Relationship
WCK Rising Edge
CGW
WE
L
Internal Write Address Pointer
Data Input
L
L
H
Incremented
enable
H
disable (memory data is retained)
—
Stopped
Note: Data is input when the WE input is low.
Read
Read operation: 8 bits of read data are output in synchronization with the RCK clock when the OE and
CGR inputs are low. The access time is stipulated from the rising edge of the RCK clock.
Read reset operations: When CGR is low, by setting RRS low, the read address pointer can be set
immediately on that RCK cycle to address 0 and the data will then be output. This operation can be
performed independently of the input level of OE. (See ‘Notes on usage’ 14 on the operation when CGR is
high.)
Read address pointer increment operations: The read address pointer is incremented in synchronization
with RCK when CGR is low. Data outputs go to the high impedance state when the OE input is set high.
The reset address pointer increment function can be stopped by setting the CGR input high. This allows
time axis expansion to be implemented easily. (See ‘Notes on usage’ 7, 8 and 10 for interval specifications
*2
of read system reset operations. )
Note: 2. The read system reset operations stands for read reset, read jump, read window reset, read line
reset and read clear.
Relation Between the OE and CGR Input Levels and the Read Address Pointer and Data Output
States
RCK Rising Edge
CGR
OE
L
Internal Read Address Pointer
Data Output
Output
L
Incremented
L
H
High impedance
Output data held
High impedance
H
H
L
Stopped
H
Note: Data is input when the OE input is low.
Line Reset (write line reset and read line reset, in 2 dimensional addressing modes)
When the 281R series products are used in 2 dimensional addressing modes, the line length can be set to be
either 1024 dots (2 dimensional (1)) or 1152 dots (2 dimensional (2)). In these modes, after accessing the
12
Datasheet Title
data at the last dot (address) on each line, address pointer incrementing is stopped. Access is restarted at
either the first dot at the head of the next line or at the first dot at the head of the current line by executing
either a line increment or a line hold, respectively. Also, since these line reset operations can be executed
at any arbitrary point in the middle of a line, an arbitrary line length (of between 64 dots and the actual line
length) can be realized.
Line increment operation: In case clock gate signal (CGW, CGR) is low, the read and write line
increment operations are executed by setting RLRS low and RRS high, and setting WLRS low and WRS
high respectively. When these operations are executed, the next access goes immediately to the starting dot
of the next line.
Line hold operation: In case clock gate signal (CGW, CGR) is low, the read and write line hold
operations are executed by setting RLRS and RRS low, and setting WLRS and WRS low respectively.
When these operations are executed, the next access goes immediately to the starting dot of the current line.
Note that the read line hold operation is invalid on the first line following a 0 reset or jump. In this case,
the same effect can be achieved by re-executing the reset or jump operation (resetting only the H address to
0). If the reset interval specifications are met (see Notes on Usage 1 to 3), the line reset operation can be
performed on an arbitrary RCK/WCK clock cycle without regard for the levels of the OE and WE inputs.
(See ‘Notes on usage’ 15 and 16 on the operation when clock gate signal (CGW, CGR) is high.)
Jump (independent functions for read and write)
It is possible to set the address pointer to the start address of an arbitrary block in 32 word units. After
initializing a jump address setup for read and/or write, after 64 WCK or 64 RCK cycles, it is possible to
execute a jump to that address (random access in 32 word by 8 bit units) independently for read and write.
(See ‘Notes on usage’ 12 on the jump operation to ‘0’ address and line end address.)
Jump address setup: The read and write jump addresses are serially input independently from the RAD
and WAD pins in synchronization with the RCK and WCK clock inputs respectively. Address input start is
enabled by setting the RAS and/or WAS inputs low for read and write respectively, and 14/15 bits of jump
address are input sequentially starting with that cycle.*10 Note that the read and write operations can
continue independently of this address input operation. Jump address setup is executed regardless of WE,
CGW and OE, CGR. Following the start of address input, it is possible to mask the input of address bits
below an arbitrary bit position by returning RAS or WAS to the high level at the desired bit position. This
can be convenient in applications that need to jump a fixed interval, since the low order bits of the address
will be fixed. When all 14 bits of an address are to be input, be sure to hold RAS and WAS low for the full
14-clock period.
Jump operation: In case clock gate signal (CGW, CGR) is ‘L’, the jump operation is executed by setting
RRS and RAS low for read, and by setting WRS and WAS low for write, and the address set is accessed
immediately from that RCK or WCK cycle. Note that as long as the interval specifications listed in Notes
7 to 9 are met, the jump operation can be executed on any RCK or WCK cycle without regard for the
values of OE and WE. (See ‘Notes on usage’ 14 and 15 on the operation, when clock gate signal (CGW,
CGR) is high.)
13
Datasheet Title
Window Scan (independent functions for read and write)
The window scan function can be used with either the 2 dimensional (1) or (2) addressing modes, and is a
function which scans a rectangular region with an arbitrary starting point. The jump address setup function
(see Jump address setup above) is used to specify the starting point
Initiating window scan: The window scan function is started by setting WWND to low for read or
RWND low for write, and executing a read or write jump operation (see Jump operation above). Window
scan will start immediately from that cycle.
Window scan operation: When the window scan function is started, one of the functions described below
will be executed independently for read and write.*11 Also note that as long as the interval conditions listed
in Notes 7 to 9 are met, these operations can be executed at arbitrary dots without regard for the address
block organization.
Clearing window scan: The window scan function is turned off either by executing a reset or jump with
RWND (for read) or WWND (for write) set high, or by executing the clear operation described in section
Clear below. Note that both setting and clearing window scan mode are executed independently of OE and
WE.
(See ‘Notes on usage’ 14 and 15 on the operation when clock gate signal (CGW, CGR) is high.)
Operation
Reset
Address Pointer Control
Reset to the first dot at the start of the window.
Line increment
Line hold
Reset to the first dot at the left edge of the window on the next line.
Reset to the first dot at the left edge of the window on the current line.
14
Datasheet Title
Overview of the window scan operation:
0
0
31
1
63
2
Horizontal (dot)
Horizontal address (H)
1023(1151)
31(35)
0
First point of the screen
First point of the window
(M, N)
Window area
Vertical
(line)
Line hold
(V, N)
(V + 1, N)
(V, N + n)
(M + m, N + n)
323
(287)
Note: 1. M and N are addresses, M is in line units, N is units of 32 dots,
and m and n are in line and dot units respectively.
Clear (independent functions for read and write)
The clear function both resets the address pointer to 0 without regard for the value on WRS, WAS, WLRS,
WWND, RRS, RAS, RLRS and RWND, and if window mode is set, clears window mode.
Clear Operation: When clock gate signal (CGW, CGR) is low, the clear operation can be executed on
any cycle by setting the RCLR pin low for read and the WCLR pin low for write. When the interval
conditions listed in Notes on usage 7 to 10 are met, clear operation is executed at any time without regard
of the level on WE and OE. (See ‘Notes on usage’ 14 and 15 on the operation when clock gate signal
(CGW, CGR) is high)
Access of New and Previous Data
New data access (follow-up read out of data currently being written): Written data can be read out 160
WCK cycles after it is written. However, it is necessary to execute the read jump address setup operation
outside the time period between 32 WCK cycles before write to that address is started and 32 WCK cycles
after write to that address is completed.
15
Datasheet Title
•
It is possible to read out the new data of 32 word block when jumping to an address at least 128 WCK
clock cycles after write to that address was started. Note that in this case, there is more than enough
time for the read jump address setup operation even if it is begun 32 or more clock cycles after the
completion of the write operation.
•
It is possible to read out the new data of less than 32 word block when 128 WCK clock after write
system reset was input.
Starting and clearing window scan:
Window off
Clear
(Reset)
(Jump)
(Clear)
Start
(Window jump)
(Reset)
(Line increment)
(Line hold)
(Jump)
Window on
New setup
(Window jump)
(Reset to the window origin point)
(Line increment)
(Line hold)
(Address setup)
At least 96 WCK clock are necessary between completion 32 word block data input and starting previous
address of 32 word block data output. Generally this mean, 160 WCK clock separation between write and
read address pointer.
Previous data access (reading out data prior to that of the current write operation): The previous data
can be read out up to 32 WCK clock cycles after the write operation. Therefore, these memories can be
used to provide delay times of between 160 and 331,808 (331,776 + 32) clock cycles.
16
Datasheet Title
Power On
Wait at least 100 µs after power-on to begin operation. At this time the write and read address pointers are
undefined.
The following operation should be executed.
•
•
•
•
CGW and CGR should be hold low.
Reset cycle when 1 dimensional addressing mode.
Clear cycle when 2 dimensional addressing mode.
Dummy cycle of over 64 WCK and 64 RCK clock cycle.
Then, initiate the desired operating mode by providing the signal input combination given by the truth
tables below.
Function Table
Note: Description of operations of function table is based on the operation on condition CGW, WE and
CGR, OE is low.
1 Dimensional Addressing Modes
Write
WCK Rising Edge
WRS
WAS
Operation
H
H
Normal state
In the normal state, the write address pointer is incremented in
synchronization with WCK.
L
L
H
H
L
L
Reset
Jump
The write address pointer is reset to 0.
Jump to the address A to which the write address pointer is set.
Address setup The write jump address is input.
Read
RCK Rising Edge
RRS
RAS
Operation
H
H
Normal state
In the normal state, the read address pointer is incremented in
synchronization with RCK.
L
L
H
H
L
L
Reset
Jump
The read address pointer is reset to 0.
Jump to the address A to which the read address pointer is set.
Address setup The read jump address is input.
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Datasheet Title
2 Dimensional Addressing Modes (when window scan is not used)
Write *1
Operation
Levels At The Rise Of WCK
Write Address Pointer Write Jump
WRS WAS WLRS WWND WCLR
Control
Address
Notes
H
H
H
H
H
Normal state Incremented in
—
2
synchronization with
WCK
L
L
H
L
H
H
H
H
H
H
Reset
Jump
Reset to (0, 0)
—
—
Jump to the set address
A
H
H
L
H
L
H
H
H
H
Address set
—
Set
H
Line
increment
Reset to the first bit of the —
next line
2
2
L
H
L
H
H
L
Line hold
Reset to the first bit of the —
current line
Clear
Reset to (0, 0)
Note: (—: VIH or VIL)
Read*1
Operation
Levels At The Rise Of WCK
RRS RAS RLRS RWND RCLR
Read Address Pointer
Control
Read Jump
Address
Notes
H
H
H
H
H
Normal state Incremented in
synchronization with RCK
—
3
L
L
H
L
H
H
H
H
H
H
Reset
Jump
Reset to (0, 0)
Jump to the set address
A
—
H
H
L
H
L
H
H
H
H
Address set
—
Set
H
Line
increment
Reset to the first bit of the —
next line
3
3
L
H
L
H
H
L
Line hold
Reset to the first bit of the —
current line
Clear
Reset to (0, 0)
—
Note: (—: VIH or VIL)
18
Datasheet Title
2 Dimensional Address Modes (when window scan is not used)
Write
Operation
Write Address
Pointer Control
Write
Jump
Window
Mode After
Levels At The Rise Of WCK
Window Window Address Execution
Mode Off Mode On
WRS WAS WLRS WWND WCLR
Notes
L
H
H
H
H
H
H
H
Reset
Normal state Incremented in
synchronization with
Reset to (0, 0)
—
—
Off
—
H
—
4
WCK
H
L
H
H
L
L
—
—
H
H
Line
increment
To the
first bit of edge of
the next the
To the left —
—
—
line
window
on the
next line
Line hold
To the
To the left —
first bit of edge of
the
the
current
line
window
on the
current
line
H
L
L
L
H
H
—
H
H
H
Address set
Jump
—
Set
—
—
Jump to the set
address A
Off
L
L
H
L
H
H
L
Window
jump
Jump to the set
address A
—
—
—
On
—
6
L
H
—
H
L
Reset
Reset to the window
origin point A
—
—
—
Clear
Reset to (0, 0)
Off
Note: (—: VIH or VIL)
19
Datasheet Title
Read
Operation
Levels At The Rise Of WCK
Read Address Pointer Control
Read
Window
Window Window Jump
Mode After
RRS RAS RLRS
RWND RCLR
Mode Off Mode On Address Execution Notes
L
H
H
H
H
H
H
H
Reset
Reset to (0, 0)
—
—
Off
—
H
—
Normal state Incremented in
synchronization with
5
RCK
H
L
H
H
L
L
—
—
H
H
Line
increment
To the
first bit of edge of
the next the
To the left —
—
—
line
window
on the
next line
Line hold
To the
To the left —
first bit of edge of
the
the
current
line
window
on the
current
line
H
L
L
L
H
H
—
H
H
H
Address set
Jump
—
Set
—
—
Jump to the set
address A
Off
L
L
H
L
H
H
L
Window
jump
Jump to the set
address A
—
—
—
On
—
6
L
H
—
H
L
Reset
Reset to the window
origin point A
—
—
—
Clear
Reset to (0, 0)
Off
(—: VIH or VIL)
•
Notes on usage.
1. Hold the WWND and RWND pin high when window mode is not used.
2. The write address pointer is incremented up to the last dot on the current line, and then stopped.
Writing is started immediately from the first dot on the next line by execution of the line increment
operation. Also, writing is started immediately from the first dot on the current line by execution
of the line hold operation.
3. The read address pointer is incremented up to the last dot on the current line, and then stopped.
Reading is started immediately from the first dot on the next line by execution of the line
increment operation. Also, reading is started immediately from the first dot on the current line by
execution of the line hold operation.
4. The write address pointer is incremented up to the last address on the line, and then stopped.
Writing is started immediately from the first dot on the next line or the left edge of the window by
execution of the line increment operation.
20
Datasheet Title
5. The read address pointer is incremented up to the last address on the line, and then stopped.
Reading is started immediately from the first dot on the next line or the left edge of the window
by execution of the line increment operation.
6. It is possible to move directly from an old window to a new window in window mode by setting up
a new jump address and executing a window setup jump operation. However, the new jump
address should be input after access to the last line of the old window.
7. Read system reset operations (read reset, read jump, read window reset, read line reset and
read clear) and the read address set up operation cannot be executed for consecutive RCK
clock cycles. Similarly write system reset operations (write reset, write jump, write window reset,
write line reset and write clear) and the write jump address setup operation cannot be executed
for consecutive WCK clock cycles.
8. Read system reset (read reset, read jump, read window reset, read line reset and read clear)
operations and read jump address set operations must be performed at times separated by at
least 64 RCK clock cycles. (There is no need to use only 32 word addressing units, and these
operations can be performed on any clock cycle).
9. Write system reset operations (write reset, write jump, write window reset, write line reset and
write clear) must be performed at times separated by at least 64 WCK clock cycles. When
address is input, write/read system reset can not be executed.
10. It is possible to input the write system reset in the middle of 32 word unit addressing. In this
case, not only must the condition of note 8 be met, but furthermore, pairs of write system resets
for units of less than 32 words must be separated by at least 160 WCK clock cycles. When the
write system reset is executed at less than 32 words, the data up to the point to which the
address pointer has advanced will be written, and the remaining data will retain the old values.
(Note that after the completion of a write of less than 32 words, a write reset is required to write
the data for the last address into the memory array.)
11.
Addressing Mode Address Structure
Input Address
1 dim. add. (FIFO) 0 to 10,367 blocks
Address bit A13 to A0
2 dim. add. (1)
32 horizontal blocks by 324 vertical lines
Line address bits V8 to V0,
horizontal address bits H4 to H0
2 dim. add. (2)
36 horizontal blocks by 288 vertical lines
Line address bits V8 to V0,
horizontal address bits H5 to H0
12. Specifiable window sizes
Horizontal: Between 64 dots and the length of the line.
Vertical: Between 1 line and the maximum number of lines.
13. Location 0 and line end cannot be specified as a jump address. Use a reset to access location
0.
14. Any number of read system reset operations can be input when CGR is high but in this case the
only first reset is effective. This read system reset operation (read reset, read jump, read
window reset, read line reset and read clear) is executed at the rising edge of the RCK just after
CGR is set low.
15. Any number of write system resets can be input when CGW is high, but the only first reset is
effective. This write system reset operation is executed at the rising edge of the WCK just after
CGW is set to low.
16. When window scan mode is used any case after power on, WWND and WRS or RWND and
RRS pins are should be input same signal.
21
Datasheet Title
Supplement
If the read system reset interval (at least 64 RCK clock cycles) of note 7, or the write system reset interval
for less than 32 word units (and at least 160 WCK clock cycles) are not provided (see note 9), it is possible
for the 32 words of data of the first address after the reset to be invalid, or for the first write of less than 32
words following the write reset to fail to occur. However, even in this case, address pointer control will
function correctly, and valid data will be output for the second and following addresses. (However, in this
case the condition of note 8 and the 32 clock or longer read system reset/read jump address interval must be
provided.)
Timing Waveforms
Write Cycle
Write address reset
Cycle N - 1
Cycle N
tWRS
Cycle 0
tWCC
Cycle 1
tWCP
Cycle 2
WCK
WRS
tWC
tWRT
tWRS
tDS tDH
D(0)
High
WAS
Din
D(N - 2)
D(N - 1)
Add 'X'
D(N)
D(1)
D(2)
Add '0'
Note: The write address pointer is reset to 0 starting with the WRS low cycle. Only the falling
edge of the WRS signal is detected. Adequate margin is provided if the rise occurs
at least one clock cycle before the next fall.
22
Datasheet Title
Write clock gate
Clock gate
cycle
Cycle N - 1
Cycle N
Cycle N + 1
Cycle N + 2
tWCC
WCK
WRS
High
High
WAS
Din
D(N - 2)
D(N - 1)
D(N)
D(N + 1)
D(N + 2)
CGW
WE
tWGS
tWGH
Low
Note: During cycles where CGW is high, the write address pointer is not incremented, and the
DIN data is not written.
Write enable
Cycle N - 1
Cycle N
Cycle N + 2
Cycle N + 3
tWCC
WCK
WRS
High
High
WAS
D(N - 2)
D(N - 1)
tWEH
D(N)
D(N + 2)
D(N + 3)
Low
Din
CGW
WE
tWES
tWES tWEH
Note: Although the write address pointer is incremented on a cycle where WE is high, the DIN
data is not written, and the previous memory data is retained.
23
Datasheet Title
Read Cycle
Read address reset
Cycle N - 1
Cycle N
tRRS
Cycle 0
tRCC
Cycle 1
tRCP
Cycle 2
RCK
RRS
tRC
tRRH
tRAC
tRRS
tOH
RAS
Dout
High
D(N - 2)
D(N - 1)
D(N)
D(0)
D(1)
D(2)
Add'X'
Add'0'
Note: The read address pointer is reset to 0 from the cycle where RRS was low.
Only the falling edge of the RRS signal is detected. Adequate margin is provided if the rise
occurs at least one clock cycle before the next fall.
Read clock gate
Clock gate
cycle
Cycle N - 1
Cycle N
Cycle N + 1
Cycle N + 2
tRCC
RCK
RRS
High
High
tRAC
RAS
tOH
Dout D(N - 2)
D(N - 1)
D(N)
tRGH
D(N + 1)
D(N + 2)
CGR
OE
tRGS
Low
Note: During cycles where CGR is high, the read address pointer is not incremented, and the
output data is retained.
24
Datasheet Title
Output enable
Disable cycle
(N + 1)
Cycle N - 1
Cycle N
Cycle N + 2
Cycle N + 3
tRCC
RCK
RRS
RAS
High
High
tRAC
tOLZ
tOAC
High-Z
Dout
CGR
OE
D(N - 2)
D(N - 1)
D(N)
tOHZ
D(N + 2)
D(N + 3)
Low
Note: During cycles where OE is high, the output goes to the high impedance state, and the
read address pointer is incremented.
Line Reset
Write line increment
tWCC
N - 1
N
0
1
2
WCK
tWLH
tWLS
WLRS
tWLS
tDS
tDH
High
WRS
Din
D(N - 1)
Add(V, H)
D(N)
D(0)
D(1)
Add(V + 1.0)
D(2)
WWND
WCLR
High
High
Note: The line address V is incremented, and the horizontal address H is reset to 0.
25
Datasheet Title
Read line increment
tRCC
N - 1
N
0
1
2
RCK
tRLH
tRLS
tRLS
RLRS
tRAC
D(0)
tOH
High
RRS
Dout
D(N - 1)
Add (V, H)
D(N)
D(1)
Add (V + 1,0)
D(2)
RWND
RCLR
High
High
Note: The line address V is incremented, and the horizontal address H is reset to 0.
Write line hold
tWCC
N - 1
N
0
1
2
WCK
WLRS
WRS
tWLS
tWLH
tWRH
tWLS
tWRS
tWRS
High
tDS
tDH
Din
D(N - 1)
Add(V, H)
D(N)
D(0)
D(1)
Add(V, 0)
D(2)
High
High
WWND
WCLR
Note: The line address V is held as it is, and the horizontal address H is reset to 0.
26
Datasheet Title
Read line hold
tRCC
N - 1
N
0
1
2
RCK
RLRS
RRS
tRLH
tRRH
tRLS
tRLS
tRRS
tRRS
High
D(2)
tRDH
D(N - 1)
Add(V, H)
D(N)
tRAC
D(0)
D(1)
Add(V, 0)
Dout
High
High
RWND
RCLR
Note: The line address V is held as it is, and the horizontal address H is reset to 0.
Jump Address Setup (1 Dimensional Addressing Mode)
Write address setup
Write address setup
Write jump
↓
↓
At least 64 CLK cycles
12
0
1
2
13
63
0
1
WCK
WAS
tWSS
tWAS tWAH
A13
tWSH
A12
A11
Valid
A1
A0
WAD
WRS
Din
Valid
Valid
Valid
Valid
Valid
D(N)
D(0)
D(1)
Add 'WA'
The write jump address WA is (A13 , A12 , ... A0 )
Note: After 64 cycles have passed following the start of write address setup, a jump to the set
address can be performed at any time.
27
Datasheet Title
Read address setup
Read address setup
Read jump
↓
↓
At least 64 CLK cycles
12
0
1
2
13
63
0
1
RCK
RAS
tRSS
tRAH
A13
tRSH
tRAS
A12
A11
A1
A0
RAD
RRS
Dout
Valid
Valid
Valid
Valid
Valid
D(N) D(0) D(1)
Add 'RA'
The read jump address RA is (A13 , A12 , ... A0 )
Note: After 64 cycles have passed following the start of read address setup, a jump to the set
address can be performed at any time.
Read and write address setup can be performed asynchronously.
Jump Address Setup (2 Dimensional Addressing Mode 1)
Write address setup (2 dimensional addressing: 324 line × 1024 dot mode)
Write address setup
Write jump
↓
↓
At least 64 CLK cycles
0
1
0
1
8
9
10
13
63
WCK
WAS
tWSS
Line address V
tWAH
tWSH
Horizontal address H
tWAS
V8
V7
V0
H4
H3
H0
WAD
WRS
Din
D(N)
D(0)
D(1)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Add'W(V, H)'
The write jump address W (V, H) is (V , ... , V0 , H4 , ... , H0 )
8
Note: The jump to the set address can be performed at any time once the required 64 cycles
have passed following the start of write address setup.
28
Datasheet Title
Read address setup (2 dimensional addressing: 324 line × 1024 dot mode)
Read address setup
Read jump
↓
↓
At least 64 CLK cycles
10 13
0
1
0
1
8
9
63
RCK
RAS
tRSH
Horizontal address H
tRSS
Line address V
tRAH
tRAS
V8
V7
V0
H4
H3
H0
RAD
RRS
Dout
Valid Valid
Valid Valid Valid Valid
Valid
D(N) D(0) D(1)
Add 'R(V, H)'
The read jump address R (V, H) is (V8 , ... , V0 , H4 , ... , H0)
Note: The jump to the set address can be performed at any time once the required 64 cycles
have passed following the start of read address setup.
Read and write address setup can be performed asynchronously.
Jump Address Setup (2 Dimensional Addressing Mode 2)
Write address setup (2 dimensional addressing: 288 line × 1152 dot mode)
Write address setup
Write jump
↓
↓
At least 64 CLK cycles
0
1
0
1
8
9
10
14
63
WCK
WAS
tWSH
tWSS
Line address V
tWAH
Horizontal address H
tWAS
V8
V7
V0
H5
H4
H0
WAD
WRS
Din
D(N)
D(0)
D(1)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Add 'W(V, H)'
The write jump address W (V, H) is (V8 , ... , V0 , H5 , ... , H0 )
Note: The jump to the set address can be performed at any time once the required 64 cycles
have passed following the start of write address setup.
29
Datasheet Title
Read address setup (2 dimensional addressing: 288 line × 1152 dot mode)
Read address setup
Read jump
↓
↓
At least 64 CLK cycles
10 14
0
1
0
1
8
9
63
RCK
RAS
tRSH
Horizontal address H
tRSS
Line address V
tRAH
tRAS
V8
V7
V0
H5
H4
H0
RAD
RRS
Dont
Valid Valid
Valid Valid Valid Valid
Valid
D(N) D(0) D(1)
Add'R(V, H)'
The read jump address R (V, H) is (V8 , ... , V0 , H5 , ... , H0 )
Note: The jump to the set address can be performed at any time once the required 64 cycles
have passed following the start of read address setup.
Read and write address setup can be performed asynchronously.
Address input mask
Address setup
Jump
↓
↓
At least 64 CLK cycles
0
1
2
8
9
10
63
0
WCK (RCK)
tWSS(tRSS
)
tWSH(tRSH
)
WAS (RAS)
tWAS(tRAS
)
tWAH(tRAH
)
WAD (RAD)
WRS (RRS)
V8 V7
V6
V0
In this example, only the line address is re-input, and the horizontal address retains its
previously set value.
Note: After the start of read or write jump address setup, if RAS or WAS respectively is returned
to the high level at an arbitrary bit position, the address bits input thereafter are masked,
and the corresponding bits retain their previous values.
30
Datasheet Title
Jump
Write jump
N - 1
N
0
1
2
tWCC
WCK
WRS
WAS
tWRS
tWSS
tWRH
tWSH
tWRS
tWSS
tDS tDH
D(N)
tDS tDH
D(0)
D(N - 2)
D(N - 1)
D(1)
D(2)
Din
Add 'X'
Add 'WA'
Note: WA is the address input in the previous write address setup cycle.
Read jump
N - 1
N
0
1
2
tRCC
RCK
RRS
RAS
tRRS
tRSS
tRRH
tRSH
tRAC
tRRS
tRSS
D(N - 1)
Add 'X'
tOH
D(N)
D0
D1
D2
Dout
Add 'RA'
Note: RA is the address input in the previous read address setup cycle.
31
Datasheet Title
New/Previous Data Access
New data access (address reset)
0
1
2
3
160
161
162
WCK
WE
CGW
WRS
WAS
High
Din
New 0 New 1 New 2
Add '0'
New160 New161 New162
Add '5'
Add '4'
0
1
2
RCK
CGR
RRS
RAS
High
OE
Dout
New 0 New 1 New 2
Add '0'
Note: Written data can be read out 160 WCK clock cycles after it was written.
32
Datasheet Title
Previous data access (address reset)
0
1
2
3
32
33
34
WCK
WE
CGW
WRS
WAS
Din
High
New 0 New 1 New 2
Add '0'
New 32 New 33 New 34
Add '1'
0
1
2
RCK
CGR
RRS
RAS
High
OE
Dout
Previous0 Previous1 Previous2
Add '0'
Note: Previous data can be read out up to 32 WCK clock cycles after the write operation.
33
Datasheet Title
New data access (address jump)
(example where the read and write jump addresses are to the same location)
0
1
2
13
160
161
162
WCK
WE
CGW
WRS
WAS
Din
New 0 New 1
New 160 New 161 New 162
Add 'A + 5'
Add 'A'
Add 'A + 4'
0
1
2
RCK
CGR
RRS
RAS
OE
Dout
New 0 New 1 New 2
Add 'A'
Note: Written data can be read out 160 WCK clock cycles after it was written. However, it is necessary
to execute the read jump address setup operation outside the time period between 32 WCK
cycles before the start of write to that address and 32 WCK cycles after the completion of
write to that address.
34
Datasheet Title
Previous data access (address jump)
(example when the read and write jump addresses are to the same location)
0
1
2
13
32
33
34
WCK
WE
CGW
WRS
WAS
Din
New 0 New 1
New 32 New 33 New 34
Add 'A + 1'
Add 'A'
0
1
2
RCK
CGR
RRS
RAS
OE
Dout
Previous0 Previous1 Previous2
Add 'A'
Note: Previous data can be read out up to 32 WCK clock cycles after the write operation.
35
Datasheet Title
Clear
Write clear
tWCC
N
N + 1
0
1
2
WCK
tWCLH
tWCLS
WCLR
WWND
tDS
tDH
Din
D(N - 1)
D(N)
Add(V, H)
D(N + 1)
D0
D1
Add(0, 0)
D2
WRS
WLRS
WAS
Note: The write address pointer is reset to (0, 0), and window mode is turned off if it was on.
Read clear
tRCC
N
N + 1
0
1
2
RCK
tRCLH
tRCLS
tOH
RCLR
RWND
tRAC
Dout
RRS
D(N - 1)
D(N)
Add(V, H)
D0
D1
Add(0, 0)
D2
D(N + 1)
RLRS
RAS
Note: The read address pointer is reset to (0, 0), and window mode is turned off if it was on.
36
Datasheet Title
Window Scan Function
Combined Window Scan Example
In window scan mode, the destination address of a jump will be the first point in the window region, and
line reset and reset operate as follows.
Line reset: Resets to the left edge of the window on the next line.
Reset: Resets to the first point in the window.
In this mode, addresses are generated automatically internally, so this function is useful in applications that
need to scan a window region.
Also, completely independent window regions can be scanned by the read and write systems.
Representative application examples are presented below.
H (32 bit units)
0
1024(1152)
0
(P, Q)
(M, N)
Window B
(R, S)
V
Window A
(P + p, Q + q)
Window C
(M + m, N + n)
(R + r, S + s)
319
37
Datasheet Title
Case 1: Switching Between Normal and Window A Scan
WWND
(RWND)
Window A
Window A
1st line
2nd line
Normal mode
Mode
Last line in A
Last line
1st line 2nd line
1st line 2nd line
WRS
(RRS)
WAS
(RAS)
WLRS
Jump to
(M, N)
(RLRS)
Jump to
(M, N)
(M, N + 1)
(M, N + n)
Jump to
(0, 0)
(1, 0)
Case 2: Repeatedly Scanning Window A
WWND
(RWND)
Window A
Window A
2nd line
Mode
1st line
Last line in A
2nd line
1st line
WRS
(RRS)
WAS
(RAS)
WLRS
(RLRS)
(M, N + 1)
(M, N + n)
(M, N + 1)
Jump
to (M, N)
Jump
to (M, N)
38
Datasheet Title
Case 3: Switching from Window A Scan to Normal Scan to Window C Scan
WWND
(RWND)
Mode
Normal
Window A
2nd line
Window C
1 st line
1st line
Last line in A
1st line 2nd line
WRS
(RRS)
WAS
(RAS)
WLRS
(RLRS)
WCLR
(RCLR)
(M, N + n)
Jump to
(M, N)
Jump to
(0, (0, 1)0)
New address
setup: (P, Q)
Jump to
(R, S)
New address
setup: (R, S)
(R, S + 1)
Case 4: Switching from Window A Scan to Window B Scan to Window C Scan
WWND
(RWND)
Window A
1st line 2nd line
Window B
1st line
Widnow C
2nd line
Mode
Last line in B 1st line
Last line in A
WRS
(RRS)
WAS
(RAS)
WLRS
(RLRS)
(M, N + n)
Jump to
(M, N)
Jump to (P,Q + 1)
(P, Q)
Jump to (R, S + 1)
(R, S)
(P,Q+q)
New address
setup: (P, Q)
New address
setup: (R, S)
39
Datasheet Title
Window Scan Timing Charts
Window Jump (setup)
• Write
tWCC
0
n
n + 1
1
2
WCK
WRS
tWRH
tWRS
tWSS
tWRS
tWSH
WAS
tWSS
tWWDS
tWWDH
WWND
tWWDS
tDS tDH
tDS tDH
D0
D(N - 1)
D(N)
Add '(X, Y)'
D1
Add '(M, N)'
D2
Din
D(N + 1)
Note: The value (M, N) is the address input during the write address setup cycle.
Window Jump (setup) (cont)
• Read
tRCC
0
1
2
n
n + 1
RCK
RRS
tRRS
tRSS
tRRH
tRRS
tRSH
RAS
tRSS
tRWDS
tRWDH
RWND
tRWDS
tOH
tRAC
D(N + 1)
D(N)
Add '(X, Y)'
D0
D1
D2
Dout
Add '(M, N)'
Note: The value (M, N) is the address input during the read address setup cycle.
40
Datasheet Title
Line Increment (in window mode)
• Write
tWCC
n
n - 1
0
1
2
WCK
tWLH
tDH
tWLS
WLRS
tWLS
tDS
High
D(N-1)
Add(M, N + n)
WRS
Din
D(N)
D(0)
D(1)
Add(M + 1, N)
D(2)
WWND
WCLR
Don't Care
High
Note: The line address M is incremented and the horizontal address currently at N + n is reset to N.
Line Increment (in window mode) (cont)
• Read
0
tRCC
n - 1
n
1
2
WCK
tRLH
tRAC
tRLS
RLRS
tRLS
tROH
High
D(N - 1)
Add(M,N + n)
RRS
Dout
D(N)
D(0)
D(1)
D(2)
Add(M + 1,N)
Don't Care
High
RWND
RCLR
Note: The line address M is incremented and the horizontal address currently at N + n is reset to N.
41
Datasheet Title
Line Hold (in window mode)
• Write
tWCC
n
n - 1
0
1
2
WCK
tWLS
tWLH
tWRH
tWLS
WLRS
WRS
tWRS
tWRS
tDS
tDH
Din
D(N-1)
Add(M, N + n)
D(N)
D(0)
D(1)
Add(M, N)
D(2)
Don't Care
High
WWND
WCLR
Note: The line address M is held at its current value and the horizontal
address currently at N + n is reset to N.
• Read
RCK
tRCC
n - 1
n
0
1
2
tRLH
tRRH
tRLS
RLRS
RRS
Dout
tRLS
tRDH
tRRS
tRRS
D(N - 1)
Add(M, N + n)
D(N)
tRAC
D(0)
D(1)
Add(M, N)
D(2)
Don't Care
High
RWND
RCLR
Note: The line address M is held at its current value and the horizontal
address currently at N + n is reset to N.
42
Datasheet Title
Window Clear
• Write
tWCC
N
N + 1
0
1
2
WCK
WRS
tWRS
tWSS
tWRH
tWSH
tWRS
*1
WAS
tWSS
tWWDH
WWND
tWWDS
tDS tDH
tDS tDH
D0
Din
D1
Add'WA'
D2
D(N - 1)
D(N)
Add'(X,Y)'
D(N+1)
Note: 1. The write address is reset to (0, 0) when WAS is high.
When WAS is low, the write address jumps to WA, and in any case, the write window is cleared.
• Read
tRCC
N
N + 1
0
1
2
RCK
RRS
tRRS
tRSS
tRRH
tRRH
tRRS
RAS
*1
tRSS
tRWDH
tRAC
RWND
tRWDS
tOH
Dout
D(N)
Add '(X, Y)'
D(N + 1)
D0
D1
D2
Add 'RA'
Note: 1. The read address is reset to (0, 0) when RAS is high.
When RAS is low, the read address jumps to RA, and in any case, the read window is cleared.
43
Datasheet Title
Clear
• Write clear
tWCC
N
N + 1
0
1
2
WCK
tWCLH
tWCLS
tWCLS
WCLR
WWND
tDS
tDH
D(N - 1)
D(N)
Add(V, H)
D(N+1)
D0
D1
Add(0, 0)
D2
Din
WRS
WLRS
WAS
Note: The write address pointer is reset to (0, 0), and window mode is turned off if it was on.
• Read clear
RCK
tRCC
N
N + 1
0
1
2
tRCLH
tRCLS
tRCLS
tOH
RCLR
RWND
tRAC
D0
D(N - 1)
D(N)
Add(V, H)
D(N + 1)
D1
Add(0, 0)
D2
Dout
RRS
RLRS
RAS
Note: The read address pointer is reset to (0, 0), and window mode is turned off if it was on.
44
Datasheet Title
Reset to the Window Origin
These figures show the timing charts for resetting the address pointer to the window origin address (M, N)
during window scan mode execution
• Write
tWCC
n
0
1
2
n + 1
WCK
WRS
WAS
tWRS
tWRH
tWRS
High
tWWDS
tWWDH
WWND
Din
tWWDS
tDS tDH
D(N+1)
tDS tDH
D0
D(N - 1)
D(N)
Add '(M + m, N + n)'
D1
Add '(M, N)'
D2
Note: The write address pointer is reset to the window origin address (M, N).
• Read
tRCC
n
n + 1
0
1
2
RCK
RRS
RAS
tRRS
tRRH
tRRS
High
tRWDS
tRWDH
tRAC
RWND
Dout
tRWDS
tOH
D(N)
Add '(M + m, N + n)'
Note: The read address pointer is reset to the window origin address (M, N).
D(N + 1)
D0
D1
D2
Add '(M, N)'
45
Datasheet Title
Package Dimensions
HM530281RTT Series (TTP-44DB)
Unit: mm
18.41
18.81 Max
44
23
22
1
0.80
M
0.21
0.30 ± 0.10
1.005 Max
11.76 ± 0.20
0 – 5°
0.80
0.10
0.50 ± 0.10
46
Datasheet Title
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
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Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Electronic Components Group
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Northern Europe Headquarters
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47
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