HM53461JP-10 [HITACHI]
Video DRAM, 64KX4, 100ns, CMOS, PDSO24, PLASTIC, SOJ-24;
| 型号： | HM53461JP-10 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Video DRAM, 64KX4, 100ns, CMOS, PDSO24, PLASTIC, SOJ-24 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总37页 (文件大小：5882K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM53461 Series, HM53462 Series
×
65,536-word 4-bit Multiport CMOS Video RAM
The HM53461/HM53462 is a 262,144-bit
• Data transfer operation (between RAM and
SAM)
multiport memory equipped with a 64 k-word 4-
×
bit dynamic RAM port and a 256-word 4-bit
serial access memory (SAM) port. The SAM port
is connected to an internal 1,024-bit data register
×
• Fast serial access operation asynchronized with
RAM port (except data transfer cycle)
• Real time read transfer capability
• Write mask mode capability
through a 256-word 4-bit serial read or write
×
access control. In the read transfer cycle, the
memory cell data is transferred from a selected
word line of the RAM port to the data register. The
RAM port has a write mask capability in addition
to the conventional operation mode. Write bit
selection out of four data bits can be achieved. The
Hitachi 2 µm CMOS process achieves a fast serial
access operation and low power dissipation. All
inputs and outputs, including clocks, are TTL
compatible. In HM53462, the RAM port has logic
operation capability. By using this function, logic
operation between memory data and input data can
be done in one cycle.
• Logic operation capability between Din and
Dout (HM53462 Series)
• SAM organization can be changed to 1024
(HM53462 Series)
1
×
Ordering Information
Access
Time
Type No.
Package
HM53461P-10
HM53461P-12
HM53461P-15
HM53461ZP-10
HM53461ZP-12
HM53461ZP-15
HM53461JP-10
HM53461JP-12
HM53461JP-15
HM53462P-10
HM53462P-12
HM53462P-15
HM53462ZP-10
HM53462ZP-12
HM53462ZP-15
HM53462JP-10
HM53462JP-12
HM53462JP-15
100 ns
120 ns
150 ns
100 ns
120 ns
150 ns
100 ns
120 ns
150 ns
100 ns
120 ns
150 ns
100 ns
120 ns
150 ns
100 ns
120 ns
150 ns
400-mil, 24-pin
plastic DIP
(DP-24A)
Features
24-pin
plastic ZIP
(ZP-24)
• Multiport organization
(RAM; 64 k-word 4-bit and SAM;
×
256 word 4-bit)
×
• Double layer polysilicon/polycide n-well CMOS
process
• Single 5 V (±10%)
• Low power
— Active: RAM: 380 mW max
SAM: 220 mW max
— Standby: 40 mW max.
• Access Time
— RAM: 100 ns/120 ns/150 ns
— SAM: 40 ns/40 ns/60 ns
• Cycle time
— Random read or write cycle time (RAM):
190 ns/220 ns/260 ns
— Serial read or write cycle time (SAM):
40 ns/40 ns/60 ns
24-pin
plastic SOJ
(CP-24D)
400-mil, 24-pin
plastic DIP
(DP-24A)
28-pin
plastic ZIP
(ZP-24)
• TTL compatible
• 256 refresh cycles: 4 ms
• Refresh function
300-mil, 24-pin
plastic SOJ
(CP-24D)
—
—
-only refresh
-before-
RAS
RAS
CAS
refresh
— Hidden refresh
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Pin Arrangement
Pin Description
HM53461ZP Series
HM53462ZP Series
Pin Name
A0–A7
I/O1–I/O4
SI/O1–SI/O4
RAS
Function
1
3
5
7
9
I/O3
I/O4
SI/O3
VSS
2
4
6
8
Address inputs
SOE
SI/O4
SC
RAM port data input/output
SAM port data input/output
Row address strobe
Column address strobe
Serial clock
SI/O1
SI/O2
DT/OE 10
I/O2 12
RAS 14
A5 16
11 I/O1
13 WE
15 A6
17 A4
19 A7
21 A2
23 A0
CAS
VCC 18
A3 20
SC
A1 22
Write enable
WE
CAS 24
/
Data transfer/output enable
SAM port enable
DT OE
(Bottom view)
SOE
VCC
VSS
HM53461P/JP Series
HM53462P/JP Series
Power supply
Ground
SC
SI/O1
SI/O2
DT, OE
I/O1
I/O2
WE
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
VSS
SI/O4
SI/O3
SOE
I/O4
I/O3
CAS
A0
A1
A2
A3
A7
RAS
A6
A5
A4
VCC
9
10
11
12
(Top view)
2
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Block Diagram
HM53461 Series
I/O1
I/O2
I/O3
I/O4
Write mask
control
OE clock
generator
I/O buffer I/O buffer I/O buffer I/O buffer
DT/OE
WE
WE clock
generator
Y decoder Y decoder Y decoder Y decoder
Transfer
control
64 k
memory
array
64 k
memory
array
64 k
memory
array
64 k
memory
array
CAS
CAS clock
generator
SOE
SOE clock
generator
RAS
Ai
RAS clock
generator
256 data 256 data 256 data 256 data
SC
register
register
register
register
SC clock
generator
Pointer
Pointer
Pointer
Pointer
X address
buffer
SI/O buffer SI/O buffer SI/O buffer SI/O buffer
Y address
buffer
SI/O1
SI/O2
SI/O3
SI/O4
Refresh
address
counter
VBB generator
RAS CAS
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Block Diagram (cont)
HM53462 Series
4
3
2
Dout
1
Dout
SC
Data
transfer
control
Memory array
4
3
256 × 256
2
Din
Din
1
SI/O1
S
4
By-1 Mode
(1024 × 4)
Other SI/O
(2–4) are in
high-Z state
DT
P
WE
3
2
SI/O1
By-4 Mode 256 × 4
(Normal Mode)
Absolute Maximum Ratings
•
•
•
•
•
•
Voltage on any pin relative to V
Power supply voltage relative to V
Operating temperature, Ta (Ambient): 0°C to +70°C
Storage temperature:
Short circuit output current:
Power dissipation:
:
–1 V to +7 V
–0.5 V to +7 V
SS
:
SS
–55°C to +125°C
50 mA
1 W
*1
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
4.5
Typ
5.0
—
Max
5.5
Unit
V
V
V
Supply voltage
Input high voltage
VIH
2.2
6.0
Input low voltage
VIL
–0.5 *2
—
0.8
Notes: 1. All voltages refernced to VSS
.
2. –3.0 V for pulse wideth ≤ 10 ns.
4
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
SAM port
———————– HM53461-10 HM53461-12 HM53461-15
Symbol Standby Active HM53462-10 HM53462-12 HM53462-15 Unit
RAM port
ICC1
O
X
70
60
50
mA
Operating current
RAS,
cycling tRC = min.
CAS
ICC7
ICC2
ICC8
ICC3
X
O
X
110
7
100
7
80
7
mA
mA
O
Standby current
,
RAS
= VIH
CAS
X
O
X
40
60
40
50
30
40
mA
mA
O
only refresh
RAS
,
current,
= VIH RAS
CAS
cycling, tRC = min.
ICC9
ICC4
X
O
X
100
50
90
40
70
35
mA
mA
O
Page mode current
RAS
,
= VIL CAS cycling, tPC
min.
=
ICC10
ICC5
ICC11
ICC6
X
O
X
90
60
80
50
65
40
mA
mA
O
CBR refresh current
cycling tRC = min.
RAS
X
O
X
O
X
100
75
90
70
55
85
mA
mA
mA
65
Data transfer current
,
cycling tRC =
RAS CAS
ICC12
O
115
105
min.
Parameter
Symbol
Min
–10
–10
2.4
—
Max
10
Unit
µA
µA
V
Input leakage
ILI
Output leakage
ILO
VOH
VOL
10
Output high voltage IOH = –2 mA
Output low voltage IOL= 4.2 mA
—
0.4
V
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Input/Output Capacitance
Parameter
Address
Clocks
Symbol
CI1
Typ
—
Max
Unit
pF
5
5
7
CI2
—
pF
I/O, SI/O
C
—
pF
I/O
Electrical Characteristics and Recommended AC Operating Conditions (Ta = 0 to
*1, 10, 11
+70°C, V = 5 V ± 10%, V = 0 V)
CC
SS
HM53461-10
HM53462-10
——————
HM53461-12
HM53462-12
——————
Min Max
HM53461-15
HM53462-15
——————
Parameter
Symbol
Min
Max
Min
Max
Unit Note
Random read or
write cycle time
tRC
190
—
220
260
—
ns
Read-modify-write
cycle time
tRWC
260
—
300
—
355
—
ns
Page mode cycle time
tPC
70
—
—
—
—
85
—
—
—
—
105
—
—
ns
Access time from
Access time from
tRAC
tCAC
tOFF1
100
50
25
120
60
30
150
75
40
ns 2, 3
ns 3, 4
RAS
CAS
—
Output buffer turn off
delay referenced to
—
ns
5
6
CAS
Transition time (rise and fall) tT
3
50
3
50
—
3
50
ns
ns
ns
ns
ns
ns
ns
ns
precharge time
pulse width
tRP
80
100
50
25
50
100
10
—
90
100
150
75
—
RAS
RAS
CAS
tRAS
tCAS
tRCD
tRSH
tCSH
tCRP
10000
10000
50
120 10000
10000
10000
75
pulse width
60
25
60
120
10
10000
60
to
RAS CAS
delay time
30
7
hold time
hold time
—
—
75
—
RAS
CAS
—
—
150
10
—
to
—
—
—
CAS RAS
precharge time
6
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Electrical Characteristics and Recommended AC Operating Conditions (Ta = 0 to
*1, 10, 11
+70°C, VCC = 5 V ± 10%, VSS = 0 V)
(cont)
HM53461-10
HM53462-10
——————
HM53461-12
HM53462-12
——————
Min Max
HM53461-15
HM53462-15
——————
Parameter
Symbol
tASR
Min
Max
Min
Max
Unit Note
Row address setup time
Row address hold time
0
—
0
—
—
—
—
—
—
—
—
0
—
ns
ns
ns
ns
tRAH
15
0
—
15
0
20
0
—
Column address setup time tASC
Column address hold time tCAH
Write command setup time tWCS
—
20
0
—
—
—
—
—
20
0
25
0
—
—
ns
ns
ns
ns
8
Write command hold time
tWCH
25
15
35
25
20
40
30
25
45
—
Write command pulse width tWP
—
Write command to
lead time
tRWL
—
RAS
Write command to
lead time
tCWL
35
—
40
—
45
—
ns
ns
CAS
Data-in setup time
Data-in hold time
tDS
tDH
0
—
—
—
—
—
0
—
—
—
—
—
0
—
—
—
—
—
9
25
0
25
0
30
0
ns 8, 9
Read command setup time tRCS
ns
ns
ns
Read command hold time
tRCH
tRRH
0
0
0
Read command hold time
10
10
10
referenced to
RAS
Refresh period
tREF
—
4
—
4
—
4
ns
ns
pulse width
RAS
(read-modify-write cycle)
tRWS
170
10000
200 10000
245
10000
to
CAS WE
delay
tCWD
tCSR
85
10
—
—
100
10
—
—
125
10
—
—
ns
ns
8
setup time
CAS
(
-before-
RAS
refresh)
refresh)
CAS
hold time
tCHR
20
—
25
—
30
—
ns
CAS
(
-before-
RAS
CAS
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Electrical Characteristics and Recommended AC Operating Conditions (Ta = 0 to
*1, 10, 11
+70°C, VCC = 5 V ± 10%, VSS = 0 V)
(cont)
HM53461-10
HM53462-10
——————
HM53461-12
HM53462-12
——————
Min Max
HM53461-15
HM53462-15
——————
Parameter
Symbol
Min
Max
Min
Max
Unit Note
precharge to
hold time
tRPC
10
—
10
—
10
—
ns
RAS
CAS
precharge time
tCP
10
—
—
—
30
25
15
—
—
—
35
30
20
—
—
—
40
40
ns
ns
ns
CAS
Access time from
tOAC
tOFF2
OE
Output buffer turn-off
delay referenced to
OE
to data-in delay time
tODD
tOEH
25
10
—
—
30
15
—
—
40
20
—
—
ns
ns
OE
OE
hold time referenced
WE
to
Data-in to
Data-in to
delay time
tDZC
tDZO
tORD
tSCC
tSCA
0
—
—
—
—
40
25
—
—
—
0
—
—
—
—
40
30
—
—
—
0
—
—
—
—
60
40
—
—
—
ns
CAS
delay time
0
0
0
ns
OE
delay time
to
OE RAS
35
40
—
—
10
10
10
40
40
—
—
10
10
10
45
60
—
—
10
10
10
ns
Serial clock cycle time
Access time from SC
ns
ns 10
ns 10
ns
t
Access time from
SC pulse width
SOE
SEA
tSC
SC precharge width
tSCP
tSOH
ns
Serial data-out hold
time after SC high
ns
Serial output buffer turn
tSEZ
—
25
—
25
—
30
ns
off delay from
SOE
Serial data-in setup time
Serial data-in hold time
tSIS
0
—
—
—
—
0
—
—
—
—
0
—
—
—
—
ns
ns
ns
ns
tSIH
tDTS
tRDH
15
0
20
0
25
0
to
DT RAS
setup tune
to
DT RAS
hold time
(read transfer cycle)
80
90
110
8
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Electrical Characteristics and Recommended AC Operating Conditions (Ta = 0 to
*1, 10, 11
+70°C, VCC = 5 V ± 10%, VSS = 0 V)
(cont)
HM53461-10
HM53462-10
——————
HM53461-12
HM53462-12
——————
Min Max
HM53461-15
HM53462-15
——————
Parameter
Symbol
tDTH
tCDH
tSDD
tSDH
tDTR
tWS
Min
15
20
5
Max
—
—
—
—
—
—
—
—
—
50
Min
20
45
10
30
10
0
Max
—
—
—
—
—
—
—
—
—
75
Unit Note
to
DT RAS
hold time
hold time
15
30
5
—
—
—
—
—
—
—
—
—
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
to
DT CAS
Last SC to
First SC to
delay time
DT
DT
hold time
25
10
0
25
10
0
to
DT RAS
delay time
setup time
hold time
setup time
hold time
to
WE RAS
to
WE RAS
tWH
15
0
15
0
20
0
I/O to
I/O to
tMS
RAS
RAS
tMH
15
10
15
10
20
10
Serial output buffer turn
off delay from
tSRZ
RAS
SC to
setup time
tSRS
tSRD
tSID
30
25
50
—
—
—
40
30
60
—
—
—
45
35
75
—
—
—
ns
ns
ns
RAS
to SC delay time
RAS
Serial data input delay
time from
RAS
Serial data input to
delay time
tSZD
0
—
0
—
0
—
ns
DT
to
SOE RAS
setup time
hold time
tES
0
—
—
—
0
—
—
—
0
—
—
—
ns
ns
ns
to
SOE RAS
tEH
15
0
15
0
20
0
Serial write enable
setup time
tSWS
Serial write enable
hold time
tSWH
35
0
—
—
35
0
—
—
55
0
—
—
ns
ns
Serial write disable
setup time
tSWIS
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Electrical Characteristics and Recommended AC Operating Conditions (Ta = 0 to
*1, 10, 11
+70°C, VCC = 5 V ± 10%, VSS = 0 V)
(cont)
HM53461-10
HM53462-10
——————
HM53461-12
HM53462-12
——————
Min Max
HM53461-15
HM53462-15
——————
Parameter
Symbol
Min
Max
Min
Max
Unit Note
Serial write disable
hold time
tSWIH
35
—
35
10
—
—
55
—
ns
to Sout in low-Z
DT
delay time
tDLZ
5
—
10
—
ns
Notes: 1. AC measurements assume tT = 5 ns.
2. Assumes that tRCD ≤ tRCD (max). If tRCD is greater than the maximum recommended value
shown in this table, tRAC exceeds the value shown.
3. Measured with a load circuit equivalent to two TTL loads and 100 pF.
4. Assumes that tRCD ≥ tRCD (max).
5.
tOFF (max) defines the time at which the output achieves the open circuit condition and is not
referenced to output voltage levels.
6. VIH(min) and VIL(max) are reference levels for measuring the timing of input signals. Also,
transition times are measured between VIH and VIL.
7. Operation with the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified
as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time
is controlled exclusively by tCAC
.
8.
tWCS and tCWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only if tWCS ≥ tWCS (min), the cycle is an early write cycle, and the data
out pin will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD
(min), the cycle is a read/write and the data output will contain data read from the selected cell.
If neither of the above sets of conditions is satisfied, the condition of the data out (at access
time) is indeterminate.
9. These parameters are referenced to
leading edge in early write cycle and to
leading
WE
CAS
edge in delayed write or read-modify-write cycles.
10. Measured with a load circuit equivalent to two TTL and 50 pF.
11. An initial pause of 100 µs is required after power-up. Then execute at least eight initialization
cycles (HM53461 Series). After power-up, pause for more than 100 µs and execute at least 8
initialization cycles. Then execute at least one logic reset cycle including write mask reset (on
the falling edge of
,
low and I/O1–I/O4 = high and execute one or more transport
RAS WE
=
cycles for initiation of the SAM port (HM53462 Series).
12. After a read transfer cycle, the first SAM must be read out before the
falling edge in the
CAS
succeeding read transfer cycle. When SAM is not read out after a read transfer cycle or when
SAM read out is not used as valid data, the restriction mentioned above is not required.
10
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Timing Waveforms
Read Cycle
tRC
tRAS
tRCD
RAS
tRP
tRSH
tCRP
tCSH
tCAS
tCAH
Column
CAS
tASR tRAH
tASC
Row
Address
tRRH
tRCH
tRCS
tCAC
WE
tRAC
tOFF1
Valid Dout
tORD
I/O (output)
tOAC
tDZC
I/O (input)
DT/OE
tDZO
tOFF2
tDTS
tDTH
Do not care
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Early Write Cycle
tRC
tRAS
tRCD
RAS
CAS
tRP
tRSH
tCRP
tCSH
tCAS
tCAH
tASR
tRAH
tASC
Row
tWH
Column
tWCS tWCH
tWP
Address
WE
tWS
*
tMS
tMH
tDS
Valid Din
High Z
tDH
*
I/O (input)
I/O (output)
tDTS
tDTH
DT/OE
Do not care
Note: When WE is high, all the data on the I/O can be written into the cell.
When WE is low, the data on the I/O are not written except when I/O is high
at the falling edge of RAS.
12
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Delayed Write Cycle
tRC
tRAS
RAS
tRP
tCRP
tRSH
tCAS
tRCD
CAS
tCSH
tASC
tASR
Address
Row
Column
tCAH
tWCH
tWP
tRAH
tWS
Note
WE
tRWL
tCWL
tDTS
tWH
tOEH
DT/OE
tMH
tDS
tDH
tMS
I/O (input)
Note
Valid Din
High-Z
I/O (output)
Do not care
Note: When WE is high, all the data on I/O1–I/O4 can be written into the memory cell. When WE is
low, the data on I/Os are not written except when I/O = high at the falling edge of RAS.
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Read Modify Write Cycle
tRWC
tRWS
tRP
RAS
tCRP
CAS
tCSH
tCAS
tCRP
tRCD
tRSH
tASR tRAH
tASC
Column
tRCS
tCAH
Row
Address
tCWL
tWS
tRWL
tWP
tWH
tCWD
Note
WE
tMH
tDZC
tDH
tMS
tDS
Valid
Din
I/O (output)
Note
tCAC
tODD
Valid
Dout
tRAC
tDZO
I/O (input)
DT/OE
tOEH
tOAC
tDTS
tDTH
tOFF2
Do not care
Note: When WE is high, all the data on I/O1–I/O4 can be written into the memory cell. When WE is
low, the data on I/Os are not written except when I/O = high at the falling edge of RAS.
14
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Page Mode Read Cycle
tRC
tRAS
RAS
tRP
tCSH
tCAS
tPC
tRSH
tCRP
tRCD
tCAS
tCAS
CAS
tCP
tASC
tRAH
tASC
tASC
tASR
tCAH
tCAH
tCAH
Col-
umn
Col-
Col-
umn
Address
WE
Row
umn
tRCH
tRRH
tRCH
tRCS
tRCS
tRCS
tRCH
tRAC
tOFF1
tCAC
tCAC
tOFF1
tCAC
tOFF1
I/O
(output)
Valid
Dout
Valid
Dout
Valid Dout
tDZC
tDZC
tDZC
I/O
tDZO
tDTS tDTH
(input)
tDZO tOFF2
tOAC
tOFF2
tOFF2
tDZO
tOAC
tOAC
DT/OE
Do not care
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Page Mode Write Cycle (Early Write)
tRC
RAS
tRAS
tRP
tCRP
tCSH
tPC
tRSH
tRCD
tCAS
tCAS
tCAS
CAS
tCP
tASC
Col-
tRAH
tASC
tASC
tASR
tCAH
tCAH
tCAH
Col-
Col-
umn
Address
WE
Row
tWS tWH
umn
umn
tWCS
tWCS
tWCS
tWCH
tWCH
tWCH
tWP
Note
tWP
tDH
tWP
tDH
tMS
tDS
tDH
tMH
tDS
tDS
I/O
(output)
Valid
Din
Valid
Din
Valid
Din
Note
High-Z
I/O
(input)
tDTS
tDTH
DT/OE
Do not care
Note: When WE is high, all the data on I/O1–I/O4 can be written into the memory cell. When WE is
low, the data on I/Os are not written except when I/O = high at the falling edge of RAS.
16
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Page Mode Write Cycle (Delayed Write)
tRC
tRAS
RAS
tRP
tCSH
tCAS
tRSH
tPC
tRCD
tRAH
tCRP
tCAS
tCAS
CAS
tCP
tCAH
tASC
tASC
tASH
tCAH
tASC
tCAH
Col-
umn
tWH
Col-
umn
Address
Row
tCWL
tCWL
tCWL
tWP
tRWL
Column
tWS
tWP
tWP
Note
WE
tMS
tDS
tDS
tDS
tDH
tDH
tMH
tDH
I/O
(input)
Note
Valid
Din
Valid
Din
Valid
Din
High-Z
I/O
tDTS
(output)
tOEH
DT/OE
Do not care
Note: When WE is high, all the data on I/O1–I/O4 can be written into the memory cell. When WE is
low, the data on I/Os are not written except when I/O = high at the falling edge of RAS.
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
RAS-Only Refresh Cycle
tRC
tRAS
RAS
tCRP
CAS
tRP
tRPC
tRAH
Row
tOFF1
tASR
Address
I/O
(output)
I/O
(input)
tDTS
tDTH
DT/OE
Do not care
18
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
CAS-Before-RAS Refresh Cycle (HM53461 Series)
tRC
tRP
tRP
tRAS
RAS
tCRP
tRPC
tCSR
tCHR
CAS
Address
WE
I/O
(input)
I/O
High-Z
(output)
DT/OE
Do not care
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
CAS-Before-RAS Refresh (HM53462 Series)
tRC
tRP
tRAS
tRP
RAS
tRPC tCSR
tCRP
tCHR
CAS
Address
tWS
tWH
WE
I/O
(input)
I/O
High-Z
(output)
DT/OE
Do not care
20
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Hidden Refresh Cycle (HM53461 Series)
tRC
tRC
RAS
tRAS
tRAS
tRP
tRP
tCRP
tCRP
tRCD
tRSH
tCHR
tRAH
tASC
CAS
tASR
Row
tCAH
Address
Column
tRCS
tRRH
WE
tORD
tOFF1
I/O
(output)
Valid Dout
tRAC
tCAC
tOAC
tDTS
tOFF2
tDTH
DT/OE
tDZO
tDZC
High-Z
I/O
(input)
Do not care
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Hidden Refresh Cycle (HM53462 Series)
tRC
tRC
RAS
tRAS
tRAS
tRP
tRP
tCRP
tCRP
tRCD
tRSH
tCHR
tRAH
tASC
CAS
tASR
Row
tCAH
Address
Column
tRSC
tWS
tRRH
tWH
WE
tORD
tOFF1
I/O
(output)
Valid Dout
tRAC
tCAC
tOAC
tDTS
tDTH
tOFF2
DT/OE
tDZO
tDZC
High-Z
I/O
(input)
Do not care
22
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
*1, 2
Read Transfer Cycle (1)
tRC
tRAS
RAS
tRP
tCRP
tRCD
tRSH
tCAS
*3
CAS
Address
WE
tRAH
tASC
tASR
tCAH
SAM start
add
Row
tCSH
tWH
tWS
tDTR
High-Z
tCDH
I/O
(output)
I/O
(input)
tDTH
tDTS
tRDH
DT/OE
SC
tSDH
tSCC
tSCP
tSDD
tSC
tSOH
SI/O
(output)
Valid
Sout
Valid
Sout
Valid
Sout
Valid
Sout
tSCA
Previous row
High-Z
New row
SI/O
(input)
Do not care
Notes: 1. In the case that the previous data transfer cycle was read transfer.
2. Assume that SOE is low.
3. CAS and SAM start address need not be supplied every cycle, only when it is desired
to change to a new SAM start address.
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
*1, 2
Read Transfer Cycle (2)
tRC
tRAS
RAS
tRP
tCRP
tRCD
tRSH
tCAS
CAS
Address
WE
*3
tASC
tRAH
tASR
tCAH
SAM start
add
Row
tCSH
tWH
tWS
tDTR
High-Z
tCDH
I/O
(output)
I/O
(input)
tDTH
tDTS
tRDH
DT/OE
SC
tSDH
tSC
tSCC
tSCA
tSRS
tSCP
tDLZ
tSOH
tSC
SI/O
Valid
Sout
(output)
tSIH
tSIS
tSZD
SI/O
(input)
Valid
Sin
Do not care
Inhibit rising
transient
Notes: 1. In the case that the previous data transfer cycle was write transfer or pseudo transfer.
2. Assume that SOE is low.
3. CAS and SAM start address need not be supplied every cycle, only when it is desired
to change to a new SAM start address.
24
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Psuedo Transfer Cycle
tRC
tRAS
tRP
RAS
tCRP
tRCD
tRSH
tCAS
CAS
* tASC
tRAH
tASR
tCAH
SAM start
Address
Row
add
tCSH
tWS
tWH
WE
tDTS
tDTH
DT/OE
SOE
SC
tEH
tES
tSRD
tSCP
tSCC
tSC
tSC
tSIH
tSID
tSRS
tSIS
SI/O
Valid Sin
(input)
tSRZ
tSOH
SI/O
(output)
Do not care
Inhibit rising
transient
Note: CAS and SAM start address need not be supplied every cycle, only when it is desired
to change to a new SAM start address.
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Write Transfer Cycle
tRC
tRAS
RAS
tRP
tCRP
tRCD
tASC
tRSH
tCAS
CAS
*
tRAH
tASR
tCAH
SAM start
Address
Row
add
tCSH
tWS
tWH
tDTH
tEH
WE
tDTS
DT/OE
tES
SOE
SC
tSRS
tSRD
tSCP
tSCC
tSC
tSIH
tSIS
tSC
tSIH
tSIS
SI/O
(input)
Valid
Valid Sin
Sin
Valid
Sin
High-Z
SI/O
(output)
Do not care
Inhibit rising
transient
Note: CAS and SAM start address need not be supplied every cycle, only when it is desired
to change to a new SAM start address.
26
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Serial Read Cycle
tRAS
tDTH
RAS
tDTS
DT/OE
SOE
tSCC
tSC
tSCC
tSCC
tSC
tSC
SC
tSOH
tSCP
tSCP
tSCP
tSEA
SI/O
(output)
Valid
Sout
Valid
Sout
Valid
Sout
tSEZ
tSCA
tSCA
tSCA
Do not care
Serial Write Cycle
tRAS
tDTH
RAS
tDTS
DT/OE
SOE
tSWIS
tSWH
tSCC
tSWIH
tSWS
tSCC
tSCC
tSCP
tSCP
tSCP
SC
tSC
tSC
tSC
tSC
SI/O
(output)
Valid
Sout
Valid
Sout
tSIS
tSIH
tSIS
tSIH
Do not care
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
AC Characteristics (Logic operation mode) (HM53462 Series)
Parameter
Symbol
tFRC
Min
230
140
80
Max
Min
Max
—
Min
310
200
105
200
105
135
120
Max
—
Unit
ns
Write cycle time
—
265
pulse width in write cycle
tRFS
10000 165
10000 95
10000
10000
—
10000
10000
ns
RAS
CAS
CAS
RAS
pulse width in write cycle
hold time in write cycle
hold time in write cycle
tCFS
ns
tFCSH
tFRSH
tFPC
140
80
—
—
—
—
165
95
ns
—
—
—
—
ns
Page mode cycle time (write cycle)
hold time
100
90
120
100
—
ns
tFCHR
—
ns
CAS
(Logic operation set/reset cycle)
hold time from precharge
tPSCH
10
—
10
—
10
—
ns
CAS
(X4 to X1 set cycle)
RAS
Logic Code (FC0–FC3 are Ax0–Ax3 in Logic Operation Set Cycle) (HM53462 Series)
Logic
———————————–
FC3
0
FC2
0
FC1
0
FC0
0
Symbol
Write Data
Description
—
—
—
0
Zero
0
0
0
1
AND1
AND2
Di Mi
·
0
0
1
0
Mi
Di·
0
0
0
1
1
0
1
0
X4 to X1
AND3
—
×
SAM organization changes to 1024
—
1
Di
·Mi
Logic operation mode reset
—
0
0
1
1
0
1
1
0
THROUGH
EOR
Di
Mi + Di
Di·
·Mi
0
1
1
1
0
0
1
0
0
1
0
1
OR1
Di + Mi
—
—
—
NOR
ENOR
Di·Mi
Di Mi +
·
Di·Mi
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
INV1
OR2
INV2
OR3
NAND
1
—
Di
+ Mi
—
Di
—
Mi
Di +
—
Mi
+
Di = External data-in
Di Mi
ONE
Mi = The data of the memory cell
28
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Logic Operation Set/Reset Cycle (with
before
refresh) (HM53462 Series)
CAS
RAS
tRP
tRC
tRAS
tRPC
RAS
tRP
tCSR
tCRP
tPSCH
tFCHR
CAS
tASR
tRAH
Address
*1
tWS
tWH
WE
tDS
tDH
I/O
(input)
*2
High-Z
I/O
(output)
DT/OE
Do not care
Notes: 1. Logic code A0–A3 (A4–A7: don't care)
2. Write mask data
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Logic Operation Mode
Early Write Cycle (HM53462 Series)
tFRC
tRFS
tRCD
RAS
tRP
tFRSH
tCRP
tFCSH
CAS
tCFS
tASR
tRAH
Row
tASC
tCAH
Column
tWCS tWCH
tWP
Address
WE
tWS
tWH
*
*
tMS
tMH
tDS
Valid Din
High-Z
tDH
I/O (input)
I/O (output)
tDTS
tDTH
DT/OE
Do not care
Note: When WE is high, all data on the I/O can be written into the cell. When WE is low,
the data on the I/O are not written except when I/O is high at the falling edge of RAS.
30
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Delayed Write Cycle (HM53462 Series)
tFRC
tRFS
RAS
tRP
tCRP
tRCD
tFRSH
tCFS
CAS
tFCSH
tASR
tASC
Address
Row
Column
tCAH
tWS
tRAH
tWCH
tWP
*
WE
tRWL
tCWL
tWH
tDTS
DT/OE
tOEH
tMH
tDS
tDH
Valid Din
High-Z
tMS
I/O (input)
*
I/O (output)
Do not care
Note: When WE is high, all data on I/O1–I/O4 can be written into the memory cell. When WE is low,
the data on the I/O are not written except when I/O is high at the falling edge of RAS.
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Page Mode Write Cycle (Delayed Write) (HM53462 Series)
tFRC
tRFS
RAS
tRP
tFPC
tFRSH
tFCSH
tRCD
tRAH
tCFS
tCRP
tCFS
tCFS
CAS
tCP
tASC
tASC
tASR
tASC
Col-
tCAH
tCAH
tCAH
Row
Address
umn
tCWL
tWP
tCWL
tCWL
tWP
Column
Column
tRWL
tWH
tWS
tWP
*
WE
tMS
tDS
tDS
tDS
tDH
tDH
tMH
tDH
I/O
(input)
*
Valid Din
Valid Din
Valid Din
tOEH
High-Z
I/O
tDTS
(output)
DT/OE
Do not care
Note: When WE is high all data on the I/O can be written into the cell. When WE is low, the data on
the I/O are not written except when I/O is high at the falling edge of RAS.
32
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Page Mode Write Cycle (Early Write) (HM53462 Series)
tFRC
tRFS
RAS
tRP
tFCSH
tFPC
tFRSH
tCFS
tCRP
tRCD
tCFS
tCFS
CAS
tRAH
tASR
tCP
tASC
tASR
tASC
tCAH
tCAH
tCAH
Address
WE
Row Column
tWH
Column
tWCH
tWCS
tWCS
tWS
tWCS
tWCH
tWP
tWCH
*
tWP
tWP
tDH
tMS
tDS
tMH
tDH
tDS
tDH
tDS
I/O
(output)
Valid
Din
Valid
Din
Valid
Din
*
High-Z
I/O
(input)
tDTS
tDTH
DT/OE
Do not care
Note: When WE is high, all data on the I/O can be written into the cell. When WE is low, the data on
the I/O are not written except when I/O is high at the falling edge of RAS.
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Logic Code: The logic code is shown in the
following logic code table. When power is turned
on, at least one logic reset cycle including write
mask reset is required to initialize logic code. If the
HM53462 Series Description
Logic Operation Mode
logic code is (A 3, A 2, A 1, A 0) = (0, 0,
1, 1), the SAM organization is changed converter
(figure 2). In the case that the SAM organization is
×
×
×
×
HM53462 has an internal logic operation unit
which makes a process of graphics simple. The
logic is determined in the logic operation set/reset
cycle, and the operation is executed in every write
cycle succeeding to the logic operation set/reset
cycle. In this mode the internal read-modify-write
operation is executed and the cell data is converted
into the new data given by the logic operation
between Din and the old cell data.
changed to 1,024 1, one data transfer cycle is
×
needed to initialize the SAM selector.
Once the SAM organization is changed to 1024
1, this code is maintained unless power is turned
×
off.
Write Mask: HM53462 has two kinds of mask
registers (register 1, 2). Register 1 is set by
Logic Operation Set/Reset Cycle
bringing
low at the falling edge of
during
WE
RAS
A logic operation set/reset cycle is performed by
the write cycle, and the mask data is available only
in this cycle. Register 2 is set by level of I/O in the
logic operation set/reset cycle, and the mask data is
available until the next logic operation set/reset
cycle. If register 1 is set during the current logic
operation mode, the mask data of the register is
preferred (that of register 2 is ignored) and the
logic becomes “THROUGH” only in this cycle
(figure 3).
bringing
and
low when
falls (figure
CAS
1). The logic code and the bits to be masked are
determined respectively by A 0–A 3 state and
WE
RAS
×
×
I/01–I/04 state at the falling edge of
Furthermore, in this cycle the
refresh operation is executed also. In the case of
executing the conventional
refresh operation,
falls.
.
RAS
-before-
CAS
RAS
-before-
CAS
must be high when
RAS
RAS
WE
34
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
RAS
CAS
L
FC0–FC3
L
Address
WE
DT/OE
Mask
register 2
I/O
Do not care
Figure 1 Logic Operation Set/Reset Cycle
Logic Code (FC0–FC3 are Ax0–Ax3 in Logic Operation Set Cycle)
Logic
———————————–
FC3
0
FC2
0
FC1
0
FC0
0
Symbol
Write Data
Description
—
—
—
0
Zero
0
0
0
1
AND1
AND2
Di Mi
·
0
0
1
0
Mi
Di·
0
0
0
1
1
0
1
0
X4 to X1
AND3
—
×
SAM organization changes to 1024
—
1
Di
·Mi
Logic operation mode reset
—
0
0
1
1
0
1
1
0
THROUGH
EOR
Di
Mi + Di
Di·
·Mi
0
1
1
1
0
0
1
0
0
1
0
1
OR1
Di + Mi
—
—
—
NOR
ENOR
Di·Mi
Di Mi +
·
Di·Mi
1
1
0
0
1
1
0
1
INV1
OR2
—
—
Di
+ Mi
Di
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
Logic Code (FC0–FC3 are Ax0–Ax3 in Logic Operation Set Cycle) (cont)
Logic
———————————–
FC3
1
FC2
1
FC1
0
FC0
0
Symbol
INV2
OR3
NAND
1
Write Data
Description
—
Mi
1
1
0
1
Di +
—
Mi
1
1
1
0
+
Di = External data-in
Di Mi
1
1
1
1
ONE
Mi = The data of the memory cell
SAM data register
Serial I/O
i + 1
e
a
b
c
d
SI/O1
SI/O2
SI/O3
SI/O4
f
g
h
Figure 2 Shift Method of SAM Data
By-4 Mode (SAM Organization: 256 4)
×
tSCC
SC
a
e
f
SI/O1
SI/O2
SI/O3
SI/O4
b
c
d
g
h
36
Home Print
HM53461, HM53462 Series
HM53461, HM53462 Series
By-1 Mode (SAM Organization: 1024 1)
×
tSCC
SC
a
b
c
d
e
SI/O1
High-Z
High-Z
SI/O2
SI/O3
SI/O4
High-Z
Logic operation
set reset cycle
Write cycle
Write cycle
Write cycle
Write cycle
RAS
CAS
L
L
H
L
H
H
H
H
H
H
WE
I/O1
0 Write
Masked
0 Write
1 Write
Masked
Masked
Masked
Masked
1 Write
0 Write
Masked
I/O2
Masked
1 Write
AND1
I/O3
I/O4
Masked
0 Write
AND1
1 Write
AND1
Logic
THROUGH
Mask register 2
is set
I/O2, I/O3:
masked.
Mask register 1
is set and valid
only in this cycle.
I/O1, I/O4:
Assume that the
logic is set to
AND1.
masked.
Figure 3 Example of Logic Operation Mode
Home Print
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