HM624256ALP-25 [HITACHI]
Cache SRAM, 256KX4, 25ns, CMOS, PDIP28, 0.400 INCH, PLASTIC, DIP-28;
| 型号： | HM624256ALP-25 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Cache SRAM, 256KX4, 25ns, CMOS, PDIP28, 0.400 INCH, PLASTIC, DIP-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM624256A Series
262144-word × 4-bit High Speed CMOS Static RAM
Description
The Hitachi HM624256A is a high speed 1M Static RAM organized as 262,144-word × 4-bit. It realizes high
speed access time (20/25/35 ns) and low power consumption, employing CMOS process technology and high
speed circuit designing technology. It is most advantageous for the field where high speed and high density
memory is required, such as the cache memory for main frame or 32-bit MPU. The HM624256A, packaged
in a 400-mil plastic SOJ is available for high density mounting.
Features
•
•
Single 5 V supply and high density 28-pin package (DIP and SOJ)
High speed
Access time: 20/25/35 ns (max)
Low power dissipation
•
•
Active mode: 350 mW (typ)
Standby mode: 100 µW (typ)
Completely static memory
No clock or timing strobe required
Equal access and cycle time
Directly TTL compatible
•
•
All inputs and outputs
HM624256A Series
Ordering Information
Type No.
Access Time Package
HM624256AP-20
HM624256AP-25
HM624256AP-35
20 ns
25 ns
35 ns
400 mil 28-pin plastic DIP (DP-28C)
HM624256ALP-20 20 ns
HM624256ALP-25 25 ns
HM624256ALP-35 35 ns
HM624256AJP-20 20 ns
HM624256AJP-25 25 ns
HM624256AJP-35 35 ns
400 mil 28-pin plastic SOJ (CP-28D)
HM624256ALJP-20 20 ns
HM624256ALJP-25 25 ns
HM624256ALJP-35 35 ns
2
HM624256A Series
Pin Arrangement
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A17
A16
A15
A14
A13
A12
A11
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
I/O 1
I/O 2
I/O 3
I/O 4
WE
CS
OE
VSS
(Top view)
Pin Description
Pin Name
A0 – A17
I/O1 – I/O4
CS
Function
Address
Input/output
Chip select
Output enable
Write enable
Power supply
Ground
OE
WE
VCC
VSS
3
HM624256A Series
Block Diagram
A2
A3
VCC
VSS
A4
Row
decoder
Memory array
512 × 2048
A5
A6
A7
A8
A9
A10
I/O1
I/O2
Column I/O
Input
data
control
Column decoder
I/O3
I/O4
A0 A1 A11A12A13A14A15A16A17
CS
WE
OE
Function Table
CS
H
L
OE
X
WE
X
Mode
VCC Current I/O Pin
Ref. Cycle
Not selected ISB, ISB1
High-Z
Dout
Din
L
H
Read
Write
Write
ICC
ICC
ICC
Read cycle (1) – (3)
Write cycle (1)
L
H
L
L
L
L
Din
Write cycle (2)
Note: X: H or L
Absolute Maximum Ratings
Parameter
Symbol
Vin
Value
–0.5*1 to +7.0
Unit
Voltage on any pin relative to VSS
Power dissipation
V
PT
1.0
W
°C
°C
°C
Operating temperature range
Storage temperature range
Storage temperature range under bias
Topr
Tstg
Tbias
0 to +70
–55 to +125
–10 to +85
Note: 1. Vin min = –2.0 V for pulse width ≤ 10 ns
4
HM624256A Series
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
4.5
0
Typ
5.0
0
Max
5.5
0
Unit
V
Supply voltage
VSS
V
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
2.2
–0.5*1
—
6.0
0.8
V
VIL
—
V
Note: 1. VIL min = –2.0 V for pulse width ≤ 10 ns
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
HM624256A-20
HM624256A-25/35
Parameter
Symbol Min Typ*1 Max Min Typ*1 Max Unit Test Conditions
Input leakage current
|ILI|
—
—
—
—
—
—
—
—
—
2.0
2.0
150
60
—
—
—
—
—
—
2.0
2.0
120
40
µA
µA
VCC = max
Vin = VSS to VCC
Output leakage current
|ILO|
—
CS = VIH
VI/O = VSS to VCC
Operating power supply ICC
current
—
mA CS = VIL, II/O = 0 mA,
min cycle
Standby power supply
current
ISB
—
mA CS = VIH,
min cycle
Standby power supply
current (1)
ISB1
0.02 2.0
0.02
2.0
mA CS ≥ VCC – 0.2 V
0 V ≤ Vin ≤ 0.2 V or
Vin ≥ VCC – 0.2 V
*2
ISB1
—
—
—
—
100*2
—
—
—
—
100*2 µA
Output low voltage
Output high voltage
VOL
—
0.4
—
—
0.4
—
V
V
IOL = 8 mA
VOH
2.4
2.4
IOH = –4 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
2. L-version
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Min
—
Max
5*2
6*3
8
Unit
pF
Test Conditions
Input capacitance
Cin
Vin = 0 V
—
pF
Input/output capacitance
CI/O
—
pF
VI/O = 0 V
Notes: 1. This parameter is sampled and not 100% tested.
2. SOJ package
3. DIP package
5
HM624256A Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
•
•
•
•
•
Input pulse levels: 0V to 3.0 V
Input rise and fall time: 4 ns
Input timing reference levels: 1.5 V
Output timing reference levels: 1.5 V
Output load: See figures
+ 5 V
+ 5 V
480 Ω
480 Ω
Dout
Dout
255 Ω
30 pF *1
255 Ω
5 pF *1
Output load (A)
Note: 1. Including scope and jig
Output load (B)
(For tCHZ, tOHZ, tCLZ, tOLZ, tWHZ and tOW
)
Read Cycle
HM624256A-20 HM624256A-25 HM624256A-35
Parameter
Symbol Min
Max
—
Min
25
—
—
5
Max
—
Min
35
—
—
5
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
tRC
20
—
—
5
Address access time
tAA
20
20
—
25
25
—
35
35
—
Chip select access time
tACS
*1
Chip selection to output in low-Z
Output enable to output valid
Output enable to output in low-Z
Chip deselection to output in high-Z
Chip disable to output in high-Z
Output hold from address change
Chip selection to power up time
tCLZ
tOE
—
0
10
—
—
0
12
—
—
0
15
—
*1
*1
tOLZ
tCHZ
tOHZ
tOH
0
10
10
—
0
12
10
—
0
15
10
—
*1
0
0
0
5
5
5
tPU
0
—
0
—
0
—
Chip deselection to power down time tPD
—
12
—
15
—
25
Notes: 1. Transition is measured ±200 mV from steady state voltage with Load (B). This parameter is
sampled not 100% tested.
6
HM624256A Series
Read Timing Waveform (1)*1 (WE = VIH)
tRC
Address
OE
tAA
tOE
tOH
tOLZ
CS
tOHZ
tCHZ
tACS
tCLZ
Dout
Valid Data
Notes: 1. Transition is measured ±200 mV from state voltage with Load (B). This parameter is
sampled and not 100% tested.
Read Timing Waveform (2) (WE = VIH, CS = VIL, OE = VIL)
tRC
Address
tAA
tOH
tOH
Valid Data
Dout
7
HM624256A Series
Read Timing Waveform (3)*1, *2 (WE = VIH, OE = VIL)
CS
tCHZ
tACS
tCLZ
Dout
Valid Data
tPD
High
Impedance
High Impedance
tPU
VCC supply
current
ICC
ISB
50 %
50 %
Notes: 1. Transition is measured ±200 mV from steady state voltage with Load (B). This parameter
is sampled and not 100% tested.
2.Device is continuously selected, CS = VIL.
Write Cycle
HM624256A-20 HM624256A-25 HM624256A-35
Parameter
Symbol Min
Max
—
—
—
—
—
—
10
12
—
—
—
Min
25
17
20
0
Max
—
—
—
—
—
—
10
15
—
—
—
Min
35
25
30
0
Max
—
—
—
—
—
—
10
15
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
tWC
tCW
tAW
tAS
20
15
16
0
Chip selection to end of write
Address valid to end of write
Address setup time
Write pulse width
*2
tWP
15
0
17
0
25
0
*3
tWR
Write recovery time
*4
Output disable to output in high-Z tOHZ
0
0
0
*4
Write to output in high-Z
Data to write time overlap
Data hold from write time
Output active from end of write
tWHZ
tDW
0
0
0
12
0
15
0
20
0
*5
tDH
*1
tOW
0
0
0
Notes: 1. Transition is measured ±200 mV from steady state voltage with Load (B). This parameter is
sampled and not 100% tested.
2. A write occurs during the overlap (tWP) of a low CS and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If CS is low during this period, I/O pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
8
HM624256A Series
Write Timing Waveform (1)
tWC
Address
tWR
OE
CS
tCW
*1
tAW
tAS
WE
tOHZ
tWP
Dout
Din
tDW
tDH
Valid Data
Notes: 1. If the CS low transition occurs simultaneously with the WE low transition or after the WE
transition, output remain in a high impedance state.
Write Timing Waveform (2) (OE Low Fixed)
tWC
Address
tWR
tCW
CS
*1
tWP
WE
tOH
*2
tAS
*3
tWHZ
tOW
Dout
Din
tDW
tDH
Valid Data
Notes: 1. If the CS low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
2.Dout is the same phase of write data of this write cycle.
3.Dout is the read data of next address.
9
HM624256A Series
Low VCC Date Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter
Symbol
Min Typ Max Unit Test Conditions
VCC for data retention
VDR
2.0
—
—
V
CS ≥ VCC – 0.2 V,
Vin ≥ VCC – 0.2 V or
0 V ≤ Vin ≤ 0.2 V
Data retention current
ICCDR
—
0
2
50*1 µA
Chip deselect to data retention time tCDR
—
—
—
—
ns
Operation recovery time
Note: 1. VCC = 3.0 V
tR
5
ms
Low VCC Data Retention Timing Waveform
Data retention mode
VCC
4.5 V
tR
tCDR
2.2 V
VDR
CS
0 V
≥
CS VCC – 0.2 V
10
HM624256A Series
Package Dimensions
HM624256AP/ALP Series (DP-28C)
Unit: mm
34.70
35.56 Max
28
15
14
1
0.89
1.30
1.27 Max
10.16
+ 0.11
– 0.05
0.25
2.54 ± 0.25
0.48 ± 0.10
0° – 15°
HM624256AJP/ALJP Series (CP-28D)
Unit: mm
18.17
18.54 Max
15
14
28
1
0.74
1.30 Max
1.27
0.10
0.43 ± 0.10
9.40 ± 0.25
11
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