HM6264ASP-15T [HITACHI]
8192-word x 8-bit High Speed CMOS Static RAM; 8192字×8位高速CMOS静态RAM
| 型号： | HM6264ASP-15T |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 8192-word x 8-bit High Speed CMOS Static RAM |
| 文件： | 总10页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM6264A Series
8192-word × 8-bit High Speed CMOS Static RAM
Access
time
Features
Type No.
Package
• Low-power standby
— 0.1 mW (typ)
— 10 µW (typ) L-/LL-version
• Low power operation
— 15 mW/MHz (typ)
• Fast access time
— l00/120/150 ns (max)
• Single +5 V supply
• Completely static memory
— No clock or timing strobe required
• Equal access and cycle time
• Common data input and output, three-state
output
• Directly TTL compatible
— All inputs and outputs
• Battery back up operation capability
(L-/LL-version)
HM6264ASP-10 100 ns
HM6264ASP-12 120 ns
HM6264ASP-15 150 ns
HM6264ALSP-10 100 ns
HM6264ALSP-12 120 ns
HM6264ALSP-15 150 ns
HM6264ALSP-10L 100 ns
HM6264ALSP-12L 120 ns
HM6264ALSP-15L 150 ns
HM6264AFP-10 100 ns
HM6264AFP-12 120 ns
HM6264AFP-15 150 ns
HM6264ALFP-10 100 ns
HM6264ALFP-12 120 ns
HM6264ALFP-15 150 ns
HM6264ALFP-10L 100 ns
HM6264ALFP-12L 120 ns
HM6264ALFP-15L 150 ns
300-mil, 28-pin
plastic DIP
(DP-28N)
28-pin plastic
SOP *1
(FP-28D/DA)
Ordering Information
Access
Type No.
time
Package
HM6264AP-10
HM6264AP-12
HM6264AP-15
100 ns
120 ns
150 ns
600-mil, 28-pin
plastic DIP
(DP-28)
HM6264ALP-10 100 ns
HM6264ALP-12 120 ns
HM6264ALP-15 150 ns
HM6264ALP-10L 100 ns
HM6264ALP-12L 120 ns
HM6264ALP-15L 150 ns
Note: 1. T is added to the end of the type number
for a SOP of 3.00 mm (max) thickness.
1
HM6264A Series
HM6264A Series
Pin Arrangement
1
2
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
28
27
26
VCC
WE
CS2
A8
3
4
25
24
5
A9
23
22
21
20
19
6
A11
OE
A10
CS1
I/O8
I/O7
I/O6
7
8
9
10
11
12
13
14
I/O1
I/O2
18
17
16
15
I/O5
I/O4
I/O3
VSS
(Top view)
Block Diagram
A11
A8
A9
A7
A12
A5
VCC
VSS
Row
decoder
Memory array
256 × 256
A6
A4
I/O1
I/O8
Column I/O
Input
data
control
Column decoder
A1 A2 A0 A10 A3
CS2
CS1
Timing pulse generator
WE
OE
2
HM6264A Series
HM6264A Series
Truth Table
WE
CS1
CS2
OE
Mode
I/O pin
High Z
High Z
VCC current
Note
ISB ISB1
,
Not selected
(power down)
×
H
×
×
ISB ISB1
,
×
×
L
×
H
L
H
H
Output disabled High Z
ICC
ICC
ICC
ICC
H
L
L
L
L
L
H
H
H
L
H
L
Read
Write
Write
Dout
Din
Read cycle
Write cycle 1
Write cycle 2
Din
Note: ×: Don’t care.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Terminal voltage *1
VT
–0.5 *2 to +7.0
1.0
V
Power dissipation
PT
W
°C
°C
°C
Operating temperature
Storage temperature
Topr
Tstg
Tbias
0 to +70
–55 to +125
–10 to +85
Storage temperature (under bias)
Notes: 1. With respect to VSS.
2. –3.0 V for pulse width ≤ 50 ns
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
4.5
Typ
5.0
0
Max
5.5
0
Unit
V
Supply voltage
VSS
0
V
VIH
2.2
—
6.0
0.8
V
Input voltage
VIL
–0.3 *1
—
V
Note: 1. –3.0 V for pulse width ≤ 50 ns
3
HM6264A Series
HM6264A Series
DC and Operating Characteristics (V = 5 V ± 10%,V = 0 V, Ta = 0 to +70°C)
CC
SS
Parameter
Symbol
Min Typ Max Unit Test condition
Input leakage current |ILI|
Output leakage current |ILO
—
—
—
—
2
2
µA
µA
Vin = VSS to VCC
|
CS1 = VIH or CS2 = VIL or OE = VIH or
WE = VIL, VI/O = VSS to VCC
Operating power
supply current
ICCDC
—
7
15
mA
CS1 = VIL, CS2 = VIH, II/O = 0 mA
ICC1
—
—
30
30
45*5 mA
55*6
Min. cycle, duty = 100%,
CS1 = VIL, CS2 = VIH, II/O = 0 mA
Average operating
current
ICC2
—
3
5
mA
Cycle time = 1 µs, duty = 100%,
I
I/O = 0 mA, CS1 ≤ 0.2 V,
CS2 ≥ VCC – 0.2 V, VIH ≥ VCC – 0.2 V,
IL ≤ 0.2 V
V
ISB
—
—
1
3
2
mA
mA
CS1 = VIH or CS2 = VIL
Standby power supply
current
ISB1 *2
0.02
CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V or
0 V ≤ CS2 ≤ 0.2 V, 0 V ≤ Vin
————————————
2*3 100*3 µA
—————————
—
—
2*4
—
—
50*4
0.4
—
VOL
VOH
—
V
V
IOL = 2.1 mA
Output voltage
2.4
IOH = –1.0 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = 25°C and not guaranteed.
2. VIL min = –0.3 V
3. These characteristics are guaranteed only for the L-version.
4. These characteristics are guaranteed only for the LL-version.
5. For 120 ns/150 ns version.
6. For 100 ns version.
*1
Capacitance (f = 1 MHz, Ta = 25°C)
Parameter
Symbol
Cin
Typ
—
Max
5
Unit
pF
Test condition
Vin = 0 V
Input capacitance
Input/output capacitance
CI/O
—
7
pF
VI/O = 0 V
Note: 1. This parameter is sampled and is not 100% tested.
4
HM6264A Series
HM6264A Series
AC Characteristics (V = 5 V ± 10%, Ta = 0 to +70°C)
CC
AC Test Conditions:
• Input pulse levels: 0.8 V/2.4 V
• Input rise and fall time: 10 ns
• Input timing reference level: 1.5 V
• Output timing reference level
— HM6264A-10: 1.5 V
— HM6264A-12/15: 0.8 V/2.0 V
• Output load: 1 TTL gate and C (100 pF) (including scope and jig)
L
Read Cycle
HM6264A-10
HM6264A-12
HM6264A-15
——————— ——————— ———————
Parameter
Symbol Min
Max
Min
120
—
—
—
—
10
10
5
Max
Min
150
—
—
—
—
15
15
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
tRC
100
—
—
—
—
10
10
5
—
—
—
tAA
100
100
100
50
120
120
120
60
150
150
150
70
Address access time
CS1
tCO1
tCO2
tOE
Chip selection to output
CS2
Output enable to output valid
CS1
CS2
Output enable to output in low Z
tLZ1
tLZ2
tOLZ
tHZ1
—
—
—
Chip selection to output
in low Z
—
—
—
—
—
—
CS1
0
35
0
40
0
50
Chip deselection to
output in high Z
CS2
tHZ2
tOHZ
0
35
0
40
0
50
Output disable to output in high Z
Output hold from address change
0
35
0
40
0
50
tOH
10
—
10
—
10
—
Notes 1. tHZ and tOHZ are defined as the time at which the outputs to achieve the open circuit
condition and are not referred to output voltage levels.
2. At any given temperature and voltage condition, tHZ maximum is less than tLZ minimum both for
a given device and from device to device.
5
HM6264A Series
HM6264A Series
Read Timing Waveform
tRC
Address
tAA
tCO1
CS1
tLZ1
tCO2
tHZ1
CS2
tLZ2
tOE
tOLZ
tHZ2
tOHZ
tOH
OE
Dout
Valid Data
Note: WE is high for read cycle.
Write Cycle
HM6264A-10
HM6264A-12
HM6264A-15
——————— ——————— ———————
Parameter
Symbol Min
Max
—
—
—
—
—
—
35
—
—
35
—
Min
120
85
0
Max
Min
150
100
0
Max
—
—
—
—
—
—
50
—
—
50
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
tWC
tCW
tAS
100
80
0
—
Chip selection to end of write
Address setup time
—
—
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
80
60
0
85
70
0
—
100
90
0
—
Write recovery time
—
Write to output in high Z
Data to write time overlap
Data hold from write time
0
0
40
—
0
40
0
40
0
50
0
—
Output enable to output in high Z tOHZ
Output active from end of write tOW
0
0
40
——
0
5
5
5
6
HM6264A Series
HM6264A Series
Write Timing Waveform (1) (OE Clock)
tWC
Address
OE
*2
*4
tCW
tWR
CS1
*6
CS2
tAW
*3
tAS
*1
tWP
WE
*5
tOHZ
Dout
Din
tDW
tDH
Valid Data
7
HM6264A Series
HM6264A Series
Write Timing Waveform (2) (OE Low Fix)
tWC
Address
tAW
tCW
*4
tWR
*2
*6
CS1
*2
tCW
CS2
*1
tWP
*3
tAS
tOH
WE
tOW
*5
tWHZ
*7
*9
*8
Dout
Din
tDW
tDH
Valid Data
Notes: 1. A write occurs during the overlap of a low CS1, a high CS2, and a low WE. A write begins
at the latest transition among CS1 going low, CS2 going high and WE going low. A write
ends at the earliest transition among CS1 going high, CS2 going low and WE going high.
Time tWP is measured from the beginning of write to the end of write.
2.
3.
4.
t
t
t
CW is measured from the later of CS1 going low or CS2 going high to the end of write.
AS is measured from the address valid to the beginning of write.
WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end
of the write cycle.
5. During this period, I/O pins are in the output state, therefore the input signals of opposite
phase to the outputs must not be applied.
6. If CS1 goes low simultaneously with WE going low or after WE goes low, the outputs
remain in high impedance state.
7. Dout is the same phase of the latest written data in this write cycle.
8. Dout is the read data of the next address.
9. If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input signals
of opposite phase to the outputs must not be applied to I/O pins
8
HM6264A Series
HM6264A Series
Low V Data Retention
CC
In data retention mode, CS2 controls the address,
WE, CS1, OE, and the Din buffer. If CS2 controls
data retention mode, Vin (for these inputs) can be
in the high impedance state. If CS1 controls the
data retention mode, CS2 must satisfy either
CS2 ≥ V
– 0.2 V or CS2 ≤ 0.2 V. The other
CC
input levels (address, WE, OE, I/O) can be in the
high impedance state.
Low V
Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only L/LL-version.
CC
Parameter
Symbol
Min
Typ
Max
Unit
Test Condition
VCC for data retention
VDR
2.0
—
—
V
CS1 ≥ VCC – 0.2 V,
CS2 ≥ VCC– 0.2 V, or
CS2 ≤ 0.2 V
Data retention current
ICCDR
—
—
1*1
1*2
50*1
25*2
µA
VCC = 3.0 V,
CS1 ≥ VCC – 0.2 V,
CS2 ≥ VCC – 0.2 V, or
0 V ≤ CS2 ≤ 0.2 V, 0 V ≤ Vin
tCDR
Chip deselect to data
retention time
0
—
—
—
—
ns
ns
See retention waveform
tRC
*3
Operation recovery time tR
See retention waveform
Notes: 1. VIL min = –0.3 V, 20 µA max at Ta = 0 to 40°C. These characteristics are guaranteed only for
the L-version.
2. VIL min = –0.3 V, 10 µA max at Ta = 0 to 40°C. These characteristics are guaranteed only for
the LL-version.
3. tRC = Read cycle time.
Low V
Data Retention Waveform (1) (CS1 Controlled)
CC
tCDR
tR
Data retention mode
VCC
4.5 V
2.2 V
VDR
CS1
0 V
CS1 ≥ VCC – 0.2 V
9
HM6264A Series
HM6264A Series
Low V
Data Retention Waveform (2) (CS2 Controlled)
CC
Data retention mode
VCC
4.5 V
tCDR
tR
CS2
VDR
0.4 V
0 V
CS2 ≤ 0.2 V
10
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