HM62V8256BLTSI-10UL [HITACHI]
STANDARD SRAM, PDSO32, 8 X 13.40 MM, PLASTIC, TSOP1-32;
| 型号： | HM62V8256BLTSI-10UL |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | STANDARD SRAM, PDSO32, 8 X 13.40 MM, PLASTIC, TSOP1-32 静态存储器 光电二极管 |
| 文件： | 总16页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62V8256BI Series
2 M SRAM (256-kword × 8-bit)
ADE-203-1004 (Z)
Preliminary, Rev. 0.0
Jan. 19, 1999
Description
The Hitachi HM62V8256BI Series is 2-Mbit static RAM organized 262,144-kword × 8-bit.
HM62V8256BI Series has realized higher density, higher performance and low power consumption by
employing Hi-CMOS process technology. The HM62V8256BI Series offers low power standby power
dissipation; therefore, it is suitable for battery backup systems. It is packaged in standard 32-pin plastic
TSOPI.
Features
•
•
•
Single 3.0 V supply: 2.7 V to 3.6 V
Access time: 85 ns/100 ns (max)
Power dissipation
Active: 15 mW/MHz (typ)
Standby: 2.4 µW (typ)
•
Completely static memory.
No clock or timing strobe required
Equal access and cycle times
Common data input and output
Three state output
•
•
•
•
Directly LV-TTL compatible all inputs
Battery backup operation
2 chip selection for battery backup
Temperature range: –40 to +85°C
•
HM62V8256BI Series
Ordering Information
Type No.
Access time Package
HM62V8256BLTSI-8
HM62V8256BLTSI-10
85 ns
100 ns
8 × 13.4 mm 32-pin plastic TSOP I (TFP-32DC)
HM62V8256BLTSI-8SL
85 ns
HM62V8256BLTSI-10SL 100 ns
HM62V8256BLTSI-8UL 85 ns
HM62V8256BLTSI-10UL 100 ns
2
HM62V8256BI Series
Pin Arrangement
32-pin TSOP (Normal Type TSOP)
1
A11
A9
32
OE
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
3
A8
4
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
5
6
7
8
9
10
11
12
13
14
15
16
A6
A1
A5
A2
A4
A3
(Top view)
Pin Description
Pin name
A0 to A17
I/O0 to I/O7
CS1
Function
Address input
Data input/output
Chip select 1
Chip select 2
Write enable
Output enable
Power supply
Ground
CS2
WE
OE
VCC
VSS
NC
No connection
3
HM62V8256BI Series
Block Diagram
LSB
A12
VCC
VSS
A7
A6
A5
A4
A3
A2
A1
A0
•
•
•
•
•
Memory matrix
512 x 4,096
Row
decoder
A10
MSB
I/O0
I/O7
•
•
•
•
Column I/O
Input
data
control
Column decoder
LSB
MSB
A14A16A15A13 A8 A9 A11 A17
•
•
CS1
CS2
Timing pulse generator
Read/Write control
WE
OE
4
HM62V8256BI Series
Operation Table
CS1
H
L
CS2
H
WE
×
OE
×
I/O
Operation
Standby
Standby
Standby
Read
High-Z
High-Z
High-Z
Dout
Din
L
×
×
L
L
×
×
L
H
H
L
L
L
H
H
L
Write
L
H
L
Din
Write
L
H
H
H
High-Z
Output disable
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage relative to VSS
Terminal voltage on any pin relative to VSS
Power dissipation
VCC
VT
–0.5 to +4.6
–0.5*1 to VCC + 0.3*2
1.0
V
V
PT
W
°C
°C
Storage temperature range
Storage temperature range under bias
Tstg
Tbias
–55 to +125
–40 to +85
Notes: 1. VT min: –1.5 V for pulse half-width ≤ 30 ns
2. Maximum voltage is +4.6 V
DC Operating Conditions
Parameter
Symbol
VCC
Min
2.7
0
Typ
3.0
0
Max
3.6
Unit
V
Note
Supply voltage
VSS
0
V
Input high voltage
VIH
2.4
–0.3
–40
—
VCC + 0.3
0.4
V
Input low voltage
VIL
—
V
1
Ambient temperature range
Ta
—
+85
°C
Note: 1. VIL min: –1.5 V for pulse half-width ≤ 30 ns
5
HM62V8256BI Series
DC Characteristics
Parameter
Symbol Min
Typ*1
—
Max
1
Unit
µA
Test conditions
Input leakage current
Output leakage current
|ILI|
—
—
Vin = VSS to VCC
|ILO|
—
1
µA
CS1 = VIH or CS2 = VIL or
OE = VIH or WE = VIL,
VI/O = VSS to VCC
Operating current
ICC
—
—
—
—
5
mA
mA
CS1 = VIL, CS2 = VIH,
others = VIH/VIL, II/O = 0 mA
Average operating current
ICC1
30
Min cycle, duty = 100%
II/O = 0 mA, CS1 = VIL, CS2
= VIH, Others = VIH/VIL
ICC2
—
5
10
mA
Cycle time = 1 µs,
duty = 100%,
II/O = 0 mA, CS1 ≤ 0.2 V,
CS2 ≥ VCC – 0.2 V,
VIH ≥ VCC – 0.2 V,
VIL ≤ 0.2 V
Standby current
ISB
—
—
0.1
0.8
0.3
60
mA
(1) CS1 = VIH, CS2 = VIH or
(2) CS2 = VIL
2
ISB1
*
µA
0 V ≤ Vin
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS1 ≥ VCC – 0.2 V,
CS2 ≥ VCC – 0.2 V
3
4
ISB1
*
*
—
—
0.8
0.5
30
8
µA
µA
V
ISB1
Output high voltage
Output low voltage
VOH
VCC–0.2 —
—
—
0.4
0.2
IOH = –100 µA
IOH = –1 mA
IOL = 2.1 mA
IOL = 100 µA
2.4
—
—
—
—
V
VOL
V
—
V
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. This characteristics is guaranteed only for L version.
3. This characteristics is guaranteed only for L-SL version.
4. This characteristics is guaranteed only for L-UL version.
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter
Symbol
Cin
Typ
—
Max
8
Unit
pF
Test conditions
Vin = 0 V
Note
Input capacitance
Input/output capacitance
1
1
CI/O
—
10
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
6
HM62V8256BI Series
AC Characteristics (Ta = –40 to +85°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions
•
•
•
•
•
Input pulse levels: VIL = 0.4 V, VIH = 2.4 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.4 V
Output timing reference level: 1.4 V
Output load (Including scope and jig)
VTM
R1
R2
Dout
R1 = 3070 Ω
50pF
R2 = 3150 Ω
VTM = 2.8 V
Read Cycle
HM62V8256BI
-8
-10
Min
100
—
—
—
—
10
10
10
5
Parameter
Symbol
tRC
Min
85
—
—
—
—
10
10
10
5
Max
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
Address access time
Chip select access time
tAA
85
85
85
45
—
100
100
100
60
tCO1
tCO2
tOE
Output enable to output valid
Output hold from address change
Chip selection to output in low-Z
tOH
—
tCLZ1
tCLZ2
tOLZ
—
—
2, 3
—
—
2, 3
Output enable to output in low-Z
—
—
2, 3
Chip deselection to output in high-Z tCHZ1
tCHZ2
0
35
35
35
0
40
1, 2, 3
1, 2, 3
1, 2, 3
0
0
40
Output disable to output in high-Z
tOHZ
0
0
40
7
HM62V8256BI Series
Write Cycle
HM62V8256BI
-8
-10
Min
100
90
90
80
0
Parameter
Symbol
tWC
Min
85
75
75
55
0
Max
—
—
—
—
—
—
—
—
—
35
35
Max
—
—
—
—
—
—
—
—
—
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write cycle time
Address valid to end of write
Chip selection to end of write
Write pulse width
tAW
tCW
5
tWP
4, 13
Address setup time
Write recovery time
Data to write time overlap
Data hold from write time
tAS
6
7
tWR
0
0
tDW
35
0
40
0
tDH
Output active from output in high-Z tOW
5
5
2
Output disable to output in high-Z
tOHZ
tWHZ
0
0
1, 2, 8
1, 2, 8
WE to output in high-Z
0
0
Notes: 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given
device and from device to device.
4. A write occurs during the overlap (tWP) of a low CS1, a high CS2, and a low WE. A write begins
at the later transition of CS1 going low, CS2 going high, or WE going low. A write ends at the
earlier transition of CS1 going high, CS2 going low, or WE going high. tWP is measured from the
beginning of write to the end of write.
5. tCW is measured from CS1 going low or CS2 going high to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earlier of WE or CS1 going high or CS2 going low to the end of write
cycle.
8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite
phase to the outputs must not be applied.
9. If the CS1 goes low or CS2 going high simultaneously with WE going low or after WE going low,
the output remain in a high impedance state.
10. Dout is the same phase of the write data of this write cycle.
11. Dout is the read data of next address.
12. If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the
input signals of the opposite phase to the outputs must not be applied to them.
13. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention. tWP ≥ tDW min + tWHZ max
8
HM62V8256BI Series
Timing Waveforms
Read Cycle (WE = VIH)
tRC
Address
Valid address
tAA
CS1
tACS1
tCLZ1
tCHZ1
CS2
tACS2
tCLZ2
tCHZ2
OE
tOHZ
tOH
tOE
tOLZ
High impedance
Dout
Valid data
9
HM62V8256BI Series
Write Cycle (1) (OE Clock)
tWC
Valid address
tAW
Address
OE
tCW
CS1
*9
tWR
CS2
tWP
tAS
WE
tOHZ
High impedance
Dout
Din
tDW
tDH
Valid data
10
HM62V8256BI Series
Write Cycle (2) (OE = VIL)
tWC
Address
Valid address
tCW
tWR
CS1
*9
CS2
tAW
tWP
tOH
WE
tAS
tOW
tWHZ
*11
*10
High impedance
tDW tDH
Dout
Din
*12
Valid data
11
HM62V8256BI Series
Low VCC Data Retention Characteristics (Ta = –40 to +85°C)
Parameter
Symbol Min
Typ*5 Max Unit
Test conditions*4
VCC for data retention
VDR
2.0
—
—
V
Vin ≥ 0V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ VCC – 0.2 V
CS1 ≥ VCC – 0.2 V
1
Data retention current
ICCDR
*
—
0.8
30
µA
VCC = 3.0 V, Vin ≥ 0 V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ VCC – 0.2 V,
CS1 ≥ VCC – 0.2 V
2
3
ICCDR
ICCDR
Chip deselect to data retention time tCDR
Operation recovery time tR
*
—
0.8
0.5
—
15
3
µA
µA
ns
ns
*
—
0
tRC*6
—
—
See retention waveform
—
Notes: 1. This characteristic is guaranteed only for L-version, 15 µA max. at Ta = –40 to +40°C.
2. This characteristic is guaranteed only for L-SL-version, 5 µA max. at Ta = –40 to +40°C.
3. This characteristic is guaranteed only for L-UL-version, 2 µA max. at Ta = –40 to +40°C.
4. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state.
If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The
other input levels (address, WE, OE, I/O) can be in the high impedance state.
5. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
6. tRC = read cycle time.
Low VCC Data Retention Timing Waveform (1) (CS1 Controlled)
tCDR
Data retention mode
tR
VCC
2.7V
2.4 V
VDR
CS1
0 V
CS1 ≥ VCC – 0.2 V
12
HM62V8256BI Series
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
tCDR
Data retention mode
tR
VCC
2.7 V
CS2
VDR
0.4 V
0 V
0 V ≤ CS2 ≤ 0.2 V
13
HM62V8256BI Series
Package Dimensions
HM62V8256BLTSI Series (TFP-32DC)
Unit: mm
8.00
8.20 Max
17
32
1
16
0.50
0.22 ± 0.08
0.20 ± 0.06
0.08 M
0.80
13.40 ± 0.30
0.43 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
TFP-32DC
JEDEC
EIAJ
—
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.23 g
14
HM62V8256BI Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
: http:semiconductor.hitachi.com/
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
Asia (Taiwan)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
Hitachi Europe GmbH
Electronic components Group
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
2000 Sierra Point Parkway Dornacher Straße 3
Brisbane, CA 94005-1897 D-85622 Feldkirchen, Munich
Tel: <1> (800) 285-1601
Fax: <1> (303) 297-0447
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
15
HM62V8256BI Series
Revision Record
Rev. Date
0.0 Jan. 19, 1999
Contents of Modification
Initial issue
Drawn by Approved by
16
相关型号：
HM62V8256BLTSI-8UL
Standard SRAM, 256KX8, 85ns, CMOS, PDSO32, 8 X 13.40 MM, PLASTIC, TSOP1-32
HITACHI
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