HM62V8512BLFP-8SL [HITACHI]
4 M SRAM (512-kword x 8-bit); 的4M SRAM（ 512千字×8位）的
| 型号： | HM62V8512BLFP-8SL |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 4 M SRAM (512-kword x 8-bit) |
| 文件： | 总17页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62V8512B Series
4 M SRAM (512-kword × 8-bit)
ADE-203-905G (Z)
Rev. 6.0
Mar. 31, 2000
Description
The Hitachi HM62V8512B is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density,
higher performance and low power consumption by employing 0.35 µm Hi-CMOS process technology. The
device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is available for high
density mounting. The HM62V8512B is suitable for battery backup system.
Features
•
•
•
Single 3.0 V supply: 2.7 V to 3.6 V
Access time: 70/85 ns (max)
Power dissipation
Active: 15 mW/MHz (typ)
Standby: 3 µW (typ)
•
•
•
•
•
Completely static memory. No clock or timing strobe required
Equal access and cycle times
Common data input and output: Three state output
Directly LV-TTL compatible: All inputs
Battery backup operation
HM62V8512B Series
Ordering Information
Type No.
Access time
Package
HM62V8512BLFP-7
HM62V8512BLFP-8
70 ns
85 ns
525-mil 32-pin plastic SOP (FP-32D)
HM62V8512BLFP-7SL 70 ns
HM62V8512BLFP-8SL 85 ns
HM62V8512BLFP-7UL 70 ns
HM62V8512BLFP-8UL 85 ns
HM62V8512BLTT-7
HM62V8512BLTT-8
70 ns
85 ns
400-mil 32-pin plastic TSOP II (TTP-32D)
HM62V8512BLTT-7SL 70 ns
HM62V8512BLTT-8SL 85 ns
HM62V8512BLTT-7UL 70 ns
HM62V8512BLTT-8UL 85 ns
HM62V8512BLRR-7
HM62V8512BLRR-8
70 ns
85 ns
400-mil 32-pin plastic TSOP II reverse (TTP-32DR)
HM62V8512BLRR-7SL 70 ns
HM62V8512BLRR-8SL 85 ns
HM62V8512BLRR-7UL 70 ns
HM62V8512BLRR-8UL 85 ns
2
HM62V8512B Series
Pin Arrangement
HM62V8512BLFP Series
HM62V8512BLTT Series
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A18
A16
A14
A12
A7
A18
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
2
2
3
3
4
5
4
A6
6
A5
5
7
A9
A4
8
A11
OE
6
A6
A3
9
A2
7
10
11
12
13
14
15
16
A10
CS
A9
A5
A1
8
A11
OE
A10
A4
A0
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0
I/O1
I/O2
VSS
9
A3
10
11
12
13
14
15
16
A2
CS
A1
I/O7
I/O6
I/O5
I/O4
I/O3
A0
(Top view)
I/O0
I/O1
I/O2
VSS
HM62V8512BLRR Series
VCC
A15
A17
WE
A13
A8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
A18
A16
A14
A12
A7
2
3
(Top view)
4
5
6
A6
A9
7
A5
A11
OE
8
A4
9
A3
A10
CS
10
11
12
13
14
15
16
A2
A1
I/O7
I/O6
I/O5
I/O4
I/O3
A0
I/O0
I/O1
I/O2
VSS
(Top view)
Pin Description
Pin name
A0 to A18
I/O0 to I/O7
CS
Function
Address input
Data input/output
Chip select
OE
Output enable
Write enable
Power supply
Ground
WE
VCC
VSS
3
HM62V8512B Series
Block Diagram
V CC
V SS
A18
A16
A1
•
•
•
•
•
A0
Memory Matrix
A2
Row
Decoder
×
1,024 4,096
A12
A14
A3
A7
A6
I/O0
I/O7
•
•
•
Column I/O
•
Input
Data
Control
Column Decoder
A13 A17A15A8A9A11A10A4 A5
•
•
CS
Timing Pulse Generator
Read/Write Control
WE
OE
4
HM62V8512B Series
Function Table
WE
×
CS
H
L
OE
×
Mode
VCC current
Dout pin
Ref. cycle
—
Not selected
Output disable
Read
ISB, ISB1
ICC
High-Z
High-Z
Dout
Din
H
H
L
H
L
—
L
ICC
Read cycle
Write cycle (1)
Write cycle (2)
L
H
L
Write
ICC
L
L
Write
ICC
Din
Note: ×: H or L
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
V
Power supply voltage
Voltage on any pin relative to VSS
Power dissipation
–0.5 to +4.6
–0.5*1 to VCC + 0.5*2
1.0
VT
V
PT
W
Operating temperature
Storage temperature
Storage temperature under bias
Topr
Tstg
Tbias
–20 to +70
–55 to +125
–20 to +85
°C
°C
°C
Notes: 1. –3.0 V for pulse half-width ≤ 30 ns
2. Maximum voltage is 4.6 V
Recommended DC Operating Conditions (Ta = –20 to +70°C)
Parameter
Symbol
VCC
Min
2.7
Typ
3.0
0
Max
3.6
0
Unit
V
Supply voltage
VSS
0
V
Input high voltage
Input low voltage
VIH
2.0
–0.3*1
—
VCC + 0.3
0.8
V
V
VIL
—
Note: 1. –3.0 V for pulse half-width ≤ 30 ns
5
HM62V8512B Series
DC Characteristics (Ta = –20 to +70°C, VCC = 2.7 V to 3.6 V, VSS = 0 V)
Parameter
Symbol Min
Typ*1
—
Max
1
Unit Test conditions
Input leakage current
Output leakage current
|ILI|
—
—
µA Vin = VSS to VCC
|ILO|
—
1
µA CS = VIH or OE = VIH or
WE = VIL, VI/O = VSS to VCC
Operating power
supply current: DC
ICC
—
—
—
—
10
40
mA CS = VIL,
others = VIH/VIL, II/O = 0 mA
Operating
power supply current
ICC1
mA Min cycle, duty = 100%
CS = VIL, others = VIH/VIL
II/O = 0 mA
Operating power
supply current
ICC2
—
5
10
mA Cycle time = 1 µs,
duty = 100%
II/O = 0 mA, CS ≤ 0.2 V
VIH ≥ VCC – 0.2 V,
VIL ≤ 0.2 V
Standby power supply
current: DC
ISB
—
—
0.1
1*2
0.3
mA CS = VIH
Standby power supply
current (1): DC
ISB1
40*2
µA Vin ≥ 0 V,
CS ≥ VCC – 0.2 V
—
—
—
—
1*3
1*4
—
20*3
5*4
0.4
0.2
—
µA
µA
Output low voltage
Output high voltage
VOL
VOH
V
V
V
V
IOL = 2.1 mA
IOL = 100 µA
IOH = –100 µA
IOH = –1.0 mA
—
VCC – 0.2 —
2.4
—
—
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. This characteristics is guaranteed only for L version.
3. This characteristics is guaranteed only for L-SL version.
4. This characteristics is guaranteed only for L-UL version.
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter
Symbol
Cin
Typ
—
Max
8
Unit
pF
Test conditions
Vin = 0 V
Input capacitance*1
Input/output capacitance*1
CI/O
—
10
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
6
HM62V8512B Series
AC Characteristics (Ta = –20 to +70°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 0.4 V to 2.4 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.4 V
Output timing reference level: 1.5 V/1.5 V(HM62V8512B-7)
0.8 V/2.0 V(HM62V8512B-8)
Output load: 1 TTL Gate + CL (50 pF)
(Including scope & jig)
Read Cycle
HM62V8512B
-7
-8
Min
85
—
—
—
10
5
Parameter
Symbol
tRC
Min
70
—
—
—
10
5
Max
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
Address access time
tAA
70
70
35
—
85
85
45
—
Chip select access time
Output enable to output valid
Chip selection to output in low-Z
Output enable to output in low-Z
tCO
tOE
tLZ
2
tOLZ
—
—
2
Chip deselection to output in high-Z tHZ
0
30
30
—
0
35
35
—
1, 2
1, 2
Output disable to output in high-Z
Output hold from address change
tOHZ
tOH
0
0
10
10
7
HM62V8512B Series
Write Cycle
HM62V8512B
-7
-8
Min
85
75
0
Parameter
Symbol
tWC
Min
70
60
0
Max
—
—
—
—
—
—
30
—
—
—
30
Max
—
—
—
—
—
—
35
—
—
—
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write cycle time
Chip selection to end of write
Address setup time
tCW
4
5
tAS
Address valid to end of write
Write pulse width
tAW
60
50
0
75
55
0
tWP
3, 12
6
Write recovery time
WE to output in high-Z
Data to write time overlap
Data hold from write time
tWR
tWHZ
tDW
0
0
1, 2, 7
30
0
35
0
tDH
Output active from output in high-Z tOW
Output disable to output in high-Z tOHZ
5
5
2
0
0
1, 2, 7
Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later
transition of CS going low or WE going low. A write ends at the earlier transition of CS going high
or WE going high. tWP is measured from the beginning of write to the end of write.
4. tCW is measured from CS going low to the end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measured from the earlier of WE or CS going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to
the outputs must not be applied.
8. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.
12. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention. tWP ≥ tDW min + tWHZ max
8
HM62V8512B Series
Timing Waveforms
Read Timing Waveform (WE = VIH)
tRC
Address
tAA
tCO
CS
tLZ
tHZ
tOE
tOLZ
OE
tOHZ
Dout
Valid Data
tOH
9
HM62V8512B Series
Write Timing Waveform (1) (OE Clock)
tWC
Address
tAW
tWR
OE
tCW
CS
*8
tWP
tAS
WE
tOHZ
Dout
Din
tDW
tDH
Valid Data
10
HM62V8512B Series
Write Timing Waveform (2) (OE Low Fixed)
tWC
Address
tCW
tWR
CS
*8
tAW
tWP
tOH
WE
tAS
tOW
tWHZ
*10
*9
Dout
Din
tDW
tDH
*11
Valid Data
11
HM62V8512B Series
Low VCC Data Retention Characteristics (Ta = –20 to +70°C)
Parameter
Symbol Min
Typ
—
0.8*5
Max Unit
Test conditions*4
VCC for data retention
Data retention current
VDR
2
—
V
CS ≥ VCC – 0.2 V, Vin ≥ 0 V
ICCDR
—
20*1
µA
VCC = 3.0 V, Vin ≥ 0 V
CS ≥ VCC – 0.2 V
—
0.8*5
0.8*5
—
10*2
2*3
—
µA
µA
ns
ns
—
Chip deselect to data retention time tCDR
Operation recovery time tR
0
tRC*6
See retention waveform
—
—
Notes: 1. For L-version and 10 µA (max.) at Ta = –20 to +40°C.
2. For L-SL-version and 3 µA (max.) at Ta = –20 to +40°C.
3. For L-UL-version and 2 µA (max.) at Ta = –20 to +40°C.
4. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin
levels (address, WE, OE, I/O) can be in the high impedance state.
5. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
6. tRC = read cycle time.
Low VCC Data Retention Timing Waveform (CS Controlled)
Data retention mode
tCDR
tR
VCC
2.7 V
VDR
2.0 V
CS
0 V
≥
CS VCC – 0.2 V
12
HM62V8512B Series
Package Dimensions
HM62V8512BLFP Series (FP-32D)
Unit: mm
20.45
20.95 Max
17
32
1
16
14.14 ± 0.30
1.00 Max
1.42
0° – 8°
0.10
M
0.80 ± 0.20
1.27
*0.40 ± 0.08
0.15
0.38 ± 0.06
Hitachi Code
JEDEC
EIAJ
FP-32D
Conforms
—
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 1.3 g
13
HM62V8512B Series
Package Dimensions (cont.)
HM62V8512BLTT Series (TTP-32D)
Unit: mm
20.95
21.35 Max
32
17
16
1
1.27
*0.42 ± 0.08
0.40 ± 0.06
M
0.21
0.80
11.76 ± 0.20
1.15 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
EIAJ
TTP-32D
Conforms
—
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.51 g
14
HM62V8512B Series
Package Dimensions (cont.)
HM62V8512BLRR Series (TTP-32DR)
Unit: mm
20.95
21.35 Max
1
16
17
32
1.27
*0.42 ± 0.08
0.40 ± 0.06
M
0.21
0.80
11.76 ± 0.20
1.15 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
EIAJ
TTP-32DR
Conforms
—
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.51 g
15
HM62V8512B Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
: http:semiconductor.hitachi.com/
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
Asia (Taiwan)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/index.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
Hitachi Europe GmbH
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
16
HM62V8512B Series
Revision Record
Rev. Date
Contents of Modification
Drawn by Approved by
0.0
0.1
Apr. 24, 1998 Initial issue
Nov. 19, 1998 DC Characteristics
CC1 max: 30 mA to 40 mA
SB1 max: 20/2 µA to 40/20 µA
Low VCC Data Retention Characteristics
CCDR max: 10/1 µA to 20/10 µA
M. Higuchi K. Imato
S. Kunito
K. Imato
I
I
I
Change of note1 and 2
1.0
Dec. 17, 1998 Deletion of Preliminary
Features
S. Kunito
K. Imato
Change of Power dissipation
Active: TBD (typ) to 15 mW/MHz (typ)
Standby: TBD (typ) to 3 µW (typ)
DC Characteristics
I
I
CC2 typ: TBD to 5 mA
SB1 typ: TBD/TBD to 1/1 µA
Low VCC Data Retention Characteristics
CCDR typ: TBD/TBD to 0.8/0.8 µA
I
2.0
3.0
Jan. 29, 1999 Low VCC Data Retention Characteristics
Change of Low VCC Data Retention Timmng Waveform
S. Kunito
S. Kunito
K. Imato
K. Imato
Apr. 8, 1999
Addition of L-UL-version
DC Characteristics
I
I
SB1 typ: 1/1 µA to 1/1/1 µA
SB1 max: 40/20 µA to 40/20/5 µA
Addition of note4
Low VCC Data Retention Characteristics
I
I
CCDR typ: 0.8/0.8 µA to 0.8/0.8/0.8 µA
CCDR max: 20/10 µA to 20/10/2 µA
Addition of note3
4.0
5.0
6.0
Aug. 24, 1999 Low VCC Data Retention Characteristics
Correct error: tR unit ms to ns
S. Kunito
K. Imato
Oct. 20, 1999 Low VCC Data Retention Characteristics
I. Ogiwara K. Imato
Change of Low VCC Data Retention Timmng Waveform
Mar. 31, 2000 AC Characteristics
Test Conditions: Output timing reference level
0.8 V/2.0 V to 1.5 V/1.5 V (HM62V8512B-7)
0.8 V/2.0 V (HM62V8512B-8)
17
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