HM62W16255HJP-10 [HITACHI]
Cache SRAM, 256KX16, 10ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44;
| 型号： | HM62W16255HJP-10 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Cache SRAM, 256KX16, 10ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44 输入元件 静态存储器 光电二极管 输出元件 内存集成电路 |
| 文件： | 总16页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62W16255H Series
262114-word × 16-bit High Speed CMOS Static RAM
ADE-203-751 (Z)
Preliminary
Rev. 0.0
Feb. 27, 1997
Description
The HM62W16255H is an asynchronous high speed static RAM organized as 256-kword × 16-bit. It has
realized high speed access time (10/12/15 ns) with employing 0.35 µm CMOS process and high speed circuit
designing technology. It is most appropriate for the application which requires high speed, high density
memory and wide bit width configuration, such as cache and buffer memory in system. The HM62W16255H
is packaged in 400-mil 44-pin SOJ for high density surface mounting.
Features
•
•
•
Single supply : 3.3 V ± 0.3V
Access time: 10 ns/12 ns/15 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
•
•
All inputs and outputs
•
•
400-mil 44-pin SOJ package
Center VCC and VSS type pinout
Ordering Information
Type No.
Access time
Package
HM62W16255HJP-10
HM62W16255HJP-12
HM62W16255HJP-15
10 ns
12 ns
15 ns
400-mil 44-pin plastic SOJ (CP-44D)
HM62W16255HLJP-10
HM62W16255HLJP-12
HM62W16255HLJP-15
10 ns
12 ns
15 ns
Preliminary: This document contains information on a new product. Specifications and information contained
herein are subject to change without notice.
HM62W16255H Series
Pin Arrangement
HM62W16255HJP/HLJP Series
A0
A1
A2
A3
A4
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
CS
LB
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A5
I/O16
I/O15
I/O14
I/O13
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
A6
A7
A8
A9
(Top View)
Pin Description
Pin name
A0 – A17
I/O1 – I/O16
CS
Function
Address input
Data input/output
Chip select
OE
Output enable
Write enable
Upper byte select
Lower byte select
Power supply
Ground
WE
UB
LB
VCC
VSS
NC
No connection
2
HM62W16255H Series
Block Diagram
(LSB)
A0
VCC
A1
A2
A3
A4
A5
A6
Memory matrix
256 rows ×
1024 columns × 16 bit
(4,194,304 bits)
VSS
Row
decoder
A7
(MSB)
CS
I/O1
.
Column I/O
.
.
Input
data
control
Column decoder
I/O8
CS
I/O9
.
.
.
I/O16
A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
WE
CS
LB
UB
OE
CS
Function Table
CS OE WE LB UB Mode
VCC current I/O1–I/O8
I/O9–I/O16
High-Z
High-Z
Output
High-Z
Output
High-Z
Input
Ref. cycle
—
H
L
L
L
L
L
L
L
L
L
×
H
L
L
L
L
×
×
×
×
×
×
×
Standby
ISB, ISB1
ICC
ICC
High-Z
High-Z
Output
Output
High-Z
High-Z
Input
H
H
H
H
H
L
×
×
Output disable
Read
—
L
L
Read cycle
Read cycle
Read cycle
—
L
H
L
Lower byte read ICC
Upper byte read ICC
H
H
L
H
L
—
ICC
ICC
Write
Write cycle
Write cycle
Write cycle
—
L
L
H
L
Lower byte write ICC
Upper byte write ICC
Input
High-Z
Input
L
H
H
High-Z
High-Z
L
H
—
ICC
High-Z
Note: ×: H or L
3
HM62W16255H Series
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
V
Supply voltage relative to VSS
Voltage on any pin relative to VSS
Power dissipation
–0.5 to +4.6
–0.5*1 to VCC + 0.5
1.0*2 /1.5*3
0 to +70
VT
V
PT
W
Operating temperature
Storage temperature
Topr
Tstg
Tbias
°C
°C
°C
–55 to +125
–10 to +85
Storage temperature under bias
Notes: 1. VT (min) = –2.5 V for pulse width (under shoot) ≤ 10 ns
2. At still air condition
3. At air flow ≥ 1.0 m/s
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC*2
VSS*3
VIH
Min
3.0
Typ
3.3
0
Max
3.6
Unit
Supply voltage
V
V
V
V
0
0
Input voltage
2.2
–0.3*1
—
VCC + 0.3
0.8
VIL
—
Notes: 1. –2.0 V for pulse width (under shoot) ≤ 10 ns
2. The supply voltage with all VCC pins must be on the same level.
3. The supply voltage with all VSS pins must be on the same level.
4
HM62W16255H Series
DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter
Symbol Min
Typ*1
—
Max
2
Unit Test conditions
Input leakage current
|ILI|
—
—
µA
µA
Vin = VSS to VCC
Vin = VSS to VCC
Output leakage
current*1
|ILO|
—
2
Operating power
supply current
10 ns cycle ICC
—
—
300
mA CS = VIL, Iout = 0 mA
Other inputs = VIH/VIL
12 ns cycle ICC
15 ns cycle ICC
—
—
—
—
—
—
270
250
100
Standby power supply 10 ns cycle ISB
current
mA CS = VIH,
Other inputs = VIH/VIL
12 ns cycle ISB
15 ns cycle ISB
ISB1
—
—
—
—
—
—
100
100
10
mA
VCC ≥ CS ≥ VCC – 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
—*2
—
—*2
—
0.5*2
0.4
—
Output voltage
VOL
VOH
V
V
IOL = 8 mA
2.4
—
IOH = –4 mA
Note: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for L-version.
Capacitance (Ta = 25°C, f = 1.0 MHz)
Parameter
Symbol
Cin
Min
—
Typ
—
Max
6
Unit
Test conditions
Vin = 0 V
Input capacitance*1
Input/output capacitance*1
pF
pF
CI/O
—
—
8
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
5
HM62W16255H Series
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
3.3 V
319Ω
Dout
Dout
353Ω
Zo=50 Ω
RL=50 Ω
30 pF
5 pF
1.5 V
Output load (B)
(for tCLZ, tOLZ, tLBLZ, tUBLZ, tCHZ, tOHZ
Output load (A)
,
t
LBHZ, tUBHZ, tWHZ, and tOW)
Read Cycle
HM62W16255H
-10
Min
10
—
—
—
—
3
-12
Max Min
-15
Parameter
Symbol
Max Min
Max Unit Notes
Read cycle time
tRC
—
10
10
5
12
—
—
—
—
3
—
12
12
6
15
—
—
—
—
3
—
15
15
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
tAA
Chip select access time
tACS
Output enable to output valid
Byte select to output valid
Output hold from address change
Chip select to output in low-Z
Output enable to output in low-Z
Byte select to output in low-Z
Chip deselect to output in high-Z
Output disable to output in high-Z
Byte deselect to output in high-Z
tOE
tLB, tUB
tOH
5
6
8
—
—
—
—
5
—
—
—
—
6
—
—
—
—
8
tCLZ
3
3
3
1
1
1
1
1
1
tOLZ
0
0
0
tLBLZ, tUBLZ
tCHZ
0
0
0
—
—
—
—
—
—
—
—
—
tOHZ
5
6
8
tLBHZ, tUBHZ
5
6
8
6
HM62W16255H Series
Write Cycle
HM62W16255H
-10
Min
10
6
-12
Max Min
-15
Parameter
Symbol
tWC
Max Min
Max Unit Notes
Write cycle time
—
—
—
—
—
—
—
—
—
—
5
12
8
—
—
—
—
—
—
—
—
—
—
6
15
10
10
10
10
0
—
—
—
—
—
—
—
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to end of write
Chip select to end of write
Write pulse width
tAW
tCW
6
8
8
tWP
6
8
7
Byte select to end of write
Address setup time
tLBW, tUBW
tAS
6
8
9, 10
0
0
5
6
Write recovery time
tWR
0
0
0
Data to write time overlap
Data hold from write time
Write disable to output in low-Z
Output disable to output in high-Z
Write enable to output in high-Z
tDW
5
6
8
tDH
0
0
0
tOW
3
3
3
1
1
1
tOHZ
tWHZ
—
—
—
—
—
—
5
6
8
Notes: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled
and not 100% tested.
2. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the
WE transition, output remains a high impedance state.
3. WE and/or CS must be high during address transition time.
4. If CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
5. tAS is measured from the latest address transition to the latest of CS, WE, LB or UB going low.
6. tWR is measured from the earliest of CS, WE, LB or UB going high to the first address transition.
7. A write occurs during the overlap of low CS, low WE and low LB or low UB.
8. tCW is measured from the later of CS going low to the end of write.
9. tLBW is measured from the later of LB going low to the end of write.
10. tUBW is measured from the later of UB going low to the end of write.
7
HM62W16255H Series
Timing Waveforms
Read Timing Waveform (1) (WE = VIH)
tRC
Address
Valid address
tAA
tACS
CS
OE
LB
1
1
*
tCHZ
tOE
tOHZ
*
tLB
1
1
tLBHZ
*
tUB
UB
tUBHZ
*
1
tLBLZ
*
4
4
*
*
High Impedance
Dout
(Lower byte)
Valid data
1
tUBLZ
*
tOH
1
tOLZ
*
1
tCLZ
*
4
4
*
*
High Impedance
Dout
(Upper byte)
Valid data
8
HM62W16255H Series
Read Timing Waveform (2) (WE = VIH, LB = VIL, UB, = VIL)
tRC
Address
Valid address
tAA
tOH
1
tCHZ
*
tACS
CS
OE
1
tOE
tOHZ
*
1
tOLZ
*
1
tCLZ
*
4
4
*
*
High Impedance
Dout
(Lower/Upper
byte)
Valid data
9
HM62W16255H Series
Write Timing Waveform (1) (LB, UB Controlled)
tWC
Valid address
Address
tAW
tWR
tAS
tWP
WE*3
CS*3
tCW
OE
LB
tLBW
tUBW
UB
tOLZ
tOW
tWHZ
tOHZ
High impedance
High impedance
Dout
(Lower byte)
Dout
(Upper byte)
tDW
tDH
Valid data
tDH
Valid data
Din
(Lower byte)
tDW
Din
(Upper byte)
10
HM62W16255H Series
Write Timing Waveform (2) (WE Controlled)
tWC
Valid address
Address
tWR
tAW
tAS
tWP
WE*3
CS*3
tCW
OE
tUBW
tLBW
LB, UB
tOLZ
tOW
tWHZ
tOHZ
High impedance
Dout
(Lower/Upper
byte)
2
*
tDW
tDH
Valid data
Din
(Lower/Upper
byte)
11
HM62W16255H Series
Write Timing Waveform (3) (CS Controlled)
tWC
Valid address
Address
tWR
tAW
tAS
tWP
WE *3
CS *3
tCW
OE
tUBW
tLBW
LB, UB
tOLZ
tOW
tWHZ
tOHZ
4
*
High impedance
Dout
(Lower/Upper
byte)
2
*
tDW
tDH
Valid data
Din
(Lower/Upper
byte)
12
HM62W16255H Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter
Symbol
Min
Typ*1 Max Unit Test conditions
VCC for data retention
VDR
2.0
—
—
V
VCC ≥ CS ≥ VCC – 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Data retention current
ICCDR
—
2
300
µA
VCC = 3 V
V
CC ≥ CS ≥ VCC – 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Chip deselect to data retention time
Operation recovery time
tCDR
tR
0
5
—
—
—
—
ns
See retention waveform
ms
Note: 1. Typical values are at VCC = 3.0 V, Ta = 25˚C, and not guaranteed.
Low VCC Data Retention Timing Waveform
Data retention mode
tCDR
tR
VCC
3.0 V
VDR
2.2 V
CS
0 V
VCC ≥ CS ≥ VCC – 0.2 V
13
HM62W16255H Series
Package Dimensions
HM62W16255HJP/HLJP Series (CP-44D)
Unit: mm
28.33
28.90 Max
44
23
22
1
0.74
1.30 Max
1.27
9.40 ± 0.25
CP-44D
0.43 ± 0.10
0.41 ± 0.08
Hitachi Code
JEDEC Code
EIAJ Code
Weight
0.10
MO-061-AE
—
1.8 g
14
HM62W16255H Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other
reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such
use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested
to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Tel: 415-589-8300
Fax: 535-1533
Fax: 415-583-4207
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Berkshire SL6 8YA
United Kingdom
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 0628-585000
Fax: 0628-778322
Tel: 27359218
Fax: 27306071
15
HM62W16255H Series
Revision Record
Rev. Date
0.0 Feb. 28, 1997
Contents of Modification
Initial issue
Drawn by Approved by
16
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