HM62W1664HLJP-45 [HITACHI]
Cache SRAM, 64KX16, 45ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44;
| 型号： | HM62W1664HLJP-45 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Cache SRAM, 64KX16, 45ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62W1664H Series
65536-word × 16-bit High Speed CMOS Static RAM
Description
The HM62W1664H is an asynchronous 3.3 V operation high speed static RAM organized as 64-kword × 16-
bit. It realizes high speed access time (30/35/45 ns) with employing 0.8 µm CMOS process and high speed
circuit designing technology. It is most appropriate for the application which requires high speed, high
density memory and wide bit width configuration, such as cache and buffer memory in system. The
HM62W1664H is packaged in 400-mil 44-pin SOJ for high density surface mounting.
Features
•
•
•
Single 3.3 V supply: 3.3 V ± 0.3 V
Access time 30/35/45 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly CMOS compatible
All inputs and outputs
•
•
•
•
400-mil 44-pin SOJ
Center VCC and VSS type pinout
Ordering Information
Type No.
Access Time
Package
HM62W1664HJP-30
HM62W1664HJP-35
HM62W1664HJP-45
30 ns
35 ns
45 ns
400-mil 44-pin plastic SOJ (CP-44D)
HM62W1664HLJP-30
HM62W1664HLJP-35
HM62W1664HLJP-45
30 ns
35 ns
45 ns
HM62W1664H Series
Pin Arrangement
HM62W1664HJP
1
44
A5
A4
2
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A6
A3
3
A7
A2
4
OE
A1
5
UB
A0
6
LB
CS
7
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
I/O1
I/O2
I/O3
I/O4
V CC
V SS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A8
A9
A10
A11
NC
(Top view)
2
HM62W1664H Series
Pin Description
Pin Name
A0 – A15
I/O1 – I/O8
I/O9 – I/O16
CS
Function
Address
Input/output (lower byte)
Input/output (upper byte)
Chip select
LB
Lower byte select
Upper byte select
Write enable
UB
WE
OE
Output enable
Power supply
Ground
VCC
VSS
NC
No connection
3
HM62W1664H Series
Block Diagram
A4
A3
A2
A1
A0
A7
A6
A5
VCC
VSS
Memory Matrix
256 rows x
256 x 16/18 columns
Row
Decoder
CS
I/O1
.
Column I/O
.
.
Input
Data
Control
Column Decoder
I/O8
CS
I/O9
.
.
.
I/O16
A12 A11 A10 A15 A14 A13 A9 A8
WE
CS
LB
UB
OE
CS
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
V
Supply voltage relative to VSS
Voltage on any pin relative to VSS
Power dissipation
–0.5 to +4.6
–0.5 *1 to VCC + 0.5
1.0
VT
V
PT
W
Operating temperature
Storage temperature
Topr
Tstg
Tbias
0 to +70
°C
°C
°C
–55 to +125
–10 to +85
Storage temperature under bias
Note: 1. –2.5 V for pulse width (under shoot) ≤ 10 ns
4
HM62W1664H Series
Function Table
CS
H
L
OE
X
H
L
WE
X
LB
X
X
L
UB
X
X
L
VCC Current
I/O(Lower Byte)
High-Z
High-Z
Output
Output
High-Z
High-Z
Input
I/O(Upper Byte)
High-Z
High-Z
Output
High-Z
Output
High-Z
Input
Ref. Cycle
—
ISB, ISB1
ICC
H
H
H
H
H
L
—
L
ICC
Read cycle
Read cycle
Read cycle
—
L
L
L
H
L
ICC
L
L
H
H
L
ICC
L
L
H
L
ICC
L
X
X
X
X
ICC
Write cycle
Write cycle
Write cycle
—
L
L
L
H
L
ICC
Input
High-Z
Input
L
L
H
H
ICC
High-Z
High-Z
L
L
H
ICC
High-Z
Note: X: H or L
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Supply voltage*2
Symbol
VCC
Min
3.0
Typ
3.3
0
Max
3.6
Unit
V
VSS
0
0
V
Input voltage
VIH
2.0
–0.3 *1
—
VCC + 0.3
0.8
V
VIL
—
V
Notes: 1. –2.0 V for pulse width (under shoot) ≤ 10 ns
2. The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
5
HM62W1664H Series
DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter
Input leakage current |ILI|
Symbol Min Typ*1 Max Unit Test Conditions
Note
—
—
—
—
2
2
µA
µA
Vin = VSS to VCC
VI/O = VSS to VCC
Output leakage
current
|ILO|
Operating power
supply current
ICC
—
80
110 mA 30 ns cycle
100 mA 35 ns cycle
CS = VIL, Iout = 0 mA
Other inputs = VIH/VIL
—
—
—
70
60
18
90
35
mA 45 ns cycle
mA 30 ns cycle
Standby power
supply current
ISB
CS = VIH,
Other inputs = VIH/VIL
—
—
—
15
13
—
30
25
1
mA 35 ns cycle
mA 45 ns cycle
Standby power
supply current (1)
ISB1
mA VCC ≥ CS ≥ VCC – 0.2 V,
0 V ≤ Vin ≤ 0.2 V or
VCC ≥ Vin ≥ VCC – 0.2 V
—
—
—
—
—
—
—
0.15 mA
L-version
Output voltage
VOL1
VOL2
VOH1
0.2
0.4
—
V
V
V
IOL1 = 0.1 mA
IOL2 = 2 mA
VCC
IOH1 = –0.1 mA
–0.2
VOH2
2.4
—
—
V
IOH2 = –2 mA
Note: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and specified loading.
Capacitance (Ta = 25°C, f = 1.0 MHz)*1
Parameter
Symbol
Cin
Min
—
Typ
—
Max
6
Unit
pF
Test Conditions
Vin = 0 V
Input capacitance
Input/output capacitance
CI/O
—
—
8
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
6
HM62W1664H Series
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 2.4 V / 0.4 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.4 V
Output load: See figures
Dout
Dout
500
Ω
500
Ω
30 pF*1
5 pF*1
1.4 V
1.4 V
Output load (A)
Output load (B)
(for tCLZ, tOLZ, tLBLZ, tUBLZ, tCHZ, tOHZ
,
Note: 1. Including scope and jig
t
LBHZ, tUBHZ, tWHZ, and tOW
)
Read Cycle
HM62W1664H
-30
-35
-45
Parameter
Symbol
tRC
Min
30
—
—
—
—
5
Max Min
Max Min
Max Unit Note
Read cycle time
—
30
30
15
15
—
—
—
—
12
12
12
35
—
—
—
—
5
—
35
35
20
20
—
—
—
—
12
12
12
45
—
—
—
—
5
—
45
45
25
25
—
—
—
—
12
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
tAA
Chip select access time
tACS
tOE
Output enable to output valid
Byte select to output valid
Output hold from address change
Chip select to output in low-Z
Output enable to output in low-Z
Byte select to output in low-Z
Chip deselect to output in high-Z
Output disable to output in high-Z
Byte deselect to output in high-Z
t
LB, tUB
tOH
tCLZ
tOLZ
5
5
5
1
1
1
1
1
1
1
1
1
t
LBLZ,tUBLZ
1
1
1
tCHZ
tOHZ
—
—
—
—
—
—
—
—
—
t
LBHZ, tUBHZ
Note: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled
and not 100% tested.
7
HM62W1664H Series
Read Timing Waveform (WE = VIH)
t RC
Address
Valid address
tAA
tOH
tCHZ
tACS
CS
OE
tOE
tOHZ
t
LBHZ, tUBHZ
t
LB, tUB
LB, UB
tOLZ
,
t
LBLZ , tUBLZ
t CLZ
High Impedance *1
Dout
Valid data
Note: 1. When CS, OE and LB are low, Dout (lower byte) is low impedance.
When CS, OE and UB are low, Dout (upper byte) is low impedance.
8
HM62W1664H Series
Write Cycle
HM62W1664H
-30
-35
Min
35
25
25
25
25
0
-45
Parameter
Symbol Min
Max
—
—
—
—
—
—
—
—
—
—
12
Max
—
—
—
—
—
—
—
—
—
—
12
Min
45
30
30
30
30
0
Max
—
—
—
—
—
—
—
—
—
—
12
Unit Notes
Write cycle time
tWC
tAW
tCW
tWP
30
20
20
20
ns
ns
ns
ns
ns
Address valid to end of write
Chip select to end of write
Write pulse width
Byte select to end of write
Address setup time
tLBW, tUBW 20
tAS
0
ns
ns
ns
ns
ns
ns
2
3
Write recovery time
Data to write time overlap
Data hold from write time
tWR
tDW
tDH
0
0
0
15
0
20
0
25
0
Write disable to output in low-Z tOW
Write enable to output in high-Z tWHZ
5
5
5
4
4
—
—
—
Notes: 1. A write occurs during the overlap of low CS, low WE and low LB or low UB.
2. tAS is measured from the latest address transition to the latest of CS, WE, LB or UB going low.
3. tWR is measured from the earliest of CS, WE, LB or UB going high to the first address transition.
4. Transition is measured ±200 mV from high impedance state’s voltage with Load (B). This
parameter is sampled and not 100% tested.
9
HM62W1664H Series
Write Timing Waveform (1) (WE Controlled)
t WC
Valid address
Address
tAW
tWR
tAS
tWP
WE *1
tCW
CS
tLBW, tUBW
UB, LB
tWHZ
tOW
Dout
Din
tDW
tDH
*2
*2
Valid data
Notes: 1. WE must be high during address transition except when the device is disabled
with CS, LB or UB.
2. If CS, OE, LB and UB are low during this period, I/O pins are in the output state.
Then, the data input signals of opposite phase to the outputs must not be applied to them.
10
HM62W1664H Series
Write Timing Waveform (2) (CS Controlled)
tWC
Valid address
Address
tAW
tWR
tWP
WE
tCW
CS
tAS
tLBW , tULB
LB, UB
tDW
tDH
*1
*1
Din
Valid data
Note: 1. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after
the WE transition, output remains a high impedance state.
11
HM62W1664H Series
Write Timing Waveform (3) (LB, UB Controlled)
tWC
Valid address
Address
tAW
tWR
tWP
WE
tCW
CS
tLBW
t
UBW
,
LB, UB
tAS
tDW
tDH
*1
*1
Din
Valid data
Note: 1. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after
the WE transition, output remains a high impedance state.
12
HM62W1664H Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter
Symbol
Min
Typ
Max Unit Test Conditions
VCC for data retention
VDR
2.0
—
—
V
VCC ≥ CS ≥ VCC – 0.2 V,
VCC ≥ Vin ≥ VCC – 0.2 V or
0 V ≤ Vin ≤ 0.2 V
Data retention current
ICCDR
tCDR
tR
—
0
2
80*1
—
µA
ns
Chip deselect to data retention time
Operation recovery time
Note: 1. VCC = 3.0 V
—
—
5
—
ms
Low VCC Data Retention Timing Waveform
Data retention mode
tR
tCDR
VCC
4.5 V
2.2 V
VDR
CS > VCC – 0.2 V
CS
0 V
13
HM62W1664H Series
Package Dimension
HM62W1664HBJP/HBLJP Series (CP-44D)
Unit: mm
28.33
28.90 Max
44
23
22
1
0.74
1.30 Max
1.27
0.43 ± 0.10
9.40 ± 0.25
0.10
14
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