HM62W8128BLFP-10 [HITACHI]

Standard SRAM, 128KX8, 100ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SOP-32;


型号：	HM62W8128BLFP-10
厂家：	HITACHI SEMICONDUCTOR
描述：	Standard SRAM, 128KX8, 100ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SOP-32 静态存储器光电二极管内存集成电路
文件：	总17页 (文件大小：99K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HM62W8128B Series

131,072-word × 8-bit High Speed CMOS Static RAM

ADE-203-656A (Z)

Rev. 1.0

Oct. 14, 1996

Description

The Hitachi HM62W8128B is a CMOS static RAM organized 131,072-word × 8-bit. It realizes higher

density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS shrink process

technology. It offers low power standby power dissipation; therefore, it is suitable for battery backup

systems. The device, packaged in a 525-mil SOP (460-mil body SOP) or a 8 mm × 20 mm TSOP with

thickness of 1.2 mm, is available for high density mounting. TSOP package is suitable for cards, and reverse

type TSOP is also provided.

Features

•

Single 3.3 V supply

Fast access time: 100/120 ns (max)

Power dissipation:

Active: 23 mW/MHz (typ)

Standby: 4 µW (typ)

•

Completely static memory. No clock or timing strobe required

Equal access and cycle times

Common data input and output. Three state output

Directry CMOS compatible all inputs and outputs.

Capability of battery backup operation. 2 chip selection for battery backup

HM62W8128B Series

Ordering Information

Type No.

Access time

Package

HM62W8128BLFP-10

HM62W8128BLFP-12

100 ns

120 ns

525-mil 32-pin plastic SOP (FP-32D)

HM62W8128BLFP-10SL 100 ns

HM62W8128BLFP-12SL 120 ns

HM62W8128BLT-10

HM62W8128BLT-12

100 ns

120 ns

8 mm × 20 mm 32-pin TSOP (normal-bend type) (TFP-32D)

8 mm × 20 mm 32-pin TSOP (reverse-bend type) (TFP-32DR)

HM62W8128BLT-10SL

HM62W8128BLT-12SL

100 ns

120 ns

HM62W8128BLR-10

HM62W8128BLR-12

100 ns

120 ns

HM62W8128BLR-10SL

HM62W8128BLR-12SL

100 ns

120 ns

HM62W8128B Series

Pin Arrangement

HM62W8128BLT Series (Normal Type TSOP)

A11

A10

CS1

I/O7

I/O6

I/O5

I/O4

I/O3

V_SS

I/O2

I/O1

I/O0

HM62W8128BLFP Series

A13

CS2

A15

V_CC

A16

A14

A12

V_CC

A15

CS2

A13

A16

A14

A12

A11

(Top view)

A10

CS1

I/O7

I/O6

I/O5

I/O4

I/O3

HM62W8128BLR Series (Reverse Type TSOP)

I/O0

I/O1

I/O2

V_SS

A12

A14

A16

V_CC

A15

CS2

A13

I/O0

I/O1

I/O2

V_SS

I/O3

I/O4

I/O5

I/O6

I/O7

CS1

A10

(Top view)

A11

(Top view)

Pin Description

Pin name

A0 to A16

I/O0 to I/O7

CS1

Function

Address input

Data input/output

Chip select 1

Chip select 2

Write enable

Output enable

No connection

Power supply

Ground

CS2

V_CC

V_SS

HM62W8128B Series

Block Diagram

LSB

V _CC

V _SS

A13

•

Memory matrix

512 x 2,048

Row

decoder

A12

A14

A15

MSB

I/O0

I/O7

•

Column I/O

Input

data

control

Column decoder

LSB

MSB

A0 A1 A2 A3 A10 A11 A9 A16

•

CS2

CS1

Timing pulse generator

Read/Write control

HM62W8128B Series

Function Table

CS1

CS2

Mode

V_CCcurrent

I_SB, I_SB1

I_CC

I/O pin

High-Z

Dout

Ref. cycle

—

Standby

Output disable

Read

—

I_CC

Read cycle

Write cycle (1)

Write cycle (2)

Write

I_CC

Din

Write

I_CC

Din

Note: ×: H or L

Absolute Maximum Ratings

Parameter

Symbol

V_CC

Value

Unit

Power supply voltage*¹

Terminal voltage*¹

–0.5 to + 4.6

–0.5*²to V_CC+ 0.3*³

V_T

Power dissipation

P_T

1.0

°C

Operating temperature

Storage temperature

Storage temperature under bias

Notes: 1. Relative to V_SS

Topr

Tstg

Tbias

0 to +70

–55 to +125

–10 to 85

2. V_Tmin: –3.0 V for pulse half-width ≤ 30 ns

3. Maximum voltage is 4.6 V

Recommended DC Operating Conditions (Ta = 0 to +70˚C)

Parameter

Symbol

V_CC

Min

3.0

Typ

3.3

Max

3.6

Unit

Supply voltage

V_SS

Input voltage

V_IH

2.0

–0.3 *¹

—

V_CC+ 0.3

0.8

V_IL

—

Note: 1. V_ILmin: –3.0 V for pulse half-width ≤ 30 ns

HM62W8128B Series

DC Characteristics (Ta = 0 to +70°C, V_CC= 3.3 V ± 0.3 V, V_SS= 0 V)

Parameter

Symbol Min

Typ*¹

—

Max

Unit

µA

Test conditions

Input leakage current

Output leakage current

|I_LI|

—

Vin = V_SSto V_CC

|I_LO|

—

µA

CS1 = V_IHor CS2 = V_ILor

OE = V_IHor WE = V_IL,

V_I/O= V_SSto V_CC

Operating power supply

current: DC

I_CC

—

CS1 = V_IL, CS2 = V_IH,

Others = V_IH/V_IL, I_I/O= 0 mA

Operating HM62W8128B-10 I_CC1

Min. cycle, duty = 100%,

I_I/O= 0 mA, CS1 = V_IL, CS2 = V_IH,

Others = V_IH/V_IL

power

supply

current

HM62W8128B-12 I_CC1

I_CC2

—

Cycle time = 1 µs, duty = 100%,

I_I/O= 0 mA, CS1 ≤ 0.2 V,

CS2 ≥ V_CC– 0.2 V

V_IH≥ V_CC– 0.2 V, V_IL≤ 0.2 V

Standby power supply

current: DC

I_SB

—

0.5

(1) CS1 = V_IH, CS2 = V_IHor

(2) CS2 = V_IL

Standby power supply

current (1): DC

I_SB1

1.2*²

70*²

µA

0 V ≤ Vin

(1) 0 V ≤ CS2 ≤ 0.2 V or

(2) CS1 ≥ V_CC– 0.2 V,

CS2 ≥ V_CC– 0.2 V

I_SB1

V_OL

—

2.4

1.2*³

—

30*³

0.4

0.2

—

µA

Output voltage

I_OL= 2 mA

—

I_OL= 100 µA

I_OH= –2 mA

I_OH= –100 µA

V_OH

—

V_CC– 0.2 —

—

Notes: 1. Typical values are at V_CC= 3.3 V, Ta = +25°C and not guaranteed.

2. This characteristic is guaranteed only for L version.

3. This characteristic is guaranteed only for L-SL version.

Capacitance (Ta = 25°C, f = 1.0 MHz)

Parameter

Input capacitance*¹

Symbol

Min

—

Typ

—

Max

Unit

Test conditions

Vin = 0 V

Cin

Input/output capacitance*¹C_I/O

—

V_I/O= 0 V

Note: 1. This parameter is sampled and not 100% tested.

HM62W8128B Series

AC Characteristics (Ta = 0 to +70°C, V_CC= 3.3 V ±0.3 V, unless otherwise noted.)

Test Conditions

•

Input pulse levels: 0.4 V to 2.4 V

Input rise and fall time: 5 ns

Input timing reference levels: 1.4 V

output timing reference levels: 2.0 V/0.8 V

Output load (Including scope and jig)

500

Ω

Dout

50 pF

1.4 V

Read Cycle

HM62W8128B

-10

-12

Min

120

—

Parameter

Symbol

t_RC

Min

100

—

Max

—

Max

—

Unit

Notes

Read cycle time

Address access time

Chip selection to output valid

t_AA

100

120

t_CO1

t_CO2

t_OE

Output enable to output valid

Chip selection to output in low-Z

t_LZ1

—

2, 3

t_LZ2

—

Output enable to output in low-Z

t_OLZ

t_HZ1

t_HZ2

t_OHZ

t_OH

—

2, 3

Chip deselection to output in high-Z

1, 2, 3

Output disable to output in high-Z

Output hold from address change

1, 2, 3

—

HM62W8128B Series

Write Cycle

HM62W8128B

-10

-12

Min

120

Parameter

Symbol

t_WC

Min

100

Max

—

Max

—

Unit

Notes

Write cycle time

Chip selection to end of write

Address setup time

t_CW

t_AS

Address valid to end of write

Write pulse width

t_AW

t_WP

4, 13

Write recovery time

t_WR

Write to output in high-Z

Data to write time overlap

Data hold from write time

Output active from end of write

t_WHZ

t_DW

1, 2, 8

t_DH

t_OW

Output disable to output in High-Z t_OHZ

1, 2, 8

Notes: 1. t_HZ, t_OHZand t_WHZare defined as the time at which the outputs achieve the open circuit conditions and

are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. At any given temperature and voltage condition, t_HZmax is less than t_LZmin both for a given device

and from device to device.

4. A write occures during the overlap of a low CS1, a high CS2, and a low WE. A write begins at the

latest transition among CS1 going low, CS2 going high, and WE going low. A write ends at the

earliest transition among CS1 going high, CS2 going low, and WE going high. t_WPis measured

from the beginning of write to the end of write.

5. t_CWis measured from the later of CS1 going low or CS2 going high to the end of write.

6. t_ASis measured from the address valid to the beginning of write.

7. t_WRis measured from the earliest of CS1 or WE going high or CS2 going low to the end of write

cycle.

8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite phase

to the outputs must not be applied.

9. If CS1 goes low simultaneously with WE going low or after WE going low, the outputs remain in a

high impedance state.

10. Dout is the same phase of the latest written data in this write cycle.

11. Dout is the read data of next address.

12. If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the input

signals of the opposite phase to the outputs must not be applied to them.

13. In the write cycle with OE low fixed, t_WPmust satisfy the following equation to avoid a problem of

data bus contention.

_WP≥ t_DWmin + t_WHZmax

HM62W8128B Series

Timing Waveform

Read Timing Waveform (WE = V_IH)

t _RC

Address

CS1

Address Valid

t_AA

t_CO1

t_HZ1

t _LZ1

CS2

t_CO2

t_LZ2

t_HZ2

t _OE

t_OHZ

t_OH

OLZ

High Impedance

Dout

Data Valid

HM62W8128B Series

Write Timing Waveform (1) (OE Clock)

t_WC

Address Valid

t_AW

Address

t_CW

CS1

CS2

t_WR

t_WP

t_AS

t_OHZ

High Impedance

Dout

t_DW

t_DH

Din

Data Valid

HM62W8128B Series

Write Timing Waveform (2) (OE Low Fixed)

t_WC

Address

Address Valid

t_CW

t_WR

CS1

CS2

t_AW

t_WP

t_OH

t_AS

t_OW

t_WHZ

*11

*10

High Impedance

t_DWt_DH

Dout

Din

*12

Data Valid

HM62W8128B Series

Low V_CCData Retention Characteristics (Ta = 0 to +70°C)

Parameter

Symbol

Min Typ*⁴Max Unit Test conditions^*3

V_CCfor data retention

V_DR

2.0

—

Vin ≥ 0V

(1) 0 V ≤ CS2 ≤ 0.2 V or

(2) CS2 ≥ V_CC– 0.2 V

CS1 ≥ V_CC– 0.2 V

Data retention current

I_CCDR(L version)

—

50^*1µA

V_CC= 3.0 V, Vin ≥ 0V

(1) 0 V ≤ CS2 ≤ 0.2 V or

(2) CS2 ≥ V_CC– 0.2 V,

CS1 ≥ V_CC– 0.2 V

I_CCDR(L-SL version)

t_CDR

—

15^*2µA

Chip deselect to data

retention time

—

See retention waveform

Operation recovery time

t_R

—

Notes: 1. This characteristic is guaranteed only for L version, 20 µA max. at Ta = 0 to 40°C.

2. This characteristic is guaranteed only for L-SL version, 3 µA max. at Ta = 0 to 40°C.

3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls

data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If

CS1 controls data retention mode, CS2 must be CS2 ≥ V_CC– 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The

other input levels (address, WE, OE, I/O) can be in the high impedance state.

4. Typical values are at V_CC= 3.0 V, Ta = +25˚C and not guaranteed.

HM62W8128B Series

Low V_CCData Retention Timing Waveform (1) (CS1 Controlled)

Data retention mode

t_CDR

t_R

V_CC

3.0 V

2.0 V

V_DR1

CS1

0 V

≥

CS1 V_CC– 0.2 V

Low V_CCData Retention Timing Waveform (2) (CS2 Controlled)

t_CDR

Data retention mode

t_R

V_CC

3.0 V

CS2

V_DR2

0.4 V

0 V

0 V CS2 0.2 V

HM62W8128B Series

Package Dimensions

HM62W8128BLFP Series (FP-32D)

Unit: mm

20.45

20.95 Max

14.14 ± 0.30

1.42

1.0 Max

0 – 8 °

0.10

0.8

1.27

+ 0.10

– 0.05

0.40

0.15

HM62W8128BLT Series (TFP-32D)

Unit: mm

8.0

8.2 Max

0.5

0.2 ± 0.1

0.08

20.0 ± 0.2

0.45 Max

0 – 5 °

0.5 ± 0.1

0.10

HM62W8128B Series

Package Dimensions (cont.)

HM62W8128BLR Series (TFP-32DR)

Unit: mm

8.0

8.2 Max

0.50

0.20 ± 0.10

0.08

20.0 ± 0.2

0.45 Max

0 – 5 °

0.10

0.50 ± 0.10

HM62W8128B Series

When using this document, keep the following in mind:

1. This document may, wholly or partially, be subject to change without notice.

2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of

this document without Hitachi’s permission.

3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other

reasons during operation of the user’s unit according to this document.

4. Circuitry and other examples described herein are meant merely to indicate the characteristics and

performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual

property claims or other problems that may result from applications based on the examples described

herein.

5. No license is granted by implication or otherwise under any patents or other rights of any third party or

Hitachi, Ltd.

6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL

APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such

use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested

to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL

APPLICATIONS.

Hitachi, Ltd.

Semiconductor & IC Div.

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan

Tel: Tokyo (03) 3270-2111

Fax: (03) 3270-5109

For further information write to:

Hitachi America, Ltd.

Semiconductor & IC Div.

2000 Sierra Point Parkway

Brisbane, CA. 94005-1835

U S A

Hitachi Europe GmbH

Electronic Components Group

Continental Europe

Dornacher Straße 3

D-85622 Feldkirchen

München

Hitachi Europe Ltd.

Electronic Components Div.

Northern Europe Headquarters

Whitebrook Park

Lower Cookham Road

Maidenhead

Hitachi Asia Pte. Ltd.

16 Collyer Quay #20-00

Hitachi Tower

Singapore 0104

Tel: 535-2100

Tel: 415-589-8300

Fax: 535-1533

Fax: 415-583-4207

Tel: 089-9 91 80-0

Fax: 089-9 29 30 00

Berkshire SL6 8YA

United Kingdom

Hitachi Asia (Hong Kong) Ltd.

Unit 706, North Tower,

World Finance Centre,

Harbour City, Canton Road

Tsim Sha Tsui, Kowloon

Hong Kong

Tel: 0628-585000

Fax: 0628-778322

Tel: 27359218

Fax: 27306071

HM62W8128B Series

Revision Record

Rev. Date

Contents of Modification

Drawn by

Approved by

1.0

Oct. 14, 1996

Initial issue

HM62W8128BLFP-10 [HITACHI]

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