HM658512ALTT-8VT [HITACHI]
Pseudo Static RAM, 512KX8, 80ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP-32;
| 型号： | HM658512ALTT-8VT |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Pseudo Static RAM, 512KX8, 80ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP-32 存储 内存集成电路 静态存储器 光电二极管 |
| 文件： | 总22页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM658512A Series
4 M PSRAM (512-kword × 8-bit)
2 k Refresh
ADE-203-218C(Z)
Rev. 3.0
Nov. 1997
Description
The Hitachi HM658512A is a CMOS pseudo static RAM organized 512-kword × 8-bit. It realizes higher
density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS process
technology.
It offers low power data retention by self refresh mode. It also offers easy non multiplexed address
interface and easy refresh functions. HM658512A is suitable for handy systems which work with battery
back-up systems.
The device is packaged in a small 525-mil SOP (460-mil body SOP) or a 8 × 20 mm TSOP with thickness
of 1.2 mm, or a 600-mil plastic DIP. High density custom cards made of Tape Carrier Packages are also
available.
Features
•
•
Single 5 V (±10%)
High speed
Access time
CE access time: 70/80/100 ns (max)
Cycle time
Random read/write cycle time:
115/130/160 ns (min)
Low power
•
Active: 250 mW (typ)
Standby: 200 µW (typ)
Directly TTL compatible
All inputs and outputs
Simple address configuration
Non multiplexed address
Refresh cycle
•
•
•
2048 refresh cycles: 32 ms
HM658512A Series
•
Easy refresh functions
Address refresh
Automatic refresh
Self refresh
Ordering Information
Type No.
Access time
Package
HM658512ALP-7
HM658512ALP-8
HM658512ALP-10
70 ns
80 ns
100 ns
600-mil 32-pin plastic DIP (DP-32)
HM658512ALP-7V
HM658512ALP-8V
HM658512ALP-10V
70 ns
80 ns
100 ns
HM658512ALFP-7
HM658512ALFP-8
HM658512ALFP-10
70 ns
80 ns
100 ns
525-mil 32-pin plastic SOP (FP-32D)
400-mil 32-pin plastic TSOP (TTP-32D)
400-mil 32-pin plastic TSOP (TTP-32DR)
HM658512ALFP-7V
HM658512ALFP-8V
HM658512ALFP-10V
70 ns
80 ns
100 ns
HM658512ALTT-7
HM658512ALTT-8
HM658512ALTT-10
70 ns
80 ns
100 ns
HM658512ALTT-7V
HM658512ALTT-8V
HM658512ALTT-10V
70 ns
80 ns
100 ns
HM658512ALRR-7
HM658512ALRR-8
HM658512ALRR-10
70 ns
80 ns
100 ns
HM658512ALRR-7V
HM658512ALRR-8V
HM658512ALRR-10V
70 ns
80 ns
100 ns
2
HM658512A Series
Pin Arrangement
HM658512ALP/ALFP Series
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A18
A16
A14
A12
A7
2
A15
A17
WE
3
4
5
A13
A8
6
A6
7
A9
A5
8
A11
OE/RFSH
A10
CE
A4
9
A3
10
11
12
13
14
15
16
A2
A1
I/O7
I/O6
I/O5
I/O4
I/O3
A0
I/O0
I/O1
I/O2
VSS
(Top view)
HM658512ALTT Series
A18
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A16
A14
A12
A7
2
A15
A17
WE
3
4
5
A13
A8
A9
A6
6
A5
7
A4
8
A11
OE/RFSH
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A3
9
A2
10
11
12
13
14
15
16
A1
A0
I/O0
I/O1
I/O2
VSS
(Top view)
3
HM658512A Series
Pin Arrangement (cont.)
HM658512ALRR Series
VCC
A15
A18
A16
A14
A12
A7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
A17
3
WE
4
A13
5
A8
A6
6
A9
A5
7
A11
A4
8
OE/RFSH
A10
A3
9
A2
10
11
12
13
14
15
16
CE
A1
I/O7
I/O6
I/O5
I/O4
I/O3
A0
I/O0
I/O1
I/O2
VSS
(Top view)
Pin Description
Pin name
A0 to A18
I/O0 to I/O7
CE
Function
Address
Input/Output
Chip enable
OE/RFSH
WE
Output enable/Refresh
Write enable
VCC
Power supply
Ground
VSS
4
HM658512A Series
Block Diagram
A0
Address
Latch
Control
Row
Decoder
Memory Matrix
(2048 × 256) × 8
A10
Column I/O
Input
Data
Control
I/O 0
I/O 7
Column Decoder
Address Latch Control
A18
A11
Refresh
Control
CE
OE/RFSH
Timing Pulse Gen.
Read Write Control
WE
5
HM658512A Series
Pin Functions
CE: Chip Enable (Input)
CE is a basic clock. RAM is active when CE is low, and is on standby when CE is high.
A0 to A18: Address Inputs (Input)
A0 to A10 are row addresses and A11 to A18 are column addresses. The entire addresses A0 to A18
are fetched into RAM by the falling edge of CE.
OE/RFSH: Output Enable/Refresh (Input)
This pin has two functions. Basically it works as OE when CE is low, and as RFSH when CE is high
(in standby mode). After a read or write cycle finishes, refresh does not start if CE goes high while
OE/RFSH is held low. In order to start a refresh in standby mode, OE/RFSH must go high to reset the
refresh circuits of the RAM. After the refresh circuits are reset, the refresh starts when OE/RFSH goes
low.
I/O0 to I/O7: Input/Output (Inputs and Outputs) These pins are data I/O pins.
WE: Write Enable (Input)
RAM is in write mode when WE is low, and is in read mode when WE is high. I/O data is fetched into
RAM by the rising edge of WE or CE (earlier timing) and the data is written into memory cells.
Refresh
There are three refresh modes : address refresh, automatic refresh and self refresh.
(1) Address refresh: Data is refreshed by accessing all 2048 row addresses every 32 ms. A read is one
method of accessing those addresses. Each row address (2048 addresses of A0 to A10)must be read at
least once every 32 ms. In address refresh mode, OE/RFSH can remain high. In this case, the I/O pins
remain at high impedance, but the refresh is done within RAM.
(2) Automatic refresh: Instead of address refresh, automatic refresh can be used. RAM goes to automatic
refresh mode if OE/RFSH falls while CE is high and it remains low for at least tFAP. One automatic
refresh cycle is executed by one low pulse of OE/RFSH. It is not necessary to input the refresh
address from outside since it is generated internally by an on-chip address counter. 2048 automatic
refresh cycles must be done every 32 ms.
(3) Self refresh: Self refresh mode is suitable for data retention by battery. In standby mode, a self refresh
starts automatically when OE/RFSH stays low for more than 8 µs. Refresh addresses are automatically
specified by the on-chip address counter, and the refresh period is determined by the on-chip timer.
Automatic refresh and self refresh are distinguished from each other by the width of the OE/RFSH low
pulse in standby mode. If the OE/RFSH low pulse is wider than 8 µs, RAM becomes into self refresh
mode; if the OE/RFSH low pulse is less than 8 µs, it is recognized as an automatic refresh instruction.
6
HM658512A Series
At the end of self refresh, refresh reset time (tRFS) is required to reset the internal self refresh operation of
the RAM. During tRFS, CE and OE/RFSH must be kept high. If auto refresh follows self refresh, low
transition of OE/RFSH at the beginning of automatic refresh must not occur during tRFS period.
Notes on Using the HM658512A
Since pseudo static RAM consists of dynamic circuits like DRAM, its clock pins are more noise-sensitive
than conventional SRAM’s.
(1) If a short CE pulse of a width less than tCE min is applied to RAM, an incomplete read occurs and
stored data may be destroyed. Make sure that CE low pulses of less than tCE min are inhibited. Note
that a 10 ns CE low pulse may sometimes occur owing to the gate delay on the board if the CE signal is
generated by the decoding of higher address signals on the board. Avoid these short pulses.
(2) OE/RFSH works as refresh control in standby mode. A short OE/RFSH low pulse may cause an
incomplete refresh that will destroy data. Make sure that OE/RFSH low pulse of less than tFAP min are
also inhibited.
(3) tOHC and tOCD are the timing specs which distinguish the OE function of OE/RFSH from the RFSH
function. The tOHC and tOCD specs must be strictly maintained.
(4) Start the HM658512A operating by executing at least eight initial cycles (dummy cycles) at least 100
µs after the power voltage reaches 4.5 V-5.5 V after power-on.
Function Table
CE
L
OE/RFSH
WE
H
I/O pin
Dout
Mode
Read
Write
L
L
X
H
L
L
High-Z
High-Z
High-Z
High-Z
L
H
—
H
H
X
Refresh
Standby
H
X
Note: X means H or L.
7
HM658512A Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Note
Terminal voltage with respect to VSS
Power dissipation
–1.0 to +7.0
1.0
1
PT
W
Operating temperature
Storage temperature
Topr
Tstg
Tbias
0 to +70
–55 to +125
–10 to +85
°C
°C
°C
Storage temperature under bias
Note: 1. With respect to VSS
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
4.5
0
Typ
5.0
0
Max
5.5
0
Unit
V
Notes
Supply voltage
VSS
V
Input voltage
VIH
2.4
–1.0
—
6.0
0.8
V
VIL
—
V
1
Note: 1. VIL min = –3.0 V for pulse width 30 ns
8
HM658512A Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10 %, VSS = 0 V)
Parameter
Symbol Min Typ Max Unit Test conditions
Notes
Operating power supply current ICC1
Standby power supply current ISB1
ISB2
—
—
—
—
75
mA II/O = 0 mA
tcyc = min
1
2
mA CE = VIH , Vin ≥ 0 V
OE/RFSH = VIH
20
200 µA
CE ≥ VCC – 0.2 V, Vin ≥ 0 V, 1
OE/RFSH ≥ VCC – 0.2 V
100 µA
CE ≥ VCC – 0.2 V, Vin ≥ 0 V, 2
OE/RFSH ≥ VCC – 0.2 V
Operating power supply current ICC2
in self refresh mode
—
—
1
2
mA CE = VIH , Vin ≥ 0 V,
OE/RFSH = VIL
ICC3
70
40
200 µA
CE ≥ VCC – 0.2 V, Vin ≥ 0 V, 1
OE/RFSH ≤ 0.2 V
100 µA
CE ≥ VCC – 0.2 V, Vin ≥ 0 V, 2
OE/RFSH ≤ 0.2 V
Input leakage current
Output leakage current
ILI
–10
–10
—
—
10
10
µA
µA
VCC = 5.5 V, Vin = VSS to VCC
ILO
OE/RFSH = VIH
VI/O = VSS to VCC
Output voltage
VOL
VOH
—
—
—
0.4
—
V
V
IOL = 2.1 mA
IOH = –1 mA
2.4
Notes: 1. Only for L-version.
2. Only for V-version.
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Cin
Typ
—
Max
Unit
pF
Test conditions
Input capacitance
Input /output capacitance
8
Vin = 0 V
VI/O = 0 V
CI/O
—
10
pF
Note : This parameter is sampled and not 100% tested.
9
HM658512A Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
•
•
•
•
•
Input pulse levels: 0.4 V, 2.4 V
Input rise and fall time: 5 ns
Timing measurement level: 0.8 V, 2.2 V
Reference levels: VOH = 2.0 V, VOL = 0.8 V
Output load: 1 TTL Gate and CL (100 pF) (Including scope and jig)
HM658512A
-7
-8
-10
Parameter
Symbol Min Max
Min
130
—
Max
—
Min Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
s
Notes
Random read or write cycle time
Chip enable access time
Read-modify- write cycle time
Output enable access time
Chip disable to output in high-Z
Chip enable to output in low-Z
Output disable to output in high-Z
Output enable to output in low-Z
Chip enable pulse width
Chip enable precharge time
Address setup time
tRC
115
—
160
—
0
—
70
—
25
25
—
25
—
160
—
220
—
0
—
tCEA
tRWC
tOEA
tCHZ
tCLZ
tOHZ
tOLZ
tCE
80
—
100
—
180
—
30
25
—
40
25
—
0
1, 2
2
20
—
0
20
—
20
—
0
25
—
25
—
1, 2
2
0
70 n 10 µ
80 n 10 µ
100 n 10 µ
tP
35
0
—
—
—
—
—
—
—
—
40
0
—
—
—
—
—
—
—
—
50
0
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
tAS
Address hold time
tAH
20
0
20
0
25
0
Read command setup time
Read command hold time
Write command pulse width
Chip enable to end of write
tRCS
tRCH
tWP
tCW
0
0
0
25
70
0
25
80
0
30
100
0
Chip enable to output enable delay tOCD
time
Output enable hold time
tOHC
0
—
0
—
0
—
ns
10
HM658512A Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.) (cont.)
HM658512A
-7
-8
Min
20
0
-10
Parameter
Symbol Min Max
Max
—
Min Max
Unit
ns
ns
ns
ns
ns
ns
ns
s
Notes
Data in to end of write
tDW
tDH
tOW
tWHZ
tT
20
0
—
—
—
20
50
—
—
25
0
—
—
—
25
50
—
—
Data in hold time for write
Output active from end of write
Write to output in high-Z
Transition time (rise and fall)
Refresh command delay time
Refresh precharge time
—
5
5
—
5
2
—
3
—
3
20
50
—
—
3
1, 2
6
tRFD
tFP
35
35
40
40
50
40
—
Refresh command pulse width for tFAP
automatic refresh
70 n 8 µ
80 n 8 µ
80 n 8 µ
Automatic refresh cycle time
tFC
115
8
—
—
130
8
—
—
160
8
—
—
ns
Refresh command pulse width for tFAS
self refresh
µs
Refresh reset time from self refresh tRFS
600
—
—
600
—
—
600
—
—
ns
9
Refresh period
tREF
32
32
32
ms
2048
cycle
Notes: 1. tCHZ, tOHZ, tWHZ are defined as the time at which the output achieves the open circuit condition.
2. tCHZ, tCLZ, tOHZ, tOLZ, tWHZ and tOW are sampled under the condition of tT = 5 ns and not 100% tested.
3. A write occurs during the overlap of low CE and low WE. Write end is defined at the earlier of
WE going high or CE going high.
4. If the CE low transition occurs simultaneously with or from the WE low transition, the output
buffers remain in high impedance state.
5. In write cycle, OE or WE must disable output buffers prior to applying data to the device and at
the end of write cycle data inputs must be floated prior to OE or WE turning on output buffers.
During this period, I/O pins are in the output state, therefore the input signals of opposite phase
to the outputs must not be applied.
6. Transition time tT is measured between VIH (min) and VIL (max). VIH (min) and VIL (max) are
reference levels for measuring timing of input signals.
7. After power-up, pause for more than 100 µs and execute at least 8 initialization cycles.
8. 2048 cycles of burst refresh or the first cycle of distributed automatic refresh must be executed
within 15 µs after self refresh, in order to meet the refresh specification of 32 ms and 2048
cycles.
9. At the end of self refresh, refresh reset time (tRFS) is required to reset the internal self refresh
operation of the RAM. During tRFS, CE and OE/RFSH must be kept high. If automatic refresh
follows self refresh, low transition of OE/RFSH at the beginning of automatic refresh must not
occur during tRFS period.
11
HM658512A Series
Timing Waveform
Read Cycle
t
RC
t
CE
CE
t
P
t
t
AH
AS
Address
A0 to A18
Valid
t
OHC
WE
OE/RFSH
Dout
t
CEA
t
RCH
t
RCS
t
OEA
t
CHZ
t
OHZ
t
OLZ
Valid data out
12
HM658512A Series
Write Cycle (1) (OE high)
t
RC
t
CE
CE
t
P
t
t
AH
AS
Address
A0 to A18
Valid
t
CW
t
WP
WE
OE/RFSH
Din
t
OCD
t
t
DH
DW
Valid
Data in
t
WHZ
t
OLZ
t
CLZ
t
OHZ
t
OW
Dout
13
HM658512A Series
Write Cycle (2) (OE low)
t
RC
t
CE
CE
t
P
t
t
AH
AS
Address
A0 to A18
Valid
t
DH
t
CW
t
WP
WE
OE/RFSH
Din
t
OHC
t
t
DH
DW
Valid data in
t
WHZ
t
CLZ
Dout
14
HM658512A Series
Read-Modify-Write Cycle
t
RWC
t
CE
CE
t
P
t
t
AH
AS
Address
A0 to A18
Valid
t
RCH
t
RCS
t
CW
t
WP
t
CEA
WE
OE/RFSH
Din
t
t
OCD
OHC
t
t
DH
t
DW
OEA
Valid data in
t
t
CHZ
OLZ
t
OHZ
t
OW
t
CLZ
Valid
data
out
Dout
Automatic Refresh Cycle
CE
t
t
t
RFD
FC
FC
t
t
FAP
t
t
FP
FAP
FP
OE/RFSH
15
HM658512A Series
Self Refresh Cycle
CE
t
RFS
t
RFD
t
t
FAS
FP
OE/RFSH
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for V-version.
Parameter
Symbol
VDR
Min
3.0
—
Typ
—
Max
5.5
50
Unit
V
Test conditions
VCC for data retention
Self refresh current
ICCDR
—
µA
VCC = 3.0 V,
CE ≥ VCC – 0.2 V
OE/RFSH ≤ 0.2
Vin ≥ 0 V
—
—
100
µA
VCC = 5.5 V,
CE ≥ VCC – 0.2 V
OE/RFSH ≤ 0.2
Vin ≥ 0 V
Refresh setup time
tFS
tFR
0
5
—
—
—
—
ns
Operation recovery time
ms
16
HM658512A Series
Low VCC Data Retention Timing Waveform
Data Retention mode
VDR
V
4.5V
CC
Vcc-0.2V
CE
2.4V
0.8V
CE
t
RFD
t
FR
t
FP
t
t
RFS
FS
t
FAS
2.4V
0.8V
OE/RFSH
0.2V
OE/RFSH
Notes:
1. Rise time and fall time of power supply voltage must be smaller than 0.05 V/ms.
2. Keep CE ≥ VCC – 0.2 V during data retention mode.
3. Regarding tRFD, tFP, tFAS and tRFS, refer to AC characteristics.
4. Input voltage should be lower than VCC +1.5 V in data retention mode.
17
HM658512A Series
Package Dimensions
HM658512ALP Series (DP-32)
Unit: mm
41.90
42.50 Max
32
17
16
1
1.20
15.24
2.30 Max
+ 0.11
– 0.05
0.25
0.48 ± 0.10
2.54 ± 0.25
0° – 15°
Hitachi Code
JEDEC
EIAJ
DP-32
—
Conforms
Weight (reference value) 5.1 g
18
HM658512A Series
HM658512ALFP Series (FP-32D)
Unit: mm
20.45
20.95 Max
17
32
1
16
14.14 ± 0.30
1.00 Max
1.42
0° – 8°
0.10
M
0.80 ± 0.20
1.27
0.40 ± 0.08
0.15
0.38 ± 0.06
Hitachi Code
JEDEC
EIAJ
FP-32D
Conforms
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 1.3 g
19
HM658512A Series
HM658512ALTT Series (TTP-32D)
Unit: mm
20.95
21.35 Max
32
17
16
1
1.27
0.42 ± 0.08
0.40 ± 0.06
M
0.21
0.80
11.76 ± 0.20
1.15 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
EIAJ
TTP-32D
Conforms
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.51 g
20
HM658512A Series
HM658512ALRR Series (TTP-32DR)
Unit: mm
20.95
21.35 Max
1
16
17
32
1.27
0.42 ± 0.08
0.40 ± 0.06
M
0.21
0.80
11.76 ± 0.20
1.15 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
EIAJ
TTP-32DR
Conforms
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.51 g
21
HM658512A Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi Semiconductor
(America) Inc.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1897
U S A
Hitachi Europe GmbH
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Tel: 800-285-1601
Fax:303-297-0447
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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