HM9264B [HITACHI]
64 k SRAM (8-kword x 8-bit); 64K的SRAM （ 8千字×8位）
| 型号： | HM9264B |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 64 k SRAM (8-kword x 8-bit) |
| 文件： | 总14页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM9264B Series
64 k SRAM (8-kword × 8-bit)
ADE-203-618C (Z)
Rev. 3.0
Nov. 1997
Description
The Hitachi HM9264B is 64k-bit static RAM organized 8-kword × 8-bit. It realizes higher performance
and low power consumption by 1.5 µm CMOS process technology. The device, packaged in 450 mil
SOP (foot print pitch width), 600 mil plastic DIP, is available for high density mounting.
Features
•
•
High speed
Fast access time: 85/100 ns (max)
Low power
Standby: 10 µW (typ)
Operation: 15 mW (typ) (f = 1 MHz)
Single 5 V supply
•
•
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Common data input and output
Three state output
•
•
•
•
Directly TTL compatible
All inputs and outputs
Battery backup operation capability
Note: HM9264B series can't be applied for Aerospace, Aircraft, Nucleus Plants, Main Flame
Computers, Medical Life-support System, and Automobile Engine Control and Industrial
machines. (e.g. Communication Hubs, NC, and others.)
Ordering Information
Type No.
Access time
Package
HM9264BLFP-8L
HM9264BLFP-10L
85 ns
100 ns
450-mil, 28-pin plastic SOP(FP-28DA)
HM9264BLP-8L
HM9264BLP-10L
85 ns
100 ns
600-mil, 28-pin plastic DIP (DP-28)
HM9264B Series
Pin Arrangement
HM9264BLFP/BLP Series
1
2
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
28
27
26
VCC
WE
CS2
A8
3
4
25
24
5
A9
23
22
21
20
19
6
A11
OE
A10
CS1
I/O8
I/O7
I/O6
7
8
9
10
11
12
13
14
I/O1
I/O2
18
17
16
15
I/O5
I/O4
I/O3
VSS
(Top view)
Pin Description
Pin name
A0 to A12
I/O1 to I/O8
CS1
Function
Address input
Data input/output
Chip select 1
Chip select 2
Write enable
Output enable
No connection
Power supply
Ground
CS2
WE
OE
NC
VCC
VSS
HM9264B Series
Block Diagram
A11
A8
A9
A7
A12
A5
VCC
VSS
Row
decoder
Memory array
256 × 256
A6
A4
I/O1
I/O8
Column I/O
Input
data
control
Column decoder
A1 A2 A0 A10 A3
CS2
CS1
Timing pulse generator
Read, Write control
WE
OE
HM9264B Series
Function Table
WE CS1 CS2 OE
Mode
VCC current
ISB, ISB1
ISB, ISB1
ICC
I/O pin
High-Z
High-Z
High-Z
Dout
Ref. cycle
×
×
H
H
L
H
×
L
L
L
L
×
×
×
H
L
Not selected (power down)
—
L
Not selected (power down)
—
H
H
H
H
Output disable
Read
—
ICC
Read cycle (1)–(3)
Write cycle (1)
Write cycle (2)
H
L
Write
ICC
Din
L
Write
ICC
Din
Note: ×: H or L
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
V
Power supply voltage*1
Terminal voltage*1
–0.5 to +7.0
–0.5*2 to VCC + 0.3*3
1.0
VT
V
Power dissipation
PT
W
Operating temperature
Storage temperature
Storage temperature under bias
Notes: 1. Relative to VSS
Topr
Tstg
Tbias
0 to + 70
°C
°C
°C
–55 to +125
–10 to +85
2. VT min: –3.0 V for pulse half-width ≤ 50 ns
3. Maximum voltage is 7.0 V
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
4.5
0
Typ
5.0
0
Max
5.5
0
Unit
V
Supply voltage
VSS
V
Input high voltage
Input low voltage
VIH
2.2
–0.3*1
—
VCC + 0.3
0.8
V
V
VIL
—
Note: 1. VIL min: –3.0 V for pulse half-width ≤ 50 ns
HM9264B Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)
Parameter
Symbol Min Typ*1 Max Unit Test conditions
Input leakage current
Output leakage current
|ILI|
—
—
—
—
2
2
µA
µA
Vin = VSS to VCC
|ILO|
CS1 = VIH or CS2 = VIL or OE = VIH or
WE = VIL, VI/O = VSS to VCC
Operating power supply
current
ICCDC
—
—
7
15
45
mA CS1 = VIL, CS2 = VIH, II/O = 0 mA
others = VIH/VIL
Average operating power ICC1
supply current
30
mA Min cycle, duty = 100%,
CS1 = VIL, CS2 = VIH, II/O = 0 mA
others = VIH/VIL
ICC2
—
3
5
mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA
CS1 ≤ 0.2 V, CS2 ≥ VCC – 0.2 V,
VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V
Standby power supply
current
ISB
—
—
1
2
3
mA CS1 = VIH, CS2 = VIL
ISB1
50
µA
CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V or
0 V ≤ CS2 ≤ 0.2 V, 0 V ≤ Vin
Output low voltage
Output high voltage
VOL
VOH
—
—
—
0.4
—
V
V
IOL = 2.1 mA
2.4
IOH = –1.0 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
Capacitance (Ta = 25°C, f = 1.0 MHz)
Parameter
Symbol
Cin
Min
—
Typ
—
Max
5
Unit
pF
Test conditions
Vin = 0 V
Input capacitance*1
Input/output capacitance*1
CI/O
—
—
7
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
HM9264B Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 0.8 V to 2.4 V
Input and output timing reference level: 1.5 V
Input rise and fall time: 10 ns
Output load: 1 TTL Gate + CL (100 pF) (Including scope & jig)
Read Cycle
HM9264B-8L HM9264B-10L
Parameter
Symbol Min
Max
—
Min
100
—
—
—
—
10
10
5
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
tRC
85
—
—
—
—
10
10
5
Address access time
Chip select access time
tAA
85
85
85
45
—
100
100
100
50
CS1
tCO1
tCO2
tOE
CS2
Output enable to output valid
Chip selection to output in low-Z
CS1
tLZ1
tLZ2
tOLZ
tHZ1
tHZ2
tOHZ
tOH
—
2
CS2
—
—
2
Output enable to output in low-Z
—
—
2
Chip deselection in to output in high-Z CS1
CS2
0
30
30
30
—
0
35
1, 2
1, 2
1, 2
0
0
35
Output disable to output in high-Z
Output hold from address change
0
0
35
10
10
—
Notes: 1. tHZ is defined as the time at which the outputs achieve the open circuit conditions and are not
referred to output voltage levels.
2. At any given temperature and voltage condition, tHZ maximum is less than tLZ minimum both for
a given device and from device to device.
3. Address must be valid prior to or simultaneously with CS1 going low or CS2 going high.
HM9264B Series
Read Timing Waveform (1) (WE = VIH)
tRC
Address
Valid address
tAA
tCO1
CS1
tLZ1
tCO2
tHZ1
CS2
tLZ2
tOE
tHZ2
tOHZ
tOH
tOLZ
OE
High Impedance
Dout
Valid data
Read Timing Waveform (2) (WE = VIH, OE = VIL)
Address
Dout
Valid address
tAA
tOH
tOH
Valid data
HM9264B Series
Read Timing Waveform (3) (WE = VIH, OE = VIL)*3
tCO1
CS1
tHZ1
tLZ1
tHZ2
CS2
tCO2
tLZ2
Dout
Valid data
HM9264B Series
Write Cycle
HM9264B-8L HM9264B-10L
Parameter
Symbol Min
Max
—
—
—
—
—
—
30
—
—
—
30
Min
100
80
0
Max
—
—
—
—
—
—
35
—
—
—
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write cycle time
tWC
tCW
tAS
85
75
0
Chip selection to end of write
Address setup time
2
3
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
75
55
0
80
60
0
1, 9
4
Write recovery time
WE to output in high-Z
Data to write time overlap
Data hold from write time
Output active from end of write
Output disable to output in high-Z
0
0
5
40
0
40
0
tOW
tOHZ
5
5
0
0
5
Notes: 1. A write occurs during the overlap of a low CS1, and high CS2, and a high WE. A write begins
at the latest transition among CS1 going low,CS2 going high and WE going low. A write ends
at the earliest transition among CS1 going high CS2 going low and WE going high. Time tWP is
measured from the beginning of write to the end of write.
2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
5. During this period, I/O pins are in the output state, therefore the input signals of the opposite
phase to the outputs must not be applied.
6. If CS1 goes low simultaneously with WE going low after WE goes low, the outputs remain in
high impedance state.
7. Dout is the same phase of the written data in this write cycle.
8. Dout is the read data of the next address
9. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem
of data bus contention
t
WP ≥ tWHZ max + tDW min.
HM9264B Series
Write Timing Waveform (1) (OE Clock)
tWC
Address
Valid address
OE
tCW
tWR
CS1
*6
CS2
tAW
tAS
tWP
WE
tOHZ
High Impedance
tDH
Dout
tDW
High Impedance
Din
Valid data
HM9264B Series
Write Timing Waveform (2) (OE Low Fixed) (OE = VIL)
tWC
Address
CS1
Valid address
tAW
tWR
tCW
*6
CS2
WE
tWP
tAS
tOH
tOW
tWHZ
*7
*5
*8
Dout
Din
tDW
tDH
High Impedance
Valid data
HM9264B Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
Parameter
Symbol Min
Typ*1 Max Unit
Test conditions*4
VCC for data retention
VDR
2.0
—
—
V
CS1 ≥ VCC –0.2 V,
CS2 ≥ VCC –0.2 V or CS2 ≤ 0.2 V
Data retention current
ICCDR
—
1*1
25*2
µA
VCC = 3.0 V, 0 V ≤ Vin ≤ VCC
CS1 ≥ VCC –0.2 V, CS2 ≥ VCC –0.2 V
or 0 V ≤ CS2 ≤ 0.2 V
Chip deselect to data
retention time
tCDR
tR
0
—
—
—
—
ns
ns
See retention waveform
*3
Operation recovery time
tRC
Notes: 1. Reference data at Ta = 25°C.
2. 10 µA max at Ta = 0 to + 40°C.
3. tRC = read cycle time.
4. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance
state. If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2
V. The other input levels (address, WE, OE, I/O) can be in the high impedance state.
Low VCC Data Retention Timing Waveform (1) (CS1 Controlled)
tCDR
tR
Data retention mode
VCC
4.5 V
2.2 V
VDR
CS1
0 V
CS1 ≥ VCC – 0.2 V
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
Data retention mode
VCC
4.5 V
tCDR
tR
CS2
VDR
0.4 V
CS2 ≤ 0.2 V
0 V
HM9264B Series
Package Dimensions
HM9264BLFP Series (FP-28DA)
Unit: mm
18.3
18.75 Max
15
28
1
14
0.895
11.8 ± 0.3
0 – 10 °
1.0
+ 0.10
– 0.05
0.40
1.27 ± 0.10
HM9264BLP Series (DP-28)
Unit: mm
35.6
36.5 Max
28
15
14
1
1.2
1.9 Max
15.24
+ 0.11
– 0.05
0.25
2.54 ± 0.25
0.48 ± 0.10
0° – 15°
HM9264B Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part
of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any
intellectual property claims or other problems that may result from applications based on the examples
described herein.1
5. No license is granted by implication or otherwise under any patents or other rights of any third party
or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
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16 Collyer Quay #20-00
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Singapore 0104
Tel: 535-2100
Tel: 415-589-8300
Fax: 535-1533
Fax: 415-583-4207
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
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United Kingdom
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Tel: 0628-585000
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