HN29WT800R-10_技术文档

HN29WT800 Series

HN29WB800 Series

1048576-word × 8-bit / 524288-word × 16-bit CMOS Flash Memory

ADE-203-537A(Z)

Rev. 1.0

May. 9, 1997

Description

The Hitachi HN29WT800 Series, HN29WB800 Series are 1-Mword × 8-bit/512-kword × 16-bit CMOS Flash

Memory with DINOR (DIvided bitline NOR) type memory cells, that realize programming and erase

capabilities with a single 3.3 V power supply. The built-in Sequence Controller allows Automatic

Program/Erase without complex external control. HN29WT800 Series, HN29WB800 Series enable the low

power and high performance systems such as mobile, personal computing and communication products.

Features

•

On-board single power supply (V_CC): V_CC= 3.3 V ± 0.3 V

Access time: 80/100/120 ns (max)

Low power dissipation:

I_CC= 30 mA (max) (Read)

I_CC= 200 µA (max) (Standby)

I_CC= 40 mA (max) (Program)

I_CC= 40 mA (max) (Erase)

I_CC= 1 µA (typ) (Deep powerdown)

Automatic page programming:

Programming time: 25 ms (typ)

Program unit: 128 word

•

Automatic erase:

Erase time: 50 ms (typ)

Erase unit: Boot block; 8-kword/16-kbyte × 1

Parameter block; 4-kword/8-kbyte × 2

Main block;16-kword/32-kbyte × 1

32-kword/64-kbyte × 15

This product is compatible with M5M29FB/T800xx by Ltd. Mitsubishi.

HN29WT800 Series, HN29WB800 Series

•

Block boot:

HN29WT800 Series: Top boot

HN29WB800 Series: Bottom boot

Program/Erase endurance

10,000 cycles

•

Other functions:

Software command control

Selective block lock

Program suspend/Resume

Erase suspend/Resume

Status register read

•

Compatible with M5M29FB/T800xx by Ltd. Mitsubishi

Ordering Information

Type No.

Access time

Package

HN29WT800T-8

HN29WT800T-10

HN29WT800T-12

80 ns

100 ns

120 ns

12 × 20.0 mm²48-pin plastic TSOP I (TFP-48D)

HN29WB800T-8

HN29WB800T-10

HN29WB800T-12

80 ns

100 ns

120 ns

HN29WT800R-8

HN29WT800R-10

HN29WT800R-12

80 ns

100 ns

120 ns

12 × 20.0 mm²48-pin plastic TSOP I (Reverse)

(TFP-48DR)

HN29WB800R-8

HN29WB800R-10

HN29WB800R-12

80 ns

100 ns

120 ns

2

HN29WT800 Series, HN29WB800 Series

Pin Arrangement

HN29WT800T Series

HN29WB800T Series

A15

A14

A13

A12

A11

A10

A9

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE

3

V_SS

4

I/O15/A-1

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

V_CC

5

6

7

A8

8

NC

WE

RP

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

NC

WP

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

OE

RDY/Busy

A18

A17

A7

A6

A5

A4

A3

VSS

A2

CE

A1

A0

(Top view)

HN29WT800R Series

HN29WB800R Series

A16

BYTE

V_SS

1

2

48

A15

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A14

A13

A12

A11

A10

A9

3

I/O15/A-1

I/O7

4

5

I/O14

I/O6

6

7

I/O13

I/O5

8

A8

9

NC

I/O12

I/O4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

NC

WE

V_CC

RP

I/O11

I/O3

NC

WP

RDY/Busy

A18

A17

A7

I/O10

I/O2

I/O9

I/O1

I/O8

A6

I/O0

A5

OE

A4

SS

V

A3

CE

A2

A0

A1

(Top view)

3

HN29WT800 Series, HN29WB800 Series

Pin Description

Pin name

A-1 to A18

I/O0 to I/O15

CE

Function

Address

Input/output

Chip enable

Output enable

Write enable

Reset/Powerdown

Ready/Busy

Write protect

Byte enable

Power supply

Ground

OE

WE

RP

RDY/Busy

WP

BYTE

V_CC

V_SS

NC

No connection

4

HN29WT800 Series, HN29WB800 Series

Block Diagram

128-word page buffer

Boot block 8-kword

Parameter block 1 4-kword

Parameter block 2 4-kword

Main block 16-kword

Main block 32-kword

X-address

buffer

X-decorder

A8 to A18

.

Main block 32-kword

Y-address

buffer

Y-gate /Sens AMP.

Y-decorder

A0 to A7

Status/ ID register

Multiplexer

CE

OE

WE

WSM

CUI

WP

RP

Input/output buffers

BYTE

RDY/Busy

V_CC

V_SS

I/O15/A-1

I/O0

CUI: Command User Interface

WSM: Write State Machine

5

HN29WT800 Series, HN29WB800 Series

Memory Map

HN29WB800 Series Memory Map

HN29WT800 Series Memory Map

× 8 (Byte mode)

FC000H to FFFFFH

FA000H to FBFFFH

F8000H to F9FFFH

F0000H to F7FFFH

E0000H to EFFFFH

D0000H to DFFFFH

C0000H to CFFFFH

B0000H to BFFFFH

A0000H to AFFFFH

90000H to 9FFFFH

80000H to 8FFFFH

70000H to 7FFFFH

60000H to 6FFFFH

50000H to 5FFFFH

40000H to 4FFFFH

30000H to 3FFFFH

20000H to 2FFFFH

10000H to 1FFFFH

00000H to 0FFFFH

A-1 to A18 (Byte mode)

× 8 (Byte mode)

F0000H to FFFFFH

E0000H to EFFFFH

D0000H to DFFFFH

C0000H to CFFFFH

B0000H to BFFFFH

A0000H to AFFFFH

90000H to 9FFFFH

80000H to 8FFFFH

70000H to 7FFFFH

60000H to 6FFFFH

50000H to 5FFFFH

40000H to 4FFFFH

30000H to 3FFFFH

20000H to 2FFFFH

10000H to 1FFFFH

08000H to 0FFFFH

06000H to 07FFFH

04000H to 05FFFH

00000H to 03FFFH

A-1 to A18 (Byte mode)

× 16 (Word mode)

7E000H to 7FFFFH

7D000H to 7DFFFH

7C000H to 7CFFFH

78000H to 7BFFFH

70000H to 77FFFH

68000H to 6FFFFH

60000H to 67FFFH

58000H to 5FFFFH

50000H to 57FFFH

48000H to 4FFFFH

40000H to 47FFFH

38000H to 3FFFFH

30000H to 37FFFH

28000H to 2FFFFH

20000H to 27FFFH

18000H to 1FFFFH

10000H to 17FFFH

08000H to 0FFFFH

00000H to 07FFFH

A0 to A18 (Word mode)

× 16 (Word mode)

78000H to 7FFFFH

70000H to 77FFFH

68000H to 6FFFFH

60000H to 67FFFH

58000H to 5FFFFH

50000H to 57FFFH

48000H to 4FFFFH

40000H to 47FFFH

38000H to 3FFFFH

30000H to 37FFFH

28000H to 2FFFFH

20000H to 27FFFH

18000H to 1FFFFH

10000H to 17FFFH

08000H to 0FFFFH

04000H to 07FFFH

03000H to 03FFFH

02000H to 02FFFH

00000H to 01FFFH

A0 to A18 (Word mode)

8-kword boot block

32-kword main block

16-kword main block

4-kword parameter block

8-kword boot block

4-kword parameter block

16-kword main block

32-kword main block

6

HN29WT800 Series, HN29WB800 Series

Top Boot Block Address Map*¹

Address

Size

Block

A18

1

A17

1

A16

1

A15

1

A14

1

A13

1

A12

×

× 8 (Byte mode)

16-kbyte

8-kbyte

× 16 (Word mode)

8-kword

Block18

Block17

Block16

Block15

Block14

Block13

Block12

Block11

Block10

Block9

Block8

Block7

Block6

Block5

Block4

Block3

Block2

Block1

Block0

1

0

1

4-kword

1

0

8-kbyte

4-kword

1

0

×

32-kbyte

64-kbyte

16-kword

32-kword

1

0

×

1

0

1

×

1

0

×

1

0

1

×

1

0

1

0

×

1

0

1

×

1

0

×

0

1

×

0

1

0

×

0

1

0

1

×

0

1

0

×

0

1

×

0

1

0

×

0

1

×

0

×

Note: 1. × can be V_IH. Address except block address must be V_IH.

7

HN29WT800 Series, HN29WB800 Series

Bottom Boot Block Address Map*¹

Address

Size

Block

A18

1

A17

1

A16

1

A15

1

A14

×

A13

×

A12

×

× 8 (Byte mode)

64-kbyte

32-kbyte

8-kbyte

× 16 (Word mode)

32-kword

16-kword

4-kword

Block18

Block17

Block16

Block15

Block14

Block13

Block12

Block11

Block10

Block9

Block8

Block7

Block6

Block5

Block4

Block3

Block2

Block1

Block0

1

0

×

1

0

1

×

1

0

×

1

0

1

×

1

0

1

0

×

1

0

1

×

1

0

×

0

1

×

0

1

0

×

0

1

0

1

×

0

1

0

×

0

1

×

0

1

0

×

0

1

×

0

1

×

0

1

0

1

0

8-kbyte

4-kword

0

×

16-kbyte

8-kword

Note: 1. × can be V_IH. Address except block address must be V_IH.

8

HN29WT800 Series, HN29WB800 Series

Mode Selection

Word Mode (BYTE = V_IH)

Mode

CE

V_IL

OE

V_IL

V_IH

×*⁵

V_IH

×

WE

V_IH

×*⁵

V_IL

×

RP

V_IH

V_IL

RDY/Busy I/O0 to I/O15

Read

Array

V_OH(High-Z) Dout

Status register

×*⁵

Status Register Data

Lock bit data (I/O6)

Lock bit status

Identifier (Maker)*¹, *²V_IL

Identifier (Device)*¹, *³V_IL

×

V_OH(High-Z) 07H

V_OH(High-Z) 85H / 86H*⁶

Output disable

Standby

Command write*⁴Program

V_IL

V_IH

×

High-Z

V_IL

×

Command/Data in

Command

Erase

Others

Deep powerdown

V_OH(High-Z) High-Z

Notes: 1. The command programming mode is used to output the identifier code. Refer to the table of

Software Command Definition.

2. A0 = V_IL

3. A0 = V_IH

4. Refer to the table of Software Command Definition. Programming and erase operation begins after

mode setting by command input.

5. × can be V_ILor V_IHfor control pins, and V_OLor V_OH(High-Z) for RDY/Busypin. The RDY/Busy is an

open drain output pin and indicates status of the internal WSM. When low, it indicates the WSM is

Busy performing an operation. A pull-up resistor of 10 k to 100 k Ω is required to allow the

RDY/Busy signal to transition high indicating a Ready WSM condition.

6. 85H: HN29WT800 Series, 86H: HN29WB800 Series.

9

HN29WT800 Series, HN29WB800 Series

BYTE Mode (BYTE= V_IL)

Mode

CE

V_IL

OE

V_IL

V_IH

×*⁵

V_IH

×

WE

V_IH

×*⁵

V_IL

×

RP

V_IH

V_IL

RDY/Busy I/O0 to I/O7

Read

Array

V_OH(High-Z) Dout

Status register

×*⁵

Status Register Data

Lock bit data (I/O6)

Lock bit status

Identifier (Maker)*¹, *²V_IL

Identifier (Device)*¹, *³V_IL

×

V_OH(High-Z) 07H

V_OH(High-Z) 85H / 86H*⁶

Output disable

Standby

Command write*⁴Program

V_IL

V_IH

×

High-Z

V_IL

×

Command/Data in

Command

Erase

Others

Deep powerdown

V_OH(High-Z) High-Z

Notes: 1. The command programming mode is used to output the identifier code. Refer to the table of

Software Command Definition.

2. A0 = V_IL

3. A0 = V_IH

4. Refer to the table of Software Command Definition. Programming and erase operation begins after

mode setting by command input.

5. × can be V_ILor V_IHfor control pins, and V_OLor V_OH(High-Z) for RDY/Busypin. The RDY/Busy is an

open drain output pin and indicates status of the internal WSM. When low, it indicates the WSM is

Busy performing an operation. A pull-up resistor of 10 k to 100 k Ω is required to allow the

RDY/Busy signal to transition high indicating a Ready WSM condition.

6. 85H: HN29WT800 Series, 86H: HN29WB800 Series.

10

HN29WT800 Series, HN29WB800 Series

Software Command Definition

First bus cycle

Second bus cycle

Third bus cycle

Operation

Data

(I/O7 to Operation

Address I/O0)*¹mode

Data

(I/O7

Data

(I/O7

Operation

mode

Command

Address to I/O0) mode

Address to I/O0)

Read array (memory) Write

Read identifier codes Write

Read status register Write

Clear status register Write

×

FFH

90H

70H

50H

41H

20H

B0H

D0H

71H

77H

Read

IA*²

ID*²

SRD*³

×

Page program*⁵

Block erase

Suspend

Write

WA0*⁴

BA*⁶

WD0*⁴Write

D0H

WA1

WD1

Resume

Read lock bit status Write

Read

Write

BA

I/O6*⁷

D0H

Lock bit

Write

program/confirm

Erase all unlocked

blocks

Write

×

A7H

Write

×

D0H

Notes: 1. In the word mode, upper byte data (I/O8 to I/O15) is ignored.

2. IA = Identifier address, A0 = V_IL(Manufacture code), A0 = V_IH(Device code), ID = ID code,

BYTE = V_IL: A-1, A1 to A18 = V_IL, BYTE = V_IH: A1 to A18 = V_IL.

3. SRD = Status register data

4. WA = Write address, WD = Write data

5. BYTE = V_IL: Write address and write data must be provided sequentially from 00H to FFH for A-1

to A6. Page size is 256 byte (256-byte × 8-bit).

BYTE = V_IH: Write address and write data must be provided sequentially from 00H to 7FH for A0 to

A6. Page size is 128 word (128-word × 16-bit).

6. BA = Block address (A12 to A18), (Addresses except block address must be V_IH)

7. I/O6 provides block lock status, I/O6 = 1: Block unlocked, I/O6 = 0: Block locked.

11

HN29WT800 Series, HN29WB800 Series

Block Locking

RP

V_IL

WP

×

Lock bit (internally) Write protection provided

×

0

1

×

All blocks locked (Deep powerdown mode)

V_HH

V_IH

×

All blocks unlocked

V_IL

V_IH

Blocks locked (Depend on lock bit data)

Blocks unlocked (Depend on lock bit data)

All blocks unlocked

Note: I/O6 provided lock status of each block after writing the Read lock status command (71H). WP pin

must not be switched during performing Read/Write operations or WSM busy (WSMS = 0).

Status Register Data (SRD)

Symbol

Function

Definition

SR. 7 (I/O7)

SR. 6 (I/O6)

SR. 5 (I/O5)

SR. 4 (I/O4)

SR. 3 (I/O3)

SR. 2 (I/O2)

Write state machine status 1 = Ready

0 = Busy

Suspend status

Erase status

1 = Suspend

1 = Error

0 = Operation in progress/completed

0 = Successful

Program status

1 = Error

0 = Successful

Block status after program 1 = Error

0 = Successful

Reserved

The function and the definition for these bits are to be

determined. These bits should be masked out when the

status register is polled.

SR. 1 (I/O1)

SR. 0 (I/O0)

Reserved

Note: The RDY/Busy is an open dran output pin and indicates status of the internal WSM. When low, it

indicates that the WSM is Busy performing an operation. A pull-up resistor of 10k Ω to 100k Ω is

required to allow the RDY/Busy signal to transition high indicating a Ready WSM condition.

I/O3 indicates the block status after the page programming. When I/O3 is High, the page has the over-

programmed cell. If over-program occures, the device is block failed. However, if I/O3 is High, please

try the block erase to the block. The block may revive.

12

HN29WT800 Series, HN29WB800 Series

Device Identifier Mode

The device identifier mode allows the reading out of binary codes that identify manufacturer and type of

device, from outputs of Flash Memory. By this mode, the device will be automatically matched its own

corresponding erase and programming algorithm.

HN29WT800 Series, HN29WB800 Series Identifier Code

Pins

A0

0

I/O7

0

I/O6

0

I/O5

0

I/O4

0

I/O3

0

I/O2

1

I/O1

1

I/O0

1

Hex. data

07H

Manufacturer code

Device code (T series)

Device code (B series)

1

0

1

0

1

85H

1

0

1

0

86H

Notes: 1. Device identifier code can be read out by using the read identified codes command.

2. In the word mode, the same data as I/O7 to I/O0 is read out from I/O15 to I/O8.

3. A9 = V_HHmode. A9 = 11.5 V to 13.0 V. Set A9 to V_HHmin 200 ns before falling edge of CE in ready

status. Min 200 ns after return to V_HH, device can’t be accessed. A1 to A8, A10 to A18, CE, OE, =

V_IL, WE = V_IH, I/O15/A-1 = V_IL(BYTE = L).

Operations of the HN29WT800 Series, HN29WB800 Series

The HN29WT800 Series, HN29WB800 Series include on-chip program/erase control circuitry. The Write

State Machine (WSM) controls block erase and page program operations. Operational modes are selected by

the commands written to the Command User Interface (CUI). The Status Register indicates the status of the

WSM and when the WSM successfully completes the desired program or block erase operation. A Deep

Powerdown mode is enabled when the RP pin is at V_SSminimizing power consumption.

Read: The HN29WT800 Series, HN29WB800 Series have three read modes, which accesses to the memory

array, the Device Identifier and the Status Register. The appropriate read command are required to be written

to the CUI. Upon initial device powerup or after exit from deep powerdown, the HN29WT800 Series,

HN29WB800 Series automatically reset to read array mode. In the read array mode, low level input to CE

and OE, high level input to WE and RP, and address signals to the address inputs (A0 to A18) output the data

of the addressed location to the data input/output (I/O0 to I/O15).

Write: Writes to the CUI enable reading of memory array data, device identifiers and reading and clearing of

the Status Register, they also enable block erase and program. The CUI is written by bringing WE to low

level, while CE is at low level and OE is at high level. Addresses and data are latched on the earlier rising

edge of WE and CE. Standard micro-processor write timings are used.

Output Disable: When OE is at V_IH, output from the device is disabled. Data input/output are in a high

impedance (High-Z) state.

13

HN29WT800 Series, HN29WB800 Series

Standby: When CE is at V_IH, the device is in the standby mode and its power consumption is reduced. Data

input/output are in a high impedance (High-Z) state. If the memory is deselected during block erase or

program, the internal control circuits remain active and the device consume normal active power until the

operation completes.

Deep Powerdown: When RP is at V_IL, the device is in the deep powerdown mode and its power

consumption is substantially low. During read modes, the memory is deselected and the data input/output are

in a high impedance (High-Z) state. After return from powerdown, the CUI is reset to Read Array and the

Status Register is cleared to value 80H. During block erase or program modes, RP low will abort either

operation. Memory array data of the block being altered become invalid.

Functional Description

The device operations are selected by writing specific software command into the CUI.

Read Array Command (FFH): The device is in read array mode on initial device power up and after exit

from deep power down, or by writing FFH to the CUI. The device remains in Read Array mode until the

other commands are written.

Read Device Identifier Command (90H): Though PROM programmers can normally read device identifier

codes by raising A9 to high voltage, multiplexing high voltage onto address lines is not desired for micro-

processor system. It is an other means to read device identifier codes that Read Device Identifier Code

Command (90H) is written to the command latch. Following the write of the Read Device Identifier

command of 90H, the manufacturer code and the device code can be read from addresses 00000H and

00001H, respectively.

Read Status Register Command (70H): The Status Register is read after writing the read status register

command of 70H to the CUI. The contents of Status Register are latched on the later falling edge of OE or

CE. So CE or OE must be toggled every status read.

Clear Status Register Command (50H): The Erase Status and Program Status bits are set to High by the

Write State Machine and can be reset by the Clear Status Register command of 50H. These bits indicates

various failure conditions.

Block Erase/Confirm Command (20H/D0H): Automated block erase is initiated by writing the Block

Erase of 20H followed by the Confirm command of D0H. An address within the block to be erased is

required. The WSM executes iterative erase pulse application and erase verify operation.

Suspend/Resume Command (B0H/D0H): Writing the suspend command of B0H during block erase

operation interrupts the block erase operation and allows read out from another block of memory. Writing the

suspend command of B0H during program operation interrupts the program operation and allows read out

from another block of memory. The device continues to output status register data when read, after the

suspend command is written to it. Polling the WSM status and suspend status bits will determine when the

erase operation or program operation has been suspended. At this point, writing of the read array command to

the CUI enables reading data from blocks other than that which is suspended. When the resume command of

D0H is written to the CUI, the WSM will continue with the erase or program processes.

14

HN29WT800 Series, HN29WB800 Series

Page Program Command (41H): Page program allows fast programming of 128-word of data. Writing of

41H initiates the page program operation. From 2nd cycle to 129th cycle write data must be serially inputted.

Address A6 to A0 have to be incremented from 00H to 7FH. After completion of data loading, the WSM

controls the program pulse application and verify operation. Basically re-program must not be done on a page

which has already programmed.

Data Protection: The HN29WT800 Series, HN29WB800 Series provide selective block locking of memory

blocks. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In

addition, the HN29WT800 Series, HN29WB800 Series have a master write protect pin (WP) which prevents

any modifications to memory blocks whose lock-bits are set to Low, when WP is low. When WP is high or

RP is V_HH, all blocks can be programmed or erased regardless of the state of lock-bits, and the lock-bits are

cleared to High by erase.

Power Supply Voltage: A delay time of 2 µs is required before any device operation is initiated. The delay

time is measured from the time V_CCreaches V_CCmin (3.0 V). During powerup, RP = V_SSis recommended.

Falling in Busy status is not recommended for possibility of damaging the device.

Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

V

Notes

1

V_CCvoltage

V_CC

–0.2 to +4.6

–0.6 to +4.6

All input and output voltages except V_CC, A9, Vin, Vout

V

1, 2

RP

A9, RP supply voltage

V_HH, V_ID

Topr

–0.6 to +14.0

0 to +70

V

1, 2

Operating temperature range

Storage temperature range

Storage temperature under bias

Notes: 1. Relative to V_SS.

˚C

Tstg

–65 to +125

–10 to +80

Tbias

2. Minimum DC voltage is –0.5 V on input/output pins. During transition, this level may undershoot to

–2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins are V_CC+0.5 V which, during

transitions, may overshoot to V_CC+1.5 V for periods < 20 ns.

Capacitance (Ta = 25˚C, f = 1 MHz)

Parameter

Symbol

Cin

Min Typ Max Unit Test conditions

Input capacitance

Output capacitance

—

8

pF

Vin = 0 V

Cout

12

Vout = 0 V

15

HN29WT800 Series, HN29WB800 Series

DC Characteristics (V_CC= 3.3 V ± 0.3 V, Ta = 0 to +70˚C)

Parameter

Symbol Min

Typ

—

50

1

Max

1

Unit Test conditions

Input leakage current

Output leakage current

Standby V_CCcurrent

I_LI

–1

–10

—

µA

Vin = V_SSto V_CC

I_LO

I_SB1

I_SB2

10

200

5

Vout = V_SSto V_CC

Vin = V_IH/V_IL, CE = RP = WP = V_IH

—

Vin = V_SSor V_CC,

CE = RP = WP = V_CC± 0.3 V

Deep powerdown V_CCcurrent I_SB3

I_SB4

—

5

1

7

15

5

µA

mA

Vin = V_IH/V_IL, RP = V_IL

Vin = V_SSor V_CC, RP = V_SS± 0.3 V

Read V_CCcurrent

I_CC1

30

Vin = V_IH/V_IL, CE = V_IL,

RP = OE = V_IH, f = 10 MHz,

Iout = 0 mA

Write V_CCcurrent

I_CC2

—

30

mA

Vin = V_IH/V_IL, CE = WE = V_IL,

RP = OE = V_IH

Programming V_CCcurrent

Erasing V_CCcurrent

I_CC3

I_CC4

I_CC5

—

40

mA

µA

V

Vin = V_IH/V_IL, CE = RP = WP = V_IH

RP = V_HHmax

—

40

Suspend V_CCcurrent

—

200

100

RP all block unlocked current I_RP

A9 intelligent identifier current I_ID

A9 intelligent identifier voltage V_ID

—

A9 = V_IDmax

11.4

–0.5

2.0

—

12.0 12.6

RP unlocked voltage

V_HH

V_IL

V

Input voltage

—

0.8

V

V_IH

V_CC+ 0.5 V

Output voltage

V_OL

V_OH1

0.45

—

V

I_OL= 5.8 mA

0.85 ×

I_OH= –2.5 mA

V_CC

V_OH2

V_LKO

V_CC- 0.4 —

1.2

—

V

I_OH= –100 µA

Low V_CClock-out voltage*²

—

Notes: 1. All currents are RMS unless otherwise noted. Typical values at V_CC= 3.3 V, Ta = 25˚C.

2. To protect initiation of write cycle during V_CCpowerup/powerdown, a write cycle is locked out for V_CC

less than V_LKO. If V_CCis less than V_LKOWrite State Machine is reset to read mode. When the Wirte

State Machine is in Busy state, if V_CCis less than V_LKO, the alternation of memory contents may

occur.

16

HN29WT800 Series, HN29WB800 Series

AC Characteristics (V_CC= 3.3 V ± 0.3 V, Ta = 0 to +70˚C)

Test Conditions

•

Input pulse levels: V_IL= 0 V, V_IH= 3.0 V

Input rise and fall time: ≤ 10 ns (HN29WT/WB800-10/12 Series)

: ≤ 5 ns (HN29WT/WB800-8 Series)

Output load: 1 TTL gate +100 pF (Including scope and jig.) (HN29WT/WB800-10/12 Series)

: 1 TTL gate +30 pF (Including scope and jig.) (HN29WT/WB800-8 Series)

Reference levels for measuring timing: 1.5 V

V_CCPowerup/Powerdown Timing

Parameter

Symbol

Min

Typ

Max

Unit

RP = V_IHsetup time from V_CCmin

t_VCS

2

—

µs

Note: During powerup/powerdown, by the noise pulses on control pins, the device has possibility of

accidental erasure or programming. The device must be protected against initiation of write cycle for

memory contents during powerup/powerdown. The delay time of min 2 µs is always required before

read operation or write operation is initiated from the time V_CCreaches V_CCmin during

powerup/powerdown. By holding RP V_IL, the contents of memory is protected during V_CC

powerup/powerdown. During powerup, RP must be held V_ILfor min 2 µs from the time V_CCreaches V_CC

min. During powerdown, RP must be held V_ILuntil V_CCreaches V_SS. RP doesn’t have latch mode, so

RP must be held V_IHduring read operation or erase/program operation.

Read/Write inhibit

V_CC

t_VCS

RP

CE

t_PS

WE

17

HN29WT800 Series, HN29WB800 Series

Read Operation

HN29WT800/HN29WB800

-8

-10

Min

100

—

-12

Min

120

—

Parameter

Symbol

t_RC

Min

80

—

0

Max

—

Max

—

Max

—

Unit

ns

Read cycle time

Address to output delay

CE to output delay

OE to output delay

CE or OE high to output float *¹

Address to output hold

t_ACC

t_CE

80

40

25

—

100

50

120

60

ns

—

ns

t_OE

—

ns

t_DF

—

25

—

30

ns

t_OH

0

—

0

—

ns

OE hold from WE high Status register t_OEH

read in busy

80

—

100

—

120

—

ns

OE hold from WE high Other read

RP recovery time before read

RP low to output High-Z

t_OEH

t_PS

0

—

150

5

0

—

150

5

0

—

300

5

ns

500

—

500

—

500

—

t_PHZ

t_BCD

t_BAD

t_BYTE

t_BHZ

CE low to BYTE high or low

Address to BYTE high or low

BYTE to output delay

5

80

25

100

25

120

30

BYTE low to output High-Z

Notes: 1. t_DFis defined as the time at which the output achieves the open circuit condition and data is no

longer driven.

2. Timing measurements are made under read timing waveform.

18

HN29WT800 Series, HN29WB800 Series

Read Timing Waveform (Byte Mode or Word Mode)

Address

Address valid

t_RC

CE

t_DF

OE

t_OEH

t_OE

WE

t_CE

t_ACC

t_OH

I/O

Output valid

t_PS

t_PHZ

RP

19

HN29WT800 Series, HN29WB800 Series

Read Timing Waveform (Byte Mode, Word Mode Switch)

Address valid

A0 to A18

Address valid

t_ACC

t_DF

CE

t_CE

t_OE

t_BAD

OE

t_BYTE

t_OH

BYTE

t_BCD

t_BAD

High-Z

Output valid

Valid

t_BHZ

Output valid

I/O0 to I/O7

t_ACC

Valid

I/O8 to I/O14

I/O15/A-1

I/O15

A-1

Note: When BYTE = High, CE = OE = Low, I/O15/A-1 is output status.

At this time, input signal must not be applied.

20

HN29WT800 Series, HN29WB800 Series

Command Write Operation

HN29WT800/HN29WB800

-8

-10

-12

Parameter

Symbol Min Typ Max Min Typ Max Min Typ Max Unit

Write cycle time

Address setup time

Address hold time

Data setup time

Data hold time

t_WC

t_AS

80

50

10

50

10

0

—

25

50

—

80

600

—

100

50

10

50

10

0

—

25

50

—

80

600

—

120

50

10

50

10

0

—

25

50

—

80

ns

ms

t_AH

t_DS

t_DH

CE setup time

t_CS

CE hold time

t_CH

0

Write pulse width

Write pulse high time

WE setup time

t_WP

t_WPH

t_WS

t_WH

t_CEP

t_CEPH

t_DAP

60

20

0

60

20

0

60

20

0

WE hold time

0

CE pulse width

60

20

—

50

80

500

80

60

20

—

60

20

—

CE pulse high time

Duration of program operation

Duration of block erase operation t_DAE

—

600 ms

BYTE high or low setup time

BYTE high or low hold time

RP high recovery to WE low

t_BS

t_BH

t_PS

t_BLS

50

100

500

100

50

120

500

120

—

ns

Block lock setup to write enable

high

t_WPS

t_BLH

80

0

—

80

100

0

—

120

0

—

ns

Block lock hold from valid SRD

—

t_WPH

t_WHRL

t_EHRL

0

—

0

WE high to RDY/Busy low

CE high to RDY/Busy low

—

100

—

120 ns

Note: Read operation parameters during command write operations mode are the same as during read timing

waveform. Typical values at V_CC= 3.3 V, Ta = 25˚C.

21

HN29WT800 Series, HN29WB800 Series

Erase and Program Performance

Parameter

Min

—

Typ

6.4

25

Max

20.4

80

Unit

s

Main block write time (Page mode)

Page write time

—

ms

Block erase time

—

50

600

Note: Typical values at V_CC= 3.3 V, Ta = 25˚C. These values exclude system level overhead.

Page Program Timing Waveform (WE control)

Read status

Write read

Page program

register array command

A7 to A18

Address valid

BYTE = Low

(A-1 to A6)

00H

01H

02H to FEH

02H to 7EH

FFH

7FH

BYTE = High

00H

t_AS

(A0 to A6)

t_AH

t_CE

t_WC

CE

OE

WE

t_OE

t_CS

t_CH

t_OEH

t_DAP

t_WP

t_WPH

t_DSt_DH

41H

Din

t_WHRL

SRD

FFH

I/O

RDY/Busy

t_BS

t_BH

BYTE

t_BLS

t_BLH

V_HH

t _PS

RP

t_WPS

t_WPH

WP

22

HN29WT800 Series, HN29WB800 Series

Page Program Timing Waveform (CE control)

Read status

Write read

Page program

register array command

A7 to A18

Address valid

BYTE = Low

(A-1 to A6)

00H

01H

02H to FEH

02H to 7EH

FFH

7FH

BYTE = High

00H

t_AS

(A0 to A6)

t_CE

t_AH

t _WC

CE

OE

WE

t_CEPH

t_OE

t_WH

t_OEH

t_DAP

t_CEP

t_WS

t_DSt_DH

41H

Din

t _EHRL

SRD

FFH

I/O

RDY/Busy

t_BS

t_BH

BYTE

t_BLS

t_BLH

V_HH

t _PS

RP

t_WPS

t_WPH

WP

23

HN29WT800 Series, HN29WB800 Series

Write Timing Waveform for Erase Operations (WE control)

Read status

Write read

Program, Erase

register array command

Address

Address valid

t_AS

t_AH

t_CE

t_WC

CE

t_OE

t_CS

t_CH

t_OEH

OE

t_WP

t

t_WPH

DAE

WE

t_DSt_DH

20H

D0H

t_WHRL

SRD

FFH

I/O

RDY/Busy

t_BS

t_BH

BYTE

t_BLH

t_BLS

V_HH

t _PS

RP

t_WPS

t_WPH

WP

24

HN29WT800 Series, HN29WB800 Series

Write Timing Waveform for Erase Operations (CE control)

Read status

Write read

Program, Erase

register array command

Address

Address valid

t_AS

t_AH

t_CE

t _WC

CE

t_CEPH

t_WH

t_OE

t_OEH

OE

t_CEP

t

DAE

t_WS

WE

t_DSt_DH

20H

D0H

t _EHRL

SRD

FFH

I/O

RDY/Busy

t_BS

t_BH

BYTE

t_BLH

t_BLS

V_HH

t _PS

RP

t_WPS

t_WPH

WP

25

HN29WT800 Series, HN29WB800 Series

Page Program Flowchart

START

Write 41H

n = 0

n = n + 1

Write

Address n, Data n

n = FFH ?

or

n = 7FH ?

NO

YES

Status register read

Write B0H ?

YES

SR. 7 = 1 ?

NO

YES

Full status check

if desired

Suspend loop

Write D0H

Page program

completed

YES

26

HN29WT800 Series, HN29WB800 Series

Block Erase Flowchart

START

Write 20H

Write D0H

Block address

Status register read

SR. 7 = 1 ?

YES

Write B0H ?

NO

YES

Full status check

if desired

Suspend loop

Write D0H

Block erase

completed

YES

27

HN29WT800 Series, HN29WB800 Series

Full Status Check Procedure

Status register

read

SR. 4 = 1

Command sequence error

and

SR. 5 = 1

?

YES

NO

Block erase error

SR. 5 = 0 ?

YES

NO

Program error

(Page, lock bit)

SR. 4 = 0 ?

YES

Program error

(Block)

SR. 3 = 0 ?

YES

Successful

(Block erase, program)

28

HN29WT800 Series, HN29WB800 Series

Suspend/Resume Flowchart

START

Suspend

Write B0H

Status register read

SR. 7 = 1 ?

YES

NO

Program/erase

completed

SR. 6 = 1 ?

NO

YES

Write FFH

Read array data

Done

NO

reading?

YES

Write D0H

Resume

Operation

resumed

29

HN29WT800 Series, HN29WB800 Series

Lock Bit Program Flowchart

START

Write 77H

Write D0H

block address

SR. 7 = 1 ?

NO

YES

Lock bit program

failed

SR. 4 = 0 ?

NO

YES

Lock bit program

successful

30

HN29WT800 Series, HN29WB800 Series

Data Protection Operation

Page programming and Block Erasing can be locked by programming a nonvolatile lock bit for each block.

When WP is V_ILlevel, those locked blocks as reflected by the Block-Lock Status bits, are protected from

inadvertent Page programming or Block Erasing.

Programmed block data and Lock-Bit Data can be locked When WP is V_ILlevel.

Lock bit data programmed

WP = V_ILlevel (Block lock!)

Operation start

Write page program command (41H)

Write block erase command (20H)

Write erase confirm command (D0H)

Block erase error (SR.5 = 1)

Write page program data

(WDn, n = 00H to FFH, 00H to 7FH)

Page program error (SR.4 = 1)

Write clear status register command (50H)

Operation end

Write clear status register command (50H)

Operation end

31

HN29WT800 Series, HN29WB800 Series

Programmed block data and Lock-Bit Data can be erased by block erase command When WP is V_IHlevel or

RP is V_HHlevel.

Lock bit data programmed

WP = V_IHlevel or RP = V_HH(Block unlock!)

Operation start

Write block erase command (20H)

Write erase confirm command (D0H)

Block data and lock bit data erase successful (SR.5 = 0)

Operation end

32

HN29WT800 Series, HN29WB800 Series

Operation Status and Effective Command

Read/standby state

Read status

register

70H

Read device

identifier

Read lock bit

status

71H

90H

Read array

FFH

Setup state

41H

20H

77H

A7H

Page program

setup

Lock bit program

setup

Block erase

setup

Erase all unlocked

blocks setup

WDi

i = 0-255

D0H

other

D0H

other

Inernal state

Program and

verify

Erase and verify

Read status

register

Read status

register

D0H

B0H

D0H

Suspend state

Read status

register

70H

Invalid data

Read device

identifier

Read lock status

71H

90H

Read array

FFH

33

HN29WT800 Series, HN29WB800 Series

Package Dimensions

HN29WT800T/HN29WB800T Series (TFP-48D)

Unit: mm

12.00

12.40 Max

25

48

1

24

0.50

0.08

0.22 ± 0.08

0.20 ± 0.06

0.80

M

20.00 ± 0.20

0.45 Max

0 – 5°

0.50 ± 0.10

0.10

Hitachi Code

TFP-48D

MO-142DD

SC-669

JEDEC Code

EIAJ Code

Weight

0.49 g

34

HN29WT800 Series, HN29WB800 Series

Package Dimensions (cont.)

HN29WT800R/HN29WB800R Series (TFP-48DR)

Unit: mm

12.00

12.40 Max

24

1

48

25

0.50

0.22 ± 0.08

0.20 ± 0.06

0.80

0.08 M

20.00 ± 0.20

0.45 Max

0 – 5°

0.50 ± 0.10

0.10

Hitachi Code

TFP-48DR

MO-142DD

SC-669

JEDEC Code

EIAJ Code

Weight

0.49 g

35

HN29WT800 Series, HN29WB800 Series

When using this document, keep the following in mind:

1. This document may, wholly or partially, be subject to change without notice.

2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of

this document without Hitachi’s permission.

3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other

reasons during operation of the user’s unit according to this document.

4. Circuitry and other examples described herein are meant merely to indicate the characteristics and

performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual

property claims or other problems that may result from applications based on the examples described

herein.

5. No license is granted by implication or otherwise under any patents or other rights of any third party or

Hitachi, Ltd.

6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL

APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such

use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested

to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL

APPLICATIONS.

Hitachi, Ltd.

Semiconductor & IC Div.

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan

Tel: Tokyo (03) 3270-2111

Fax: (03) 3270-5109

For further information write to:

Hitachi America, Ltd.

Semiconductor & IC Div.

2000 Sierra Point Parkway

Brisbane, CA. 94005-1835

U S A

Hitachi Europe GmbH

Electronic Components Group

Continental Europe

Dornacher Straße 3

D-85622 Feldkirchen

München

Hitachi Europe Ltd.

Electronic Components Div.

Northern Europe Headquarters

Whitebrook Park

Lower Cookham Road

Maidenhead

Hitachi Asia Pte. Ltd.

16 Collyer Quay #20-00

Hitachi Tower

Singapore 0104

Tel: 535-2100

Tel: 415-589-8300

Fax: 535-1533

Fax: 415-583-4207

Tel: 089-9 91 80-0

Fax: 089-9 29 30 00

Berkshire SL6 8YA

United Kingdom

Hitachi Asia (Hong Kong) Ltd.

Unit 706, North Tower,

World Finance Centre,

Harbour City, Canton Road

Tsim Sha Tsui, Kowloon

Hong Kong

Tel: 0628-585000

Fax: 0628-778322

Tel: 27359218

Fax: 27306071

36

HN29WT800 Series, HN29WB800 Series

Revision Record

Rev.

0.0

Date

Contents of Modification

Initial issue

Drawn by

K. Izawa

Approved by

T. Muto

Jun. 14, 1996

May. 9, 1997

1.0

Deletion of HN29WT/WB800FP Series

Addition of Top Boot Block Address Map

and Bottom Boot Block Address Map

Software Command Definition

Deletion of Sleep command

Deletion of notes8

Deletion of Block Locking (SOP Package)

Change of Status Register Data (SRD)

DC Characteristics

V

_LKOmin: 1.5 V to 1.2 V

_LKOmax: 2.5 V to —

AC Characteristics

Test Conditions (HN29WT/WB800-10/12):

1TTL gate + 50 pF to 1TTL gate + 100 pF

Change of parameter name: t_RWHto t_PS

Deletion of t_RP

t_PSmin: 0/0/0 ns 500/500/500 ns

t

_DAPmax: 120/120/120 ms to 80/80/80 ms

Erase and program performance

Main block write time max: 38.4 s to 20.4 s

Page write time max: 120 ms to 80 ms

Change of Full Status Check Procedure and

Operation Status and Effective Command

Addition of Data Protection Operation

37


型号：	HN29WT800R-10
厂家：	HITACHI SEMICONDUCTOR
描述：	1048576-word x 8-bit / 524288-word x 16-bit CMOS Flash Memory 1048576字×8位/ 524288字×16位CMOS闪存闪存存储内存集成电路光电二极管
文件：	总37页 (文件大小：180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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