HN58V65A [HITACHI]
64 k EEPROM (8-kword x 8-bit) Ready/Busy function, RES function (HN58V66A); 64K的EEPROM （ 8千字×8位）就绪/忙功能， RES功能（ HN58V66A ）
| 型号： | HN58V65A |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 64 k EEPROM (8-kword x 8-bit) Ready/Busy function, RES function (HN58V66A) |
| 文件： | 总27页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HN58V65A Series
HN58V66A Series
64 k EEPROM (8-kword × 8-bit)
Ready/Busy function, RES function (HN58V66A)
ADE-203-539B (Z)
Rev. 2.0
Nov. 1997
Description
The Hitachi HN58V65A series and HN58V66A series are a electrically erasable and programmable
EEPROM’s organized as 8192-word × 8-bit. They have realized high speed, low power consumption
and high relisbility by employing advanced MNOS memory technology and CMOS process and
circuitry technology. They also have a 64-byte page programming function to make their write
operations faster.
Features
•
•
Single supply: 2.7 to 5.5 V
Access time:
100 ns (max) at 2.7 V ≤ VCC < 4.5 V
70 ns (max) at 4.5 V ≤ VCC ≤ 5.5 V
Power dissipation:
•
Active: 20 mW/MHz (typ)
Standby: 110 µW (max)
•
•
•
•
•
•
•
•
On-chip latches: address, data, CE, OE, WE
Automatic byte write: 10 ms (max)
Automatic page write (64 bytes): 10 ms (max)
Ready/Busy
Data polling and Toggle bit
Data protection circuit on power on/off
Conforms to JEDEC byte-wide standard
Reliable CMOS with MNOS cell technology
HN58V65A Series, HN58V66A Series
Features (cont)
•
•
•
•
•
105 erase/write cycles (in page mode)
10 years data retention
Software data protection
Write protection by RES pin (only the HN58V66A series)
Industrial versions (Temperatur range: –20 to 85˚C and –40 to 85˚C) are also available.
Ordering Information
Access time
2.7 V ≤ VCC < 4.5 V 4.5 V ≤ VCC ≤ 5.5 V Package
Type No.
HN58V65AP-10
HN58V66AP-10
HN58V65AFP-10
HN58V66AFP-10
HN58V65AT-10
HN58V66AT-10
100 ns
100 ns
100 ns
100 ns
100 ns
100 ns
70 ns
70 ns
70 ns
70 ns
70 ns
70 ns
600 mil 28-pin plastic DIP (DP-28)
400 mil 28-pin plastic SOP (FP-28D)
28-pin plastic TSOP(TFP-28DB)
Pin Arrangement
HN58V65AP Series
HN58V65AFP Series
HN58V66AP Series
HN58V66AFP Series
RDY/Busy
A12
A7
RDY/Busy
V
V
CC
1
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
A12
WE
NC
WE
RES
A8
2
2
A7
3
3
A6
A6
A8
4
4
A5
A5
A9
A9
5
5
A4
A4
A11
OE
A10
A11
OE
A10
6
6
A3
A3
7
7
A2
A2
8
8
A1
A1
CE
CE
9
9
A0
A0
I/O7
I/O6
I/O5
I/O4
I/O3
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
10
11
12
13
14
I/O0
I/O1
I/O2
I/O0
I/O1
I/O2
V
V
SS
SS
(Top view)
(Top view)
HN58V65A Series, HN58V66A Series
Pin Arrangement (cont)
HN58V65AT Series
15
A2
A3
14
13
12
11
10
9
16
A1
A4
17
A0
A5
18
A6
I/O0
19
A7
I/O1
20
A12
RDY/Busy
VCC
WE
NC
I/O2
21
8
VSS
22
7
I/O3
23
6
I/O4
24
5
I/O5
25
A8
A9
A11
OE
4
I/O6
26
3
I/O7
27
2
CE
28
1
A10
(Top view)
HN58V66AT Series
15
A2
A3
14
13
12
11
10
9
16
A1
A4
17
A0
A5
18
A6
I/O0
19
A7
I/O1
20
A12
RDY/Busy
VCC
WE
RES
A8
I/O2
21
8
VSS
22
7
I/O3
23
6
I/O4
24
5
I/O5
25
4
I/O6
26
A9
A11
OE
3
I/O7
27
2
CE
28
1
A10
(Top view)
HN58V65A Series, HN58V66A Series
Pin Description
Pin name
A0 to A12
I/O0 to I/O7
OE
Function
Address input
Data input/output
Output enable
Chip enable
Write enable
Power supply
Ground
CE
WE
VCC
VSS
RDY/Busy
RES*1
NC
Ready busy
Reset
No connection
Notes: 1. This function is supported by only the HN58V66A series.
Block Diagram
Notes: This function is supported by only the HN58V66A series.
to
I/O0
I/O7
RDY/Busy
VCC
High voltage generator
VSS
1
*
RES
OE
I/O buffer
and
input latch
CE
Control logic and timing
WE
1
*
RES
A0
to
Y gating
Y decoder
X decoder
A5
Address
buffer and
latch
Memory array
Data latch
A6
to
A12
HN58V65A Series, HN58V66A Series
Operation Table
Operation
Read
CE
VIL
VIH
VIL
VIL
×
OE
VIL
×*2
VIH
VIH
×
WE
VIH
×
RES*3
VH*1
×
RDY/Busy
High-Z
High-Z
High-Z to VOL
High-Z
—
I/O
Dout
High-Z
Din
Standby
Write
VIL
VIH
VIH
×
VH
Deselect
Write Inhibit
VH
High-Z
—
×
×
VIL
VIL
×
×
—
—
Data Polling
VIL
×
VIH
×
VH
VOL
Dout (I/O7)
High-Z
Program reset
VIL
High-Z
Notes: 1. Refer to the recommended DC operating conditions.
2. × : Don’t care
3. This function supported by only the HN58V66A series.
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
V
Power supply voltage relative to VSS
Input voltage relative to VSS
Operating temperature range *2
Storage temperature range
–0.6 to +7.0
–0.5*1 to +7.0*3
0 to +70
Vin
V
Topr
Tstg
˚C
˚C
–55 to +125
Notes: 1. Vin min : –3.0 V for pulse width ≤ 50 ns.
2. Including electrical characteristics and data retention.
3. Should not exceed VCC + 1 V.
HN58V65A Series, HN58V66A Series
Recommended DC Operating Conditions
Parameter
Symbol
VCC
Min
2.7
Typ
—
0
Max
Unit
V
Supply voltage
5.5
VSS
0
0
V
Input voltage
VIL
–0.3*1
1.9*2
VCC – 0.5
0
—
—
—
—
0.6*5
VCC + 0.3*3
VCC + 1.0
70
V
VIH
VH*4
V
V
Operating temperature
Topr
˚C
Notes: 1. VIL min: –1.0 V for pulse width ≤ 50 ns.
2. VIH = 2.2 V for VCC = 3.6 to 5.5 V.
3. VIH max: VCC + 1.0 V for pulse width ≤ 50 ns.
4. This function is supported by only the HN58V66A series.
5. VIL = 0.8 V for VCC = 3.6 V to 5.5 V
DC Characteristics (Ta = 0 to + 70˚C, VCC = 2.7 to 5.5 V)
Parameter
Symbol Min
Typ
—
Max Unit Test conditions
Input leakage current
Output leakage current
Standby VCC curren
ILI
—
—
—
—
—
2*1
µA
µA
µA
mA
mA
Vin = 0 V to VCC
Vout = 0 V to VCC
ILO
—
2
ICC1
ICC2
ICC3
1 to 2
—
5
CE = VCC – 0.3 V to VCC + 1.0 V
CE = VIH
1
Operating VCC current
—
6
Iout = 0 mA, Duty = 100%,
Cycle = 1 µs at VCC = 3.6 V
—
—
—
—
—
—
—
—
8
mA
mA
mA
Iout = 0 mA, Duty = 100%,
Cycle = 1 µs at VCC = 5.5 V
12
25
Iout = 0 mA, Duty = 100%,
Cycle = 100 ns at VCC = 3.6 V
Iout = 0 mA, Duty = 100%,
Cycle = 70 ns at VCC = 5.5 V
Output low voltage
Output high voltage
VOL
VOH
0.4
—
V
V
IOL = 2.1 mA
VCC × 0.8 —
IOH = –400 µA
Note: 1. ILI on RES : 100 µA max (only the HN58V66A series)
Capacitance (Ta = 25˚C, f = 1 MHz)
Parameter
Symbol
Cin*1
Cout*1
Min
—
Typ
—
Max
Unit
pF
Test conditions
Vin = 0 V
Input capacitance
Output capacitance
6
—
—
12
pF
Vout = 0 V
Note: 1. This parameter is sampled and not 100% tested.
HN58V65A Series, HN58V66A Series
AC Characteristics (Ta = 0 to + 70˚C, VCC = 2.7 to 5.5 V)
Test Conditions
•
Input pulse levels : 0.4 V to 2.4 V (VCC = 2.7 to 3.6 V), 0.4 V to 3.0 V (VCC = 3.6 to 5.5 V)
0 V to VCC (RES pin*2)
•
•
•
•
Input rise and fall time : ≤ 5 ns
Input timing reference levels : 0.8, 1.8 V
Output load : 1TTL Gate +100 pF
Output reference levels : 1.5 V, 1.5 V
Read Cycle 1 (VCC = 2.7 to 4.5 V)
HN58V65A/HN58V66A
-10
Parameter
Symbol Min
Max
Unit
ns
Test conditions
Address to output delay
CE to output delay
OE to output delay
Address to output hold
tACC
tCE
tOE
tOH
—
—
10
0
100
100
50
CE = OE = VIL, WE = VIH
OE = VIL, WE = VIH
ns
ns
CE = VIL, WE = VIH
—
ns
CE = OE = VIL, WE = VIH
CE = VIL, WE = VIH
OE (CE) high to output float*1 tDF
0
40
ns
RES low to output float*1, 2
RES to output delay*2
tDFR
tRR
0
350
450
ns
CE = OE = VIL, WE = VIH
CE = OE= VIL, WE = VIH
0
ns
HN58V65A Series, HN58V66A Series
Write Cycle 1 (VCC = 2.7 to 4.5 V)
Parameter
Symbol Min*3 Typ
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
30
—
10*4
—
—
—
—
Unit Test conditions
Address setup time
tAS
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ms
ns
ns
µs
µs
Address hold time
tAH
50
0
CE to write setup time (WE controlled)
CE hold time (WE controlled)
WE to write setup time (CE controlled)
WE hold time (CE controlled)
OE to write setup time
OE hold time
tCS
tCH
tWS
tWH
tOES
tOEH
tDS
0
0
0
0
0
Data setup time
50
0
Data hold time
tDH
tWP
tCW
tDL
WE pulse width (WE controlled)
CE pulse width (CE controlled)
Data latch time
200
200
100
0.3
100
—
120
0*5
100
1
Byte load cycle
tBLC
tBL
tWC
tDB
tDW
tRP
Byte load window
Write cycle time
Time to device busy
Write start time
Reset protect time*2
Reset high time*2, 6
tRES
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions
and
are no longer driven.
2. This function is supported by only the HN58V66A series.
3. Use this device in longer cycle than this value.
4. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This
device automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are
used.
6. This parameter is sampled and not 100% tested.
7. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of WE.
8. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of CE.
9. See AC read characteristics.
HN58V65A Series, HN58V66A Series
Read Cycle 2 (VCC = 4.5 to 5.5 V)
HN58V65A/HN58V66A
-10
Parameter
Symbol Min
Max
70
Unit
ns
Test conditions
Address to output delay
CE to output delay
OE to output delay
Address to output hold
tACC
tCE
tOE
tOH
—
—
10
0
CE = OE = VIL, WE = VIH
OE = VIL, WE = VIH
70
ns
40
ns
CE = VIL, WE = VIH
—
ns
CE = OE = VIL, WE = VIH
CE = VIL, WE = VIH
OE (CE) high to output float*1 tDF
0
30
ns
RES low to output float*1, 2
RES to output delay*2
tDFR
tRR
0
350
450
ns
CE = OE = VIL, WE = VIH
CE = OE= VIL, WE = VIH
0
ns
HN58V65A Series, HN58V66A Series
Write Cycle 2 (VCC = 4.5 to 5.5 V)
Parameter
Symbol Min*3 Typ
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
30
—
10*4
—
—
—
—
Unit Test conditions
Address setup time
tAS
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ms
ns
ns
µs
µs
Address hold time
tAH
50
0
CE to write setup time (WE controlled)
CE hold time (WE controlled)
WE to write setup time (CE controlled)
WE hold time (CE controlled)
OE to write setup time
OE hold time
tCS
tCH
tWS
tWH
tOES
tOEH
tDS
0
0
0
0
0
Data setup time
50
0
Data hold time
tDH
tWP
tCW
tDL
WE pulse width (WE controlled)
CE pulse width (CE controlled)
Data latch time
100
100
50
0.2
100
—
120
0*5
100
1
Byte load cycle
tBLC
tBL
tWC
tDB
tDW
tRP
Byte load window
Write cycle time
Time to device busy
Write start time
Reset protect time*2
Reset high time*2, 6
tRES
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions
and
are no longer driven.
2. This function is supported by only the HN58V66A series.
3. Use this device in longer cycle than this value.
4. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This
device automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are
used.
6. This parameter is sampled and not 100% tested.
7. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of WE.
8. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of CE.
9. See AC read characteristics.
HN58V65A Series, HN58V66A Series
Read Timing Waveform
Address
tACC
CE
tOH
tCE
OE
tDF
tOE
High
WE
Data Out
Data out valid
tRR
tDFR
RES *2
HN58V65A Series, HN58V66A Series
Byte Write Timing Waveform(1) (WE Controlled)
tWC
Address
tCS tAH
tCH
CE
tAS
tBL
tWP
WE
tOES
tOEH
OE
tDS
tDH
Din
tDW
High-Z
tDB
High-Z
RDY/Busy
tRP
tRES
RES *2
VCC
HN58V65A Series, HN58V66A Series
Byte Write Timing Waveform(2) (CE Controlled)
Address
CE
tWC
tWS
tAH
tBL
tCW
tAS
tWH
WE
tOES
tOEH
OE
tDH
tDS
Din
tDW
High-Z
tDB
High-Z
RDY/Busy
tRP
tRES
RES *2
VCC
HN58V65A Series, HN58V66A Series
Page Write Timing Waveform(1) (WE Controlled)
Address*7
A0 to A12
tAH
tAS
tBL
tWP
WE
tDL
tCH
tBLC
tWC
tCS
CE
tOEH
tOES
tDH
OE
tDS
Din
tDW
tDB
High-Z
tRP
High-Z
RDY/Busy
RES *2
tRES
VCC
HN58V65A Series, HN58V66A Series
Page Write Timing Waveform(2) (CE Controlled)
Address*8
A0 to A12
tAH
tCW
tAS
tBL
CE
tDL
tBLC
tWC
tWS
tWH
WE
tOEH
tOES
tDH
OE
tDS
Din
tDW
tDB
High-Z
High-Z
RDY/Busy
tRP
RES *2
tRES
VCC
HN58V65A Series, HN58V66A Series
Data Polling Timing Waveform
Address
An
An
An
CE
*9
tCE
WE
OE
tOES
tOEH
*9
tOE
tDW
Din X
Dout X
Dout X
I/O7
tWC
HN58V65A Series, HN58V66A Series
Toggle Bit
This device provide another function to determine the internal programming cycle. If the EEPROM is
set to read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for
each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device
can be accessible for next read or program.
Toggle Bit Waveform
Notes: 1. I/O6 begining state is “1”.
2. I/O6 ending state will vary.
3. See AC read characteristics.
4. Any address location can be used, but the address must be fixed.
Next mode
*4
Address
*3
t
CE
CE
WE
OE
*3
t
OE
t
t
OES
OEH
*1
*2
*2
Din
Dout
Dout
Dout
Dout
I/O6
t
DW
t
WC
HN58V65A Series, HN58V66A Series
Software Data Protection Timing Waveform(1) (in protection mode)
VCC
CE
WE
tBLC
tWC
Address
Data
1555
AA
1555 Write address
A0 Write data
0AAA
55
Software Data Protection Timing Waveform(2) (in non-protection mode)
VCC
Normal active
mode
tWC
CE
WE
Address
Data
1555 0AAA 1555 1555 0AAA 1555
AA 55 80 AA 55 20
HN58V65A Series, HN58V66A Series
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write
cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner.
Each additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or
CE. When CE or W E is kept high for 100 µs after data input, the EEPROM enters write mode
automatically and the input data are written into the EEPROM.
Data Polling
Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read
mode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the
EEPROM is performing a write operation.
RDY/Busy Signal
RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to VOL after the first write signal. At the end of a write
cycle, the RDY/Busy signal changes state to high impedance.
RES Signal (only the HN58V66A series)
When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by
keeping RES low when VCC is switched. RES should be high during read and programming because it
doesn’t provide a latch function.
VCC
Read inhibit
Read inhibit
RES
Program inhibit
Program inhibit
HN58V65A Series, HN58V66A Series
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the
rising edge of WE or CE.
Write/Erase Endurance and Data Retention Time
The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte
programming (1% cumulative failure rate). The data retention time is more than 10 years when a device
is page-programmed less than 104 cycles.
Data Protection
1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to
programming mode by mistake.
To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is
15 ns or less.
Be careful not to allow noise of a width of more than 15 ns on the control pins.
WE
CE
V
IH
0 V
V
IH
OE
0 V
15 ns max
HN58V65A Series, HN58V66A Series
2. Data protection at VCC on/off
When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may
act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional
programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable
state.
Note: The EEPROM shoud be kept in unprogrammable state during VCC on/off by using CPU RESET
signal.
VCC
CPU
RESET
*
*
Unprogrammable
Unprogrammable
(1) Protection by CE, OE, WE
To realize the unprogrammable state, the input level of control pins must be held as shown in the table
below.
CE
OE
WE
VCC
×
×
×
VSS
×
×
×
VCC
×: Don’t care.
VCC: Pull-up to VCC level.
VSS: Pull-down to VSS level.
HN58V65A Series, HN58V66A Series
(2) Protection by RES (only the HN58V66A series)
The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the
EEPROM’s RES pin. RES should be kept VSS level during VCC on/off. The EEPROM breaks off
programming operation when RES becomes low, programming operation doesn’t finish correctly in
case that RES falls low during programming operation. RES should be kept high for 10 ms after the last
data input.
VCC
RES
Program inhibit
Program inhibit
WE
or CE
10 ms min
1 µs min
100 µs min
HN58V65A Series, HN58V66A Series
3. Software data protection
To prevent unintentional programming caused by noise generated by external circuits, this device has
the software data protection function. In software data protection mode, 3 bytes of data must be input
before write data as follows. And these bytes can switch the non-protection mode to the protection
mode. SDP is enabled if only the 3 bytes code is input.
Address
Data
1555
AA
↓
↓
0AAA
↓
55
↓
1555
↓
A0
↓
Write address Write data } Normal data input
Software data protection mode can be cancelled by inputting the following 6 bytes. After that, this
device turns to the non-protection mode and can write data normally. But when the data is input in the
cancelling cycle, the data cannot be written.
Address
Data
1555
↓
AA
↓
0AAA
↓
55
↓
1555
↓
1555
↓
0AAA
↓
1555
80
↓
AA
↓
55
↓
20
The software data protection is not enabled at the shipment.
Note: There are some differences between Hitachi’s and other company’s for enable/disable sequence
of software data protection. If there are any questions , please contact with Hitachi sales
offices.
HN58V65A Series, HN58V66A Series
Package Dimensions
HN58V65AP Series
HN58V66AP Series (DP-28)
Unit: mm
35.6
36.5 Max
28
15
14
1
1.2
1.9 Max
15.24
0.25
+ 0.11
– 0.05
2.54 ± 0.25
0.48 ± 0.10
0° – 15°
Hitachi Code
JEDEC Code
EIAJ Code
DP-28
—
SC-510-28E
Weight (reference value) 4.6 g
HN58V65A Series, HN58V66A Series
Package Dimensions (cont)
HN58V65AFP Series
HN58V66AFP Series (FP-28D)
Unit: mm
18.3
18.8 Max
15
28
1
14
11.8 ± 0.3
1.12 Max
1.7
0° – 8°
1.27
1.0 ± 0.2
0.15
0.40 ± 0.08
0.38 ± 0.06
M
0.20
Hitachi Code
JEDEC Code
EIAJ Code
FP-28D
MO-059-AC
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.7 g
HN58V65A Series, HN58V66A Series
Package Dimensions (cont)
HN58V65AT Series
HN58V66AT Series (TFP-28DB)
Unit: mm
8.00
8.20 Max
15
28
1
14
0.55
0.22 ± 0.08
0.20 ± 0.06
0.10 M
0.80
13.40 ± 0.30
0.45 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
TFP-28DB
JEDEC Code
EIAJ Code
Weight (reference value) 0.23 g
—
—
Dimension including the plating thickness
Base material dimension
HN58V65A Series, HN58V66A Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or
part of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or
any other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any
intellectual property claims or other problems that may result from applications based on the
examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party
or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in
MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Tel: 415-589-8300
Fax: 535-1533
Fax: 415-583-4207
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Berkshire SL6 8YA
United Kingdom
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 0628-585000
Fax: 0628-778322
Tel: 27359218
Fax: 27306071
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