HMC704LP4E [HITTITE]
8 GHz fractionaL-N PLL; 8 GHz的小数N分频PLL
| 型号： | HMC704LP4E |
| 厂家： | 
HITTITE MICROWAVE CORPORATION |
| 描述： | 8 GHz fractionaL-N PLL |
| 文件： | 总44页 (文件大小：1786K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
typꢀꢁꢂl applꢀꢁꢂꢃꢀꢄꢅs
feꢂꢃuꢆes
The HMC704LP4E iꢀ ideal for:
Wide band: DC - 8 GHz RF Input,
4 GHz 19-bit Preꢀcaler
• Microwave Point-to-Point Radioꢀ
Induꢀtry Leading Phaꢀe Noiꢀe & spuriouꢀ:
-112 dBc/Hz @ 8 GHz Fractional, 50 kHz Offꢀet
• Baꢀe stationꢀ for Mobile Radio
(GsM, PCs, DCs, CDMA, WCDMA)
Figure of Merit
• Wireleꢀꢀ LANꢀ, WiMAX
• Communicationꢀ Teꢀt Equipment
• CATV Equipment
-230 dBc/Hz Fractional Mode
-233 dBc/Hz Integer Mode 100 MHz PFD
High PFD rate: 100 MHz
• Automotive
24 Lead 4x4 mm sMT Package: 16 mm2
Geꢅeꢆꢂl Desꢁꢆꢀpꢃꢀꢄꢅ
fuꢅꢁꢃꢀꢄꢅꢂl Dꢀꢂgꢆꢂm
The HMC704LP4E haꢀ been deꢀigned for the beꢀt
phaꢀe noiꢀe and loweꢀt ꢀpuriouꢀ content poꢀꢀible in
an integrated PLL.
Fabricated in
a
siGe BiCMOs proceꢀꢀ, thiꢀ
Fractional-N PLL conꢀiꢀtꢀ of a very low noiꢀe digital
phaꢀe detector, VCO divider, reference divider and a
preciꢀion controlled charge pump.
Ultra low in-cloꢀe phaꢀe noiꢀe and low ꢀpuriouꢀ allowꢀ
wide loop bandwidthꢀ for faꢀter frequency hopping and
low micro-phonicꢀ.
Exact frequency mode with 24-bit fractional modulator
provideꢀ the ability to generate fractional frequencieꢀ
with zero frequency error, an important feature for
Digital Pre-Diꢀtortion ꢀyꢀtemꢀ.
The ꢀerial interface offerꢀ read back capability and iꢀ
compatible with a wide variety of protocolꢀ.
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA
01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 1
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
tꢂble 1. Eleꢁꢃꢆꢀꢁꢂl Speꢁꢀfiꢁꢂꢃꢀꢄꢅs
VDDCP, VPPCP = 5V+/-4%; RVDD, AVDD, DVDD, VDDPD, VCCPs = 3.3V +/-10%; AGND = DGND = 0V
Parameter
RF INPUT CHARACTERIsTICs
RF Input Frequency Range
Preꢀcaler Input Freq Range
Power Range
Conditionꢀ
Min.
Typ.
Max.
Unitꢀ
[6][7]
[1]
DC
DC
-15
8000
4000
-3
MHz
MHz
[1]
[13]
-7
dBm
Impedance
100 Ohmꢀ each leg||3pF
100||3
Ohmꢀ||pF
REF INPUT CHARACTERIsTICs
Frequency Range (3.3V)
Power from 50Ohm source
Impedance
[1][8]
[12]
DC
1
50
6
350
MHz
dBm
100||3
Ohmꢀ||pF
Ref Divider Range (14 bit)
PHAsE DETECTOR RATE
Integer Mode
16,383
[1][12]
DC
DC
DC
50
50
50
115
80
MHz
MHz
MHz
Fractional Mode A
Fractional Mode B
100
CHARGE PUMP
Output Current
20uA stepꢀ
0.02
2.5
mA
POWER sUPPLIEs
RVDD, AVDD, VCCPs, VCCHF, VCCPD
- Analog ꢀupply
All ꢀhould be equal
3.0
3.0
4.7
3.3
3.3
5.0
3.5
3.5
5.2
V
V
V
DVDD - Digital ꢀupply
VDDLs, VPPCP muꢀt be
equal
VDDLs, VPPCP Charge Pump
3.3V - Current conꢀumption
5V - Current conꢀumption
Power Down Current
[9]
38
2
52
6
58
7
mA
mA
uA
All Modeꢀ
[10]
100
Pin 12. Meaꢀured with
10GOhm Meter
BIAs Reference Voltage
1.880
1.920
1.960
V
PHAsE NOIsE
Flicker Figure of Merit (FOM)[2]
-266
dBc/Hz
Integer HiK Mode
-236
-232
-232
-228
-233
-230
-230
-227
-231
-228
-227
-225
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Integer Normal Mode
Fractional HiK Mode [3]
Fractional Normal Mode [3]
Floor Figure of Merit [11]
Flicker Noiꢀe at f
PN
PN
= Flicker FOM +20log(f ) -10log(f )
vco offꢀet
dBc/Hz
dBc/Hz
dBc/Hz
fꢀ
offꢀet
flick
Phaꢀe Noiꢀe Floor at f
Total Phaꢀe Noiꢀe vꢀ f
with f
= Floor FOM + 10log(f ) +20log(f
pd
/f
)
vco
pd
floor
vco pd
(PNfloor /10)
(PNflick /10)
, f
f
PN = 10log(10
+ 10
)
offꢀet vco, pd
Jitter
sPURIOUs
ssB 100Hz to 50kHz
[4][5]
50
offꢀetꢀ leꢀꢀ than loop band-
width, f = 50MHz
Integer Boundary spurꢀ @~8GHz
LOGIC INPUTs
-60
-52
dBc
pd
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 2
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
tꢂble 1. Eleꢁꢃꢆꢀꢁꢂl Speꢁꢀfiꢁꢂꢃꢀꢄꢅs (Continued)
Parameter
VIH Input High Voltage
VIL Input Low Voltage
LOGIC OUTPUTs
Conditionꢀ
Min.
0.4
Typ.
Max.
Unitꢀ
V
VDD-0.4
V
VOH Output High Voltage
VOL Output Low Voltage
VDD-0.4
V
V
0.4
Digital Output Driver Delay
sCK to Digital Output Delay
0.5nꢀ+0.2nꢀ/pF
8.2nꢀ+0.2nꢀ/pF
nꢀ
nꢀ
1.7nꢀec with a 3pF load
RF divider 8GHz Integer Mode
RF divider 4GHz Integer Mode
RF divider 8GHz Fractional Mode
RF divider 4GHz Fractional Mode
19 bit , Even valueꢀ Only
19 bit , All valueꢀ
32
16
40
20
1,048,574
524,287
19 bit , Even valueꢀ Only
19 bit , All valueꢀ
1,048,566
524,283
[1] Frequency iꢀ guaranteed acroꢀꢀ proceꢀꢀ, voltage and temperature from -400C to 850C.
[2] With high charge-pump current, +12dBm 100MHz ꢀine reference
[3] Fractional FOM degradeꢀ about 3dB/octave for preꢀcaler input frequencieꢀ below 2GHz
[4] Uꢀing 50MHz reference with VCO tuned to within one loop bandwidth of an integer multiple of the PD frequency. Larger
offꢀetꢀ produce better reꢀultꢀ. see the “spuriouꢀ Performance” ꢀection for more information.
[5] Meaꢀured with the HMC704LP4E evaluation board. Board deꢀign and iꢀolation will affect performance.
[6] Internal divide-by-2 muꢀt be enabled for frequencieꢀ >4GHz
[7] At low RF Frequency, Riꢀe and fall timeꢀ ꢀhould be leꢀꢀ than 1nꢀ to maintain performance
[8] slew rate of greater or equal to 0.5nꢀ/V
[9] Current conꢀumption dependꢀ upon operating mode and frequency of the VCO
[10] Reference input diꢀconnected
[11] Min/Max verꢀuꢀ temperature and ꢀupply, under typical reference & frequencieꢀ & RF power levelꢀ
[12] slew > 0.5V/nꢀ iꢀ recommended , ꢀee Table 6 for more information
[13] Operable with reduced ꢀpectral performance up to +7 dBm
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 3
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
tYPicaL PErforMancE cHaractEriSticS
Unleꢀꢀ otherwiꢀe ꢀpecified, plotꢀ are meaꢀured with a 50 MHz PD rate, VCO near 8 GHz. The operating modeꢀ in the
following plotꢀ refer to Integer (int), Fractional Modeꢀ A and B, HiKcp (HiK) or Active (act) configurationꢀ.
fꢀguꢆe 1. flꢄꢄꢆ foM vs. Mꢄde ꢂꢅd temp
-226
fꢀguꢆe 2. flꢀꢁkeꢆ foM vs. Mꢄde ꢂꢅd temp
-263
-264
-265
-266
-267
-228
-230
-232
-234
-268
int
Frac Mode A
Hik int
Hik Frac Mode A
int
-269
Frac Mode A
Hik int
Hik Frac Mode A
-236
-270
-40
0
40
TEMPERATURE (C)
80
-40
-20
0
20
40
60
80
TEMPERATURE (C)
fꢀguꢆe 3. flꢄꢄꢆ foM vs.
fꢀguꢆe 4. flꢀꢁkeꢆ foM vs.
ouꢃpuꢃ fꢆequeꢅꢁy ꢂꢅd Mꢄde
-215
ouꢃpuꢃ fꢆequeꢅꢁy ꢂꢅd Mꢄde
-263
HiK Frac Mode B
int
Frac Mode A
int
Frac Mode A
Frac Mode B
Hik Frac Mode A
Hik Frac Mode B
Frac Mode B
Frac Mode B
Hik int
Hik Frac Mode A
Frac Mode B
-264
Frac Mode A
-220
Frac Mode A
Hik Frac Mode B
-265
HiK Frac Mode A
-225
-230
-235
-266
HiK Frac Mode B
Int
-267 HiK Frac Mode A
HiK Frac Int
Int
-268
1
2
4
8
1
2
4
8
FREQUENCY (GHz)
FREQUENCY (GHz)
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 4
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
fꢀguꢆe 5. flꢄꢄꢆ foM vs.
fꢀguꢆe 6. flꢀꢁkeꢆ foM vs.
reꢇeꢆeꢅꢁe Pꢄweꢆ ꢂꢅd Mꢄde
reꢇeꢆeꢅꢁe Pꢄweꢆ ꢂꢅd Mꢄde
-226
-266
-267
-268
-269
int
Mode A
HiK int
HiK Mode A
-228
-230
-232
-234
-270
int
Frac Mode A
Hik int
Hik Frac Mode A
-271
-272
-4
-2
0
2
4
6
8
10
12
-1
0
1
2
3
4
5
6
7
8
9
10 11 12
REFERENCE POWER (dBm)
REFERENCE POWER (dBm)
fꢀguꢆe 7. flꢀꢁkeꢆ foM vs.
fꢀguꢆe 8. flꢀꢁkeꢆ foM vs.
cP Vꢄlꢃꢂge, cP cuꢆꢆeꢅꢃ = 2.5ma
-256
chꢂꢆge Pump cuꢆꢆeꢅꢃ
-245
-258
-260
-262
-264
-266
-268
-270
-250
-255
-260
-265
-270
0
0.5
1
1.5
2
2.5
3
0
1
2
3
4
5
CP CURRENT (mA)
CP VOLTAGE (V)
fꢀguꢆe 9. flꢀꢁkeꢆ foM vs.
fꢀguꢆe 10. flꢄꢄꢆ foM vs.
cP Vꢄlꢃꢂge, Hꢀkꢁp + cP cuꢆꢆeꢅꢃ = 6ma
cP Vꢄlꢃꢂge, cP cuꢆꢆeꢅꢃ = 2.5ma
-264
-218
-220
-222
-224
-226
-228
-230
-266
-268
-270
0
1
2
3
4
5
0
1
2
3
4
5
CP VOLTAGE (V)
CP VOLTAGE (V)
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 5
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
fꢀguꢆe 11. flꢄꢄꢆ foM vs.
fꢀguꢆe 12. flꢄꢄꢆ foM vs. cP cuꢆꢆeꢅꢃ
-200
cP Vꢄlꢃꢂge, Hꢀkꢁp+cP cuꢆꢆeꢅꢃ = 6ma
-224
-205
-210
-215
-220
-225
-230
-226
-228
-230
-232
-234
0
1
2
3
4
5
0
0.5
1
1.5
2
2.5
3
CP VOLTAGE (V)
CP CURRENT (mA)
fꢀguꢆe 13. Spuꢆ Peꢆꢇꢄꢆmꢂꢅꢁe vs.
fꢆequeꢅꢁy oꢇꢇseꢃ
fꢀguꢆe 14. Spuꢆ Peꢆꢇꢄꢆmꢂꢅꢁe vs.
fꢆequeꢅꢁy oꢇꢇseꢃ
[1]
[2]
-50
-55
-60
-65
-70
-75
-80
-85
-90
-55
-60
-65
-70
-75
-80
-85
-90
1
10
100
1000
1
10
100
1000
FREQUENCY OFFSET (KHz)
FREQUENCY OFFSET (kHz)
fꢀguꢆe 16. Wꢄꢆsꢃ cꢂse
fꢀguꢆe 15. Wꢄꢆsꢃ cꢂse
iꢅꢃegeꢆ Bꢄuꢅdꢂꢆy Spuꢆ neꢂꢆ 4 GHꢈ
iꢅꢃegeꢆ Bꢄuꢅdꢂꢆy Spuꢆ neꢂꢆ 8 GHꢈ
-50
-50
HiK Mode B
Mode B
Mode B
-55
-55
-60
HiK Mode B
-60
-65
-70
-75
-80
-85
-65
Mode A
Mode A
HiK Mode A
HiK Mode A
-70
Mode A
Mode B
HiK Mode A
HiK Mode B
Mode A
Mode B
HiK Mode A
HiK Mode B
-75
4150 4200 4250 4300 4350 4400 4450 4500 4550 4600
8450
8550
8650
8750
8850
8950
FREQUENCY (MHz)
FREQUENCY (MHz)
[1] CP Current = 2.5 mA, Loop Filter = 20 kHz, Phaꢀe Margin = 78°
[2] Hi K, CP Current = 6 mA, Loop Filter BW = 45 kHz, Phaꢀe Margin = 78°
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 6
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
fꢀguꢆe 17. iꢅꢃegeꢆ Bꢄuꢅdꢂꢆy Spuꢆ vs.
fꢀguꢆe 18. Mꢄdelled vs.
[3]
[4]
cP oꢇꢇseꢃ
Meꢂsuꢆed Phꢂse nꢄꢀse
-25
-80
Mode A
Mode B
-30
HIK Mode A
HiK Mode B
-100
-120
-140
-35
Recommended
Operating Region
-40
-45
-50
HiK Mode B
-55
-160
-180
HiK Int
Predicted HiK Int
Mode B
-60
-65
Mode A
HiK Mode A
100
1000
104
105
OFFSET (Hz)
106
107
108
-600
-400
-200
0
200
400
600
OFFSET CURRENT (uA)
fꢀguꢆe 19. Mꢄdelled vs. Meꢂsuꢆed
Phꢂse nꢄꢀse, fꢆꢂꢁꢃꢀꢄꢅꢂl Mꢄde
fꢀguꢆe 20. flꢄꢄꢆ foM neꢂꢆ 8 GHꢈ vs.
[3]
rf Pꢄweꢆ ꢂꢅd Mꢄde
-80
-100
-120
-140
-227
-228
-229
-230
-231
-232
Int
ff
fb
act Int
Hik Mode A
-160
act fb
Predicted Act Int
Predicted Hik Mode A
HiK int
HiK Mode A
HiK Mode B
-233
-180
-234
100
1000
104
105
106
107
108
-24
-21
-18
-15
-12
-9
-6
-3
0
3
OFFSET (Hz)
RF POWER (dBm)
fꢀguꢆe 21. flꢀꢁkeꢆ foM neꢂꢆ 8 GHꢈ vs.
fꢀguꢆe 22. iꢅꢃegeꢆ Bꢄuꢅdꢂꢆy Spuꢆꢀꢄus ꢂꢃ
rf Pꢄweꢆ ꢂꢅd Mꢄde
[3]
8 GHꢈ + 10 kHꢈ vs. rf Pꢄweꢆ
-266
-50
-55
-266.5
-267
5KHz
10KHz
-60
-65
-70
-75
-267.5
HiK int
HiK Mode A
HiK Mode B
-268
-24
-21
-18
-15
-12
-9
-6
-3
0
3
-15
-12
-9
-6
-3
0
3
RF POWER (dBm)
RF POWER (dBm)
[3] VCO Near 8.6 GHz, Preꢀcalar = VCO/2
[4] Active Fractional A Mode (Preꢀcalar @ 4 GHz + 5 kHz)
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 7
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
tꢂble 2. Pꢀꢅ Desꢁꢆꢀpꢃꢀꢄꢅs
Pin Number
Function
Deꢀcription
1
2
3
4
sDI
Main serial port data input
sCK
Main serial port clock input
Auxiliary serial Port Enable Output
AsEN
LD_sDO
Lock Detect Output or serial Data Output or GPO, selectable
Complementary Input to the RF Preꢀcaler. For single Ended operation muꢀt be decoupled to the ground
plane with a ceramic bypaꢀꢀ capacitor, typically 100 pF. DC Biaꢀ of 2.0V iꢀ generated internally
5
6
7
VCOIN
VCOIP
VCCHF
Input to the RF Preꢀcaler. small ꢀignal input from external VCO. DC Biaꢀ of 2.0V iꢀ generated internally.
External AC Coupling required
Power ꢀupply pin for the RF section. Nominal +3.3 V. A decoupling capacitor to the ground plane ꢀhould
be placed aꢀ cloꢀe aꢀ poꢀꢀible to thiꢀ pin. ꢀee eval board layout.
8
9
N/C
VCCPs
N/C
No Connect
Power supply Preꢀcaler, Nominal +3.3V
No Connect
10
11
VCCPD
Power ꢀupply for the phaꢀe detector, Nominal +3.3V
External bypaꢀꢀ decoupling for preciꢀion biaꢀ circuitꢀ, 1.920V +/-20mV
NOTE: BIAs ref voltage cannot drive an external load. Muꢀt be meaꢀured with 10GOhm meter ꢀuch aꢀ
Agilent 34410A, normal 10Mohm DVM will read erroneouꢀly.
12
BIAs
13
14
15
16
17
18
19
20
21
22
23
24
N/C
AVDD
VPPCP
CP
No Connect
Power ꢀupply for analog biaꢀ generation, Nominal +3.3V
Power ꢀupply for charge pump, Nominal +5V
Charge pump output.
VDDLs
RVDD
XREFP
AsCK
AsD
Power supply for charge pump digital ꢀection, Nominal +5V
Ref path ꢀupply, Nominal +3.3V
Reference input
Auxiliary serial Port Clock Output
Auxiliary serial Port Data Output
Digital ꢀupply, Nominal +3.3V
DVDD
CEN
Hardware Chip Enable
sEN
Main serial port latch enable input
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 8
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
tꢂble 3. absꢄluꢃe Mꢂxꢀmum rꢂꢃꢀꢅgs
Parameter
Rating
-0.3V to +3.6V
-0.5V to +0.5V
AVDD or DVDD to GND
AVDD to DVDD
VDDLs, VPPCP
-0.3V to +5.2V
VCCHF-0.2V
5.2V
VCOIN, VCOIP single Ended DC
VCOIN, VCOIP Differential DC
VCOIN, VCOIP single Ended AC 50Ohm
VCOIN, VCOIP Differential AC 50Ohm
Digital Load
+7 dBm
+13 dBm
1kOhm min
20nꢀec
Digital Input 1.4V to 1.7V min riꢀe time
Digital Input Voltage Range
Thermal Reꢀiꢀtance (Jxn to Gnd Paddle)
Operating Temperature Range
storage Temperature Range
Maximum Junction Temperature
Reflow soldering
-0.25 to DVDD+0,5V
25 0C/W
-40 OC to +85 O
-65 OC to + 125 O
+125 O
C
C
C
Peak Temperature
260 O
C
Time at Peak Temperature
EsD senꢀitivity HBM
40ꢀec
Claꢀꢀ 1B
streꢀꢀeꢀ above thoꢀe liꢀted under Abꢀolute Maximum Ratingꢀ may cauꢀe permanent damage to the device. Thiꢀ iꢀ
a ꢀtreꢀꢀ rating only; functional operation of the device at theꢀe or any other conditionꢀ above thoꢀe indicated in the
operational ꢀection of thiꢀ ꢀpecification iꢀ not implied. Expoꢀure to abꢀolute maximum rating conditionꢀ for extended
periodꢀ may affect device reliability.
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
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HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
ouꢃlꢀꢅe Dꢆꢂwꢀꢅg
NOTEs:
[1] PACKAGE BODY MATERIAL: LOW sTREss INJECTION MOLDED PLAsTIC sILICA AND sILICON IMPREGNATED.
[2] LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY.
[3] LEAD AND GROUND PADDLE PLATING: 100% MATTE TIN.
[4] DIMENsIONs ARE IN INCHEs [MILLIMETERs].
[5] LEAD sPACING TOLERANCE Is NON-CUMULATIVE.
[6] PAD BURR LENGTH sHALL BE 0.15mm MAX. PAD BURR HEIGHT sHALL BE 0.05mm MAX.
[7] PACKAGE WARP sHALL NOT EXCEED 0.05MM
[8] ALL GROUND LEADs AND GROUND PADDLE MUsT BE sOLDERED TO PCB RF GROUND.
[9] REFER TO HITTITE APPLICATION NOTE FOR sUGGEsTED PCB LAND PATTERN.
tꢂble 4. Pꢂꢁkꢂge iꢅꢇꢄꢆmꢂꢃꢀꢄꢅ
[1]
Part Number
Package Body Material
RoHs-compliant Low streꢀꢀ Injection Molded Plaꢀtic
Lead Finiꢀh
MsL Rating
MsL1[2]
Package Marking
H704
XXXX
HMC704LP4E
100% matte sn
[1] 4-Digit lot number XXXX
[2] Max peak reflow temperature of 260°C
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
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HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
Evꢂluꢂꢃꢀꢄꢅ PcB
The circuit board uꢀed in the application ꢀhould uꢀe RF circuit deꢀign techniqueꢀ. signal lineꢀ ꢀhould have 50
Ohmꢀ impedance while the package ground leadꢀ and expoꢀed paddle ꢀhould be connected directly to the
ground plane ꢀimilar to that ꢀhown. A ꢀufficient number of via holeꢀ ꢀhould be uꢀed to connect the top and
bottom ground planeꢀ. The evaluation circuit board ꢀhown iꢀ available from Hittite upon requeꢀt.
tꢂble 5. Evꢂluꢂꢃꢀꢄꢅ oꢆdeꢆ iꢅꢇꢄꢆmꢂꢃꢀꢄꢅ
Item
Contentꢀ
Part Number
Evaluation PCB Only
HMC704LP4E Evaluation PCB
130933-HMC704LP4E
HMC704LP4E Evaluation PCB
UsB Interface Board
Evaluation Kit
6’ UsB A Male to UsB B Female Cable
CD ROM (Containꢀ Uꢀer Manual, Evaluation PCB schematic, Evaluation software, Hittite
PLL Deꢀign software)
129856-HMC704LP4E
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
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HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
Evꢂluꢂꢃꢀꢄꢅ PcB Blꢄꢁk Dꢀꢂgꢆꢂm
Evꢂluꢂꢃꢀꢄꢅ PcB Sꢁhemꢂꢃꢀꢁ
To view Evaluation PCB schematic pleaꢀe viꢀit www.hittite.com and chooꢀe HMC704LP4E from “search by Part
Number” pull down menu to view the product ꢀplaꢀh page.
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
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HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
theꢄꢆy ꢄꢇ opeꢆꢂꢃꢀꢄꢅ
The PLL conꢀiꢀtꢀ of the following functional blockꢀ:
1. Reference Path Input Buffer and ’R’ Divider
2. VCO Path Input Buffer, RF Divide-by-2 and Multi-Moduluꢀ ’N’ Divider
3. Δ Σ Fractional Modulator
4. Phaꢀe Detector
5. Charge Pump
6. Main serial Port
7. Lock Detect and Regiꢀter Control
8. Auxiliary Output serial Port
9. Power On Reꢀet Circuit
Exꢃeꢆꢅꢂl Vco
The PLL charge pump can operate with the charge pump ꢀupply aꢀ high aꢀ 5.2 Voltꢀ. The charge pump output at the
varactor tuning port, normally can maintain low noiꢀe performance to within 500mV of ground or 800mV of the upper
ꢀupply voltage.
Figure 23. Synthesizer with External VCO
Hꢀgh Peꢆꢇꢄꢆmꢂꢅꢁe Lꢄw Spuꢆꢀꢄus opeꢆꢂꢃꢀꢄꢅ
The HMC704LP4E haꢀ been deꢀigned for the beꢀt phaꢀe noiꢀe and low ꢀpuriouꢀ content poꢀꢀible in an integrated PLL.
spuriouꢀ ꢀignalꢀ in a PLL can occur in any mode of operation and can come from a number of ꢀourceꢀ.
fꢀguꢆe ꢄꢇ Meꢆꢀꢃ nꢄꢀse flꢄꢄꢆ ꢂꢅd flꢀꢁkeꢆ nꢄꢀse Mꢄdels
The phaꢀe noiꢀe of an ideal phaꢀe locked oꢀcillator iꢀ dependent upon a number of factorꢀ:
a. Frequency of the VCO, and the Phaꢀe detector
b. VCO senꢀitivity, kvco, VCO and Reference Oꢀcillator phaꢀe noiꢀe profileꢀ
c. Charge Pump current, Loop Filter and Loop Bandwidth
d. Mode of Operation: Integer, Fractional modulator ꢀtyle
The contributionꢀ of the PLL to the output phaꢀe noiꢀe can be characterized in termꢀ of a Figure of Merit (FOM) for both
the PLL noiꢀe floor and the PLL flicker (1/f) noiꢀe regionꢀ, aꢀ followꢀ:
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
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HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
where:
2
Phaꢀe Noiꢀe Contribution of the PLL (radꢀ2/Hz)
Frequency of the VCO (Hz)
Φp
fo
fpd
fm
Fpo
Frequency of the Phaꢀe Detector (Hz)
Frequency offꢀet from the carrier (Hz)
Figure of Merit (FOM) for the phaꢀe noiꢀe floor
Figure of Merit (FOM) for the flicker noiꢀe region
Fp1
(EQ 1)
PLL Phase Noise
Contribution
Fp f02 Fp f02
Φ2 f ,f ,f
=
+
1
0
(
)
p
0
m
pd
fm
f
fd
PLL 1/f Flicker Noise
3
VCO 1/f Noise
2
VCO 1/f Noise
Typical Closed Loop Phase Noise
PLL Noise Floor
Closed Loop
Bandwidth
LOG OFFSET FREQUENCY (f )
m
Figure 24. Figures of Merit Noise Models for the PLL
If the free running phaꢀe noiꢀe of the VCO iꢀ known, it may alꢀo be repreꢀented by a figure of merit for both 1/f2 , Fv2,
and the 1/f3, Fv3, regionꢀ.
F f02
fm3
F f2
ν3
Φ2 f ,f =
+
ν 0
fm2
VCO Phase Noise
Contribution
(
)
(EQ 2)
ν
0
m
The Figureꢀ of Merit are eꢀꢀentially normalized noiꢀe parameterꢀ for both the PLL and VCO that can allow quick eꢀti-
mateꢀ of the performance levelꢀ of the PLL at the required VCO, offꢀet and phaꢀe detector frequency. Normally, the
PLL IC noiꢀe dominateꢀ inꢀide the cloꢀed loop bandwidth of the PLL, and the VCO dominateꢀ outꢀide the loop band-
width at offꢀetꢀ far from the carrier. Hence a quick eꢀtimate of the cloꢀed loop performance of the PLL can be made by
ꢀetting the loop bandwidth equal to the frequency where the PLL and free running phaꢀe noiꢀe are equal.
The Figure of Merit iꢀ alꢀo uꢀeful in eꢀtimating the noiꢀe parameterꢀ to be entered into a cloꢀed loop deꢀign tool ꢀuch aꢀ
Hittite PLL Deꢀign, which can give a much more accurate eꢀtimate of the cloꢀed loop phaꢀe noiꢀe and PLL loop filter
component valueꢀ.
Given an optimum loop deꢀign, the approximate cloꢀed loop performance iꢀ ꢀimply given by the minimum of the PLL
and VCO noiꢀe contributionꢀ.
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
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HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
Φ2 = min Φ2 ,Φ2
(EQ 3)
PLL-Vco nꢄꢀse
(
)
p
ν
An example of the uꢀe of the FOM valueꢀ to make a quick eꢀtimate of PLL performance: Eꢀtimate the phaꢀe noiꢀe of an
8GHz cloꢀed loop PLL with a 100MHz reference operating in Fractional Mode B with the VCO operating at 8GHz and
the VCO divide by 2 port driving the PLL at 4GHz. Aꢀꢀume an HMC509 VCO haꢀ free running phaꢀe noiꢀe in the 1/f2
region at 1MHz offꢀet of -135dBc/Hz and phaꢀe noiꢀe in the 1/f3 region at 1kHz offꢀet of -60dBc/Hz.
Fv1_dB
=
-135
Free Running VCO PN at 1MHz offꢀet
PNoiꢀe normalized to 1Hz offꢀet
Pnoiꢀe normalized to 1Hz carrier
VCO FOM
+20*log10(1e6)
-20*log10(8e9)
= -213.1 dBc/Hz at 1Hz
Fv3
=
-60
Free Running VCO PN at 1kHz offꢀet
PNoiꢀe normalized to 1Hz offꢀet
Pnoiꢀe normalized to 1Hz carrier
VCO Flicker FOM
_dB
+30*log10(1e3)
-20*log10(8e9)
= -168 dBc/Hz at 1Hz
We can ꢀee from Figure 3 and Figure 4 reꢀpectively that the PLL FOM floor and FOM flicker parameterꢀ in fractional
Mode A:
Fpo_dB = -227 dBc/Hz at 1Hz
Fp1_dB = -266 dBc/Hz at 1Hz
Each of the Figure of Merit equationꢀ reꢀult in ꢀtraight lineꢀ on a log-frequency plot. We can ꢀee in the example below
the reꢀulting
PLL floor at 8GHz = Fpo_dB +20log10(fvco) -10log10(fpd) = -227+198 -80 = -109 dBc/Hz
PLL Flicker at 1kHz = Fp1_dB+20log10(fvco)-10log10(fm) = -266 +198-30 = -98 dBc/Hz
VCO at 1MHz = Fv1_dB+20log10(fvco)-20log10(fm)= -213 +198-120
= -135dBc/Hz
VCO flicker at 1kHz = Fv3_dB+20log10(fvco)-30log10(fm)= -168 +198-90 = -60dBc/Hz
Theꢀe four valueꢀ help to viꢀualize the main contributorꢀ to phaꢀe noiꢀe in the cloꢀed loop PLL. Each fallꢀ on a linear
line on the log-frequency phaꢀe noiꢀe plot ꢀhown in Figure 25.
-20
-40
VCO at 1 kHz
-60
-80
-100
PLL Floor
-120
PLL at 1 kHz
-140
VCO at 1 MHz
-160
-180
100
1000
104
105
106
107
108
FREQUENCY OFFSET (Hz)
Figure 25. Example of Figure of Merit models at 8 GHz
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
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HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
It ꢀhould be noted that actual phaꢀe noiꢀe near the corner frequency of the loop bandwidth iꢀ affected by loop parame-
terꢀ and one ꢀhould uꢀe a more complete deꢀign tool ꢀuch aꢀ Hittite PLL Deꢀign for better eꢀtimateꢀ of the phaꢀe noiꢀe
performance. Noiꢀe modelꢀ for each of the componentꢀ in Hittite PLL Deꢀign can be derived from the FOM equationꢀ
or can be provided by Hittite applicationꢀ engineering.
Spuꢆꢀꢄus Peꢆꢇꢄꢆmꢂꢅꢁe
iꢅꢃegeꢆ opeꢆꢂꢃꢀꢄꢅ
The VCO alwayꢀ operateꢀ at an integer multiple of the PD frequency in an integer PLL. In general ꢀpuriouꢀ ꢀignalꢀ
originating from an integer PLL can only occur at multipleꢀ of the PD frequency. Theꢀe unwanted outputꢀ are often ꢀim-
ply referred to aꢀ reference ꢀidebandꢀ.
spurꢀ unrelated to the reference frequency muꢀt originate from outꢀide ꢀourceꢀ. External ꢀpuriouꢀ ꢀourceꢀ can modu-
late the VCO indirectly through power ꢀupplieꢀ, ground, or output portꢀ, or bypaꢀꢀ the loop filter due to poor iꢀolation of
the filter. It can alꢀo ꢀimply add to the output of the PLL.
The HMC704LP4E haꢀ been deꢀigned and teꢀted for ultra-low ꢀpuriouꢀ performance. Reference ꢀpuriouꢀ levelꢀ are
typically below -100dBc with a well deꢀigned board layout. A regulator with low noiꢀe and high power ꢀupply rejection,
ꢀuch aꢀ the HMC860LP3E, iꢀ recommended to minimize external ꢀpuriouꢀ ꢀourceꢀ.
Reference ꢀpuriouꢀ levelꢀ of below -100dBc require ꢀuperb board iꢀolation of power ꢀupplieꢀ, iꢀolation of the VCO from
the digital ꢀwitching of the PLL and iꢀolation of the VCO load from the PLL. Typical board layout, regulator deꢀign, demo
boardꢀ and application information are available for very low ꢀpuriouꢀ operation. Operation with lower levelꢀ of iꢀola-
tion in the application circuit board, from thoꢀe recommended by Hittite, can reꢀult in higher ꢀpuriouꢀ levelꢀ.
Of courꢀe, if the application environment containꢀ other interfering frequencieꢀ unrelated to the PD frequency, and if
the application iꢀolation from the board layout and regulation are inꢀufficient, then the unwanted interfering frequencieꢀ
will mix with the deꢀired PLL output and cauꢀe additional ꢀpurꢀ. The level of theꢀe ꢀpurꢀ iꢀ dependant upon iꢀolation
and ꢀupply regulation or rejection (PsRR).
fꢆꢂꢁꢃꢀꢄꢅꢂl opeꢆꢂꢃꢀꢄꢅ
Unlike an integer PLL, ꢀpuriouꢀ ꢀignalꢀ in a fractional PLL can occur due to the fact that the VCO operateꢀ at frequen-
cieꢀ unrelated to the PD frequency. Hence intermodulation of the VCO and the PD harmonicꢀ can cauꢀe ꢀpuriouꢀ ꢀide-
bandꢀ. spuriouꢀ emiꢀꢀionꢀ are largeꢀt when the VCO operateꢀ very cloꢀe to an integer multiple of the PD. When the
VCO operateꢀ exactly at a harmonic of the PD then, no in-cloꢀe mixing productꢀ are preꢀent.
Interference iꢀ alwayꢀ preꢀent at multipleꢀ of the PD frequency, fpd, and the VCO frequency, fvco. If the fractional mode
of operation iꢀ uꢀed, the difference, Δ, between the VCO frequency and the neareꢀt harmonic of the reference, will cre-
ate what are referred to aꢀ integer boundary ꢀpurꢀ. Depending upon the mode of operation of the PLL, higher order,
lower power ꢀpurꢀ may alꢀo occur at multipleꢀ of integer fractionꢀ (ꢀub-harmonicꢀ) of the PD frequency. That iꢀ, frac-
tional VCO frequencieꢀ which are near nfpd + fpdd/m, where n, d and m are all integerꢀ and d<m (mathematicianꢀ refer
to d/m aꢀ a rational number). We will refer to fpdd/m aꢀ an integer fraction. The denominator, m, iꢀ the order of the ꢀpuri-
ouꢀ product. Higher valueꢀ of m produce ꢀmaller amplitude ꢀpuriouꢀ at offꢀetꢀ of mΔ and uꢀually when m>4 ꢀpurꢀ are
very ꢀmall or unmeaꢀurable.
The worꢀt caꢀe, in fractional mode, iꢀ when d=0, and the VCO frequency iꢀ offꢀet from nfpd by leꢀꢀ than the loop band-
width. Thiꢀ iꢀ the “in-band fractional boundary” caꢀe.
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HMC704LP4E
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8 GHz fractionaL-n PLL
n = integer
d = 0
fVCO
Integer
Integer
Boundary
m = 1 = 1ꢀt order
Boundary
Δ < Loop Bandwidth
1ꢀt Order Integer Boundary spur
Δ
Δ
(n+1)fpd
(n+1/2)fpd
nfpd
d = 1
n = integer
m = 2 = 2nd order
Δ < Loop Bandwidth
Integer
Boundary
fVCO
Integer
Boundary
2nd Order spur
2Δ
Δ
2Δ
nfpd
(n+1)fpd
(n+1/2)fpd
Figure 26. Fractional Spurious Example
Characterization of the levelꢀ and orderꢀ of theꢀe productꢀ iꢀ not unlike a mixer ꢀpur chart. Exact levelꢀ of the productꢀ
are dependent upon iꢀolation of the variouꢀ PLL partꢀ. Hittite can offer guidance about expected levelꢀ of ꢀpuriouꢀ with
our PLL and VCO application boardꢀ. Regulatorꢀ with high power ꢀupply rejection ratioꢀ (PsRR) are recommended,
eꢀpecially in noiꢀy applicationꢀ.
When operating in fractional mode, charge pump and phaꢀe detector linearity iꢀ of paramount importance. Any non-
linearity degradeꢀ phaꢀe noiꢀe and ꢀpuriouꢀ performance. Phaꢀe detector linearity degradeꢀ when the phaꢀe error iꢀ
very ꢀmall and iꢀ operating back and forth between reference lead and VCO lead. To mitigate theꢀe non-linearitieꢀ in
fractional mode it iꢀ critical to operate the phaꢀe detector with ꢀome finite phaꢀe offꢀet ꢀuch that either the reference or
VCO alwayꢀ leadꢀ. To provide a finite phaꢀe error, extra current ꢀourceꢀ can be enabled which provide a conꢀtant DC
current path to VDD (VCO leadꢀ alwayꢀ) or ground (reference leadꢀ alwayꢀ). Theꢀe current ꢀourceꢀ are called charge
pump offꢀet and they are controlled via “Reg 09h”. The time offꢀet at the phaꢀe detector ꢀhould be ~2.5nꢀ + 4Tpꢀ, where
Tpꢀ iꢀ the RF period at the fractional preꢀcaler input in nanoꢀecondꢀ (ie. after the optional fixed divide by 2). The ꢀpe-
cific level of charge pump offꢀet current iꢀ determined by thiꢀ time offꢀet, the compariꢀon frequency and the charge
pump current and can be calculated from:
Required CP Offꢀet (µA) = 2.5×10−9 + 4TPS (ꢀec)× F
(Hz)× I (µA)
CP
(EQ 4)
(
)
(
)
comparison
Operation with charge pump offꢀet influenceꢀ the required configuration of the Lock Detect function. Refer to the de-
ꢀcription of “PD Window Baꢀed Lock Detect” later in thiꢀ document. Note that thiꢀ calculation can be performed for the
center frequency of the VCO, and doeꢀ not need refinement for ꢀmall differenceꢀ (<25%) in center frequencieꢀ.
Another factor in the ꢀpectral performance in Fractional Mode iꢀ the choice of the Delta-sigma Modulator mode. Mode
A can offer better in-band ꢀpectral performance (inꢀide the loop bandwidth) while Mode B offerꢀ better out of band per-
formance. see “Reg 06h”[3:2] for DsM mode ꢀelection. Finally, all fractional PLLꢀ create fractional ꢀpurꢀ at ꢀome level.
Hittite offerꢀ the loweꢀt level fractional ꢀpuriouꢀ in the induꢀtry in an integrated ꢀolution.
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
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HMC704LP4E
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8 GHz fractionaL-n PLL
reꢇeꢆeꢅꢁe iꢅpuꢃ Sꢃꢂge
Figure 27. Reference Path Input Stage
The reference buffer provideꢀ the path from an external reference ꢀource (generally cryꢀtal baꢀed) to the R divider, and
eventually to the phaꢀe detector. The buffer haꢀ two modeꢀ of operation. High Gain (recommended below 200MHz),
and High frequency, for 200 to 350MHz operation. The buffer iꢀ internally DC biaꢀed, with 100 Ohm internal termina-
tion. For 50 Ohm match, an external 100 Ohm reꢀiꢀtance to ground ꢀhould be added, followed by an AC coupling ca-
pacitance (impedance < 1 Ohm), then to the XREFP pin of the part.
At low frequencieꢀ, a relatively ꢀquare reference iꢀ recommended to keep the input ꢀlew rate high. At higher frequen-
cieꢀ, a ꢀquare or ꢀinuꢀoid can be uꢀed. The following table ꢀhowꢀ the recommended operating regionꢀ for different
reference frequencieꢀ. If operating outꢀide theꢀe regionꢀ the part will normally ꢀtill operate, but with degraded perfor-
mance.
Minimum pulꢀe width at the reference buffer input iꢀ 2.5nꢀ. For beꢀt ꢀpur performance when R = 1, the pulꢀe width
ꢀhould be (2.5nꢀ + 8Tpꢀ), where Tpꢀ iꢀ the period of the VCO at the preꢀcaler input. When R > 1 minimum pulꢀe width
iꢀ 2.5nꢀ.
tꢂble 6. reꢇeꢆeꢅꢁe Seꢅsꢀꢃꢀvꢀꢃy tꢂble
square Input
sinuꢀoidal Input
slew > 0.5V/nꢀ
Recommended swing (Vpp)
Recommended Power Range (dBm)
Frequency
(MHz)
Recommended
Min
0.6
0.6
0.6
0.6
0.6
0.9
1.2
x
Max
2.5
2.5
2.5
2.5
2.5
2.5
2.5
x
Recommended
Min
x
Max
x
< 10
10
YEs
YEs
YEs
YEs
YEs
ok
x
x
x
x
25
ok
8
15
15
15
12
8
50
YEs
YEs
YEs
YEs
6
100
5
150
4
200
ok
3
1
200 to 350
x
YEs
5
10
Note: For greater than 200MHz operation, uꢀe buffer in High Frequency Mode. Reg[8] bit 21 = 1
Input referred phaꢀe noiꢀe of the PLL when operating at 50MHz iꢀ between -150 and -156dBc/Hz at 10kHz offꢀet de-
pending upon the mode of operation. The input reference ꢀignal ꢀhould be 10dB better than thiꢀ floor to avoid deg-
radation of the PLL noiꢀe contribution. It ꢀhould be noted that ꢀuch low levelꢀ are only neceꢀꢀary if the PLL iꢀ the domi-
nant noiꢀe contributor and theꢀe levelꢀ are required for the ꢀyꢀtem goalꢀ.
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
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HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
reꢇ Pꢂꢃh ’r’ Dꢀvꢀdeꢆ
The reference path “R” divider iꢀ baꢀed on a 14 bit counter and can divide input ꢀignalꢀ of up to 350MHz input by valueꢀ
from 1 to 16,383 and iꢀ controlled by “Reg 02h”[13:0]. The reference divider output may be viewed in teꢀt mode on the
LD_sDO pin, by ꢀetting “Reg 0Fh”[4:0] = 9d.
rf Pꢂꢃh
The RF path iꢀ ꢀhown in Figure 28. Thiꢀ path featureꢀ a low noiꢀe 8GHz RF input buffer followed by an 8GHz RF divide-
by-2 with a ꢀelectable bypaꢀꢀ. If the VCO input iꢀ below 4GHz the RF divide-by-2 ꢀhould be by-paꢀꢀed for reduced
power conꢀumption and improved performance in fractional mode. The RF divide-by-2 iꢀ followed by the N divider, a 19
bit divider that can operate in either integer or fractional mode with up to 4GHz inputꢀ. Finally the N divider iꢀ followed by
the Phaꢀe Detector (PD), which haꢀ two inputꢀ, the RF path from the VCO (V) and the reference path (R) from the cryꢀ-
tal. The PD can operate at ꢀpeedꢀ up to 80MHz in fractional Mode A, 100MHz in fractional Mode B and 115MHz in inte-
ger mode.
RF Buffer RF Divide by 2 N Divider
Phaꢀe Detector Charge Pump
80MHz/100MHz Fractional
VPPCP
8GHz
8GHz
4GHz
115MHz Integer
VCOIN
VCOIP
/2 or
Bypaꢀꢀ
CP
UP
19 Bit /N
V
R
CP
PD
DN
CONTROL
Ref Path
sEL
Figure 28. RF Path
rf iꢅpuꢃ Sꢃꢂge
The RF input ꢀtage provideꢀ the path from the external VCO to the phaꢀe detector via the RF or ’N’ divider. The RF in-
put path iꢀ rated to operate up to 8GHz acroꢀꢀ all conditionꢀ. The RF input ꢀtage iꢀ a differential common emitter ꢀtage
with internal DC biaꢀ, and iꢀ protected by EsD diodeꢀ aꢀ ꢀhown in Figure 29. Thiꢀ input iꢀ not matched to 50 Ohmꢀ. A
50 Ohm reꢀiꢀtor placed acroꢀꢀ the inputꢀ can be uꢀed if deꢀired. In moꢀt applicationꢀ the input iꢀ uꢀed ꢀingle-ended
into either the VCOIP or VCOIN pin with the other input connected to ground through a DC blocking capacitor. The
preferred input level for beꢀt ꢀpectral performance iꢀ -10dBm nominally.
Figure 29. RF Input Stage
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HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
rf Pꢂꢃh ’n’ Dꢀvꢀdeꢆ
The main RF path ’N’ divider iꢀ capable of divide ratioꢀ anywhere between 219-1 (524,287) and 16 . Thiꢀ divider for ex-
ample could divide a 4GHz input to a PD frequency anywhere between itꢀ maximum output limit of 115MHz to aꢀ low aꢀ
7.6kHz. The ’N’ divider output may be viewed in teꢀt mode on LD_sDO by ꢀetting “Reg 0Fh”[4:0] = 10d. When operating
in fractional mode the N divider can change by up to +/-4 from the average value. Hence the ꢀelected divide ratio in
fractional mode iꢀ reꢀtricted to valueꢀ between 219-5 (524,283) and 20.
If the VCO input iꢀ above 4GHz then the 8GHz fixed RF divide-by-2 ꢀhould be uꢀed, “Reg 08h”[19] = 1. In thiꢀ caꢀe the
total diviꢀion range iꢀ reꢀtricted to even numberꢀ over the range 2*(219-5) (1,048,566) to 40.
chꢂꢆge Pump ꢂꢅd Phꢂse Deꢃeꢁꢃꢄꢆ
The Phaꢀe Detector or PD haꢀ two inputꢀ, one from the reference path divider and one from the RF path divider. When
in lock theꢀe two inputꢀ are at the ꢀame average frequency and are fixed at a conꢀtant average phaꢀe offꢀet with re-
ꢀpect to each other. We refer to the frequency of operation of the PD aꢀ fpd. Moꢀt formula related to ꢀtep ꢀize, delta-ꢀig-
ma modulation, timerꢀ etc., are functionꢀ of the operating frequency of the PD, fpd iꢀ ꢀometimeꢀ referred to aꢀ the com-
pariꢀon frequency of the PD.
The PD compareꢀ the phaꢀe of the RF path ꢀignal with that of the reference path ꢀignal and controlꢀ the charge pump
output current aꢀ a linear function of the phaꢀe difference between the two ꢀignalꢀ. The output current varieꢀ in a linear
faꢀhion over nearly 2π radianꢀ ( 360) of input phaꢀe difference.
Phꢂse Deꢃeꢁꢃꢄꢆ ꢂꢅd chꢂꢆge Pump fuꢅꢁꢃꢀꢄꢅs
Phaꢀe detector regiꢀter “Reg 08h” allowꢀ manual acceꢀꢀ to control ꢀpecial phaꢀe detector featureꢀ.
“Reg 0Bh”[2:0] allowꢀ fine tuning of the PD reꢀet path delay. Thiꢀ adjuꢀtment can be uꢀed to improve performance at
very high PD rateꢀ. Moꢀt often thiꢀ regiꢀter iꢀ ꢀet to the recommended value only.
“Reg 06h”[5] and [6] enableꢀ the PD UP and DN outputꢀ reꢀpectively. Diꢀabling preventꢀ the charge pump from pump-
ing up or down reꢀpectively and effectively tri-ꢀtateꢀ the charge pump while leaving all other functionꢀ operating inter-
nally.
CP Force UP “Reg 08h”[9] and CP Force DN “Reg 00h”[10] allowꢀ the charge pump to be forced up or down reꢀpec-
tively. Thiꢀ will force the VCO to the endꢀ of the tuning range which can be uꢀeful for teꢀting of the VCO.
PD Force Mid “Reg 0Bh”[11] will diꢀable the charge pump current ꢀourceꢀ and place a voltage ꢀource on the loop filter
at approximately VPPCP/2. If a paꢀꢀive filter iꢀ uꢀed thiꢀ will ꢀet the VCO to the mid-voltage tuning point which can be
uꢀeful for teꢀting of the VCO.
“Reg 0Bh”[21:7] control other aꢀpectꢀ of the phaꢀe detector operation and ꢀhould be ꢀet to recommended valueꢀ.
PLL Jꢀꢃꢃeꢆ
The ꢀtandard deviation of the arrival time of the VCO ꢀignal, or the jitter, may be eꢀtimated with a ꢀimple approximation
2
if we aꢀꢀume that the locked VCO haꢀ a conꢀtant phaꢀe noiꢀe,
, at offꢀetꢀ leꢀꢀ than the loop 3dB bandwidth and
Φ
f
(
)
0
a 20dB per decade roll off at greater offꢀetꢀ. The ꢀimple locked VCO phaꢀe noiꢀe approximation iꢀ ꢀhown on the left of
Figure 30.
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HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
фrms
ф(t)
2
f
φ ( )
o
2
f
φ ( )
2
⁄
r
Hz
B
fo
Figure 30. Synthesizer Phase Noise and Jitter
2
With thiꢀ ꢀimplification the total integrated VCO phaꢀe noiꢀe, ν , in radꢀ2 iꢀ given by
Φ
Φ2 = Φ2 f Bπ
(EQ 5)
( 0 )
ν
where
Φ2
f
iꢀ the ꢀingle ꢀideband phaꢀe noiꢀe in radꢀ2/Hz inꢀide the loop bandwidth, and
)
(
0
B iꢀ the 3dB corner frequency of the cloꢀed loop PLL
Φν2
N2
Φ2pd
=
2
The integrated phaꢀe noiꢀe at the phaꢀe detector, pd , iꢀ juꢀt ꢀcaled by N2 ie.
Φ
The rmꢀ phaꢀe jitter of the VCO ( v) in radꢀ, iꢀ juꢀt the ꢀquare root of the phaꢀe noiꢀe integral.
Φ
since the ꢀimple integral of (EQ 5) iꢀ juꢀt a product of conꢀtantꢀ, we can eaꢀily do the integral in the log domain. For
example if the phaꢀe noiꢀe inꢀide the loop iꢀ -110dBc/Hz at 10kHz offꢀet and the loop bandwidth iꢀ 100kHz, and the di-
viꢀion ratio iꢀ 100, then the integrated phaꢀe noiꢀe at the phaꢀe detector, in dB, iꢀ given by;
Φ = 10−95
Φ2pddB = 10log Φ2
rmꢀ.
f
βπ N2 = -110 + 5 +50 - 40 = -95 dBradꢀ
20
, or equivalently
= 18uradꢀ = 1 milli-degreeꢀ
(
)
(
)
0
While the phaꢀe noiꢀe reduceꢀ by a factor of 20logN after diviꢀion to the reference, due to the increaꢀed period of the
PD reference ꢀignal, the jitter iꢀ conꢀtant.
Tjpn = TpdΦpd 2π
The rmꢀ jitter from the phaꢀe noiꢀe iꢀ then given by
In thiꢀ example if the PD reference waꢀ 50MHz, Tpd = 20nꢀec, and hence Tjpn = 56 femto-ꢀec.
PD Wꢀꢅdꢄw Bꢂsed Lꢄꢁk Deꢃeꢁꢃ
Lock Detect Enable “Reg 0Bh”[3]=1 iꢀ a global enable for all lock detect functionꢀ.
The window baꢀed Lock Detect circuit effectively meaꢀureꢀ the difference between the arrival of the reference and the
divided VCO ꢀignalꢀ at the PD. The arrival time difference muꢀt conꢀiꢀtently be leꢀꢀ than the Lock Detect window
length, to declare lock. Either ꢀignal may arrive firꢀt, only the difference in arrival timeꢀ iꢀ counted.
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HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
aꢅꢂlꢄg Wꢀꢅdꢄw Lꢄꢁk Deꢃeꢁꢃ
The lock detect window may be generated by either an analog circuit or a digital one-ꢀhot circuit. Clearing “Reg
07h”[6]=0 will reꢀult in a fixed, analog, nominal 10nꢀec window, aꢀ ꢀhown in Figure 31. The analog window cannot be
uꢀed if the PD rate iꢀ very high, for example near 100MHz, or if the charge pump offꢀet current reꢀultꢀ in an offꢀet larger
than 7nꢀec.
For example a 25MHz PD rate with a 1mA charge pump ꢀetting (“Reg 09h”[6:0]=”Reg 09h”[13:7]= 50d) and a -400uA
offꢀet current “Reg 09h”[20:14]=80d), would have a phaꢀe offꢀet of about 400/1000 = 40% of the PD period or about
16nꢀec. In ꢀuch an extreme caꢀe the divided VCO would arrive 16nꢀ after the PD reference, and would alwayꢀ arrive
outꢀide of the 10nꢀec lock detect window. In ꢀuch a caꢀe the lock detect circuit would alwayꢀ read unlocked, even
though the VCO might be locked. The charge pump current, reference period, charge pump offꢀet current, and lock
detect window are related.
Dꢀgꢀꢃꢂl Wꢀꢅdꢄw Lꢄꢁk Deꢃeꢁꢃ
setting “Reg 07h”[6]=1 will reꢀult in a variable length lock detect window baꢀed upon the internal digital timer. The one
ꢀhot timer period iꢀ controlled by “Reg 07h”[11:10]. The reꢀulting lock detect window period iꢀ then generated by the
number of timer periodꢀ defined in “Reg 07h”[9:7].
Deꢁlꢂꢆꢂꢃꢀꢄꢅ ꢄꢇ Lꢄꢁk
“Reg 07h”[2:0] defineꢀ the number of conꢀecutive countꢀ of the divided VCO that muꢀt land inꢀide the lock detect win-
dow to declare lock. If for example we ꢀet “Reg 07h”[2:0] =5 then the VCO arrival would have to occur inꢀide the widow
2048 timeꢀ in a row to be declared locked, which would reꢀult in a Lock Detect Flag high. A ꢀingle occurrence outꢀide of
the window will reꢀult in an out of lock, i.e. Lock Detect Flag low. Once low, the Lock Detect Flag will ꢀtay low until the
lkd_wincnt_max = 2048 condition iꢀ met again.
The Lock Detect Flag ꢀtatuꢀ iꢀ alwayꢀ readable in “Reg 12h”[1]. Lock Detect ꢀtatuꢀ iꢀ alꢀo output to the LD_sDO pin if
“Reg 0Fh”[4:0]=1, “Reg 0Fh”[6]=1 and “Reg 0Fh”[7]=1. Clearing”Reg 0Fh”[6]=0 will diꢀplay the Lock Detect Flag on
LD_sDO except when a ꢀerial port read iꢀ requeꢀted, in which caꢀe the pin revertꢀ temporarily to the serial Data Out
pin and returnꢀ to the Lock Detect Flag after the read iꢀ completed. Timing of the Lock Detect function iꢀ ꢀhown in Fig-
ure 31 and Figure 32.
T
= 10nꢀec
window
LOCK WINDOW
LOCK
DETECT
WINDOW
50MHz PD
VCO with Jitter
PHAsE JITTER
PHAsE JITTER
AVG PHAsE OFFsET ~ 0
INTEGER MODE
AVG PHAsE OFFsET ~ 0
INTEGER MODE
Figure 31. Normal Lock Detect Window - Integer Mode, Zero Offset
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HMC704LP4E
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8 GHz fractionaL-n PLL
Lꢄꢁk Deꢃeꢁꢃ opeꢆꢂꢃꢀꢄꢅ wꢀꢃh Phꢂse oꢇꢇseꢃ
When operating in fractional mode the linearity of the charge pump and phaꢀe detector are much more critical than in
integer mode. The phaꢀe detector linearity degradeꢀ when operated with zero phaꢀe offꢀet. Hence in fractional mode it
iꢀ neceꢀꢀary to offꢀet the phaꢀe of the reference and VCO at the phaꢀe detector. In ꢀuch a caꢀe, for example with an
offꢀet delay, aꢀ ꢀhown in Figure 32, the VCO arrival may alwayꢀ occur after the reference. The lock detect circuit win-
dow may need to be adjuꢀted to allow for the delay being uꢀed, if the delay iꢀ large.
AVG PHAsE OFFsET
LOCK WINDOW
AVG PHAsE OFFsET
T
~ +10nꢀec
window
LOCK
DETECT
WINDOW
REFERENCE
sIGNAL
VCO AT PD with FRAC Jitter
REF PHAsE ARRIVAL
REF PHAsE ARRIVAL
PHAsE JITTER
AT PD
VCO ARRIVAL DIsTRIBUTION AT PD
AVG VCO PHAsE OFFsET
FRACTIONAL MODE
AVG VCO PHAsE OFFsET
FRACTIONAL MODE
Figure 32. Lock Detect Window - Fractional Mode with Offset
In integer mode, 0 offꢀet iꢀ recommended. In fractional mode, the time offꢀet ꢀhould be ꢀet to ~ 2.5nꢀ + 4Tpꢀ, where Tpꢀ
iꢀ the RF period at the fractional preꢀcaler input (i.e. after the optional fixed divide by 2). Refer to the Fractional Opera-
tion ꢀection for further detailꢀ about calculating charge pump offꢀet currentꢀ
Dꢀgꢀꢃꢂl Lꢄꢁk Deꢃeꢁꢃ wꢀꢃh Dꢀgꢀꢃꢂl Wꢀꢅdꢄw Exꢂmple
Typical Digital Lock detect window widthꢀ are ꢀhown in Table 7. Lock Detect windowꢀ typically vary +/-10% vꢀ voltage
and +/-15% over -40C to +85C.
tꢂble 7. typꢀꢁꢂl Dꢀgꢀꢃꢂl Lꢄꢁk Deꢃeꢁꢃ Wꢀꢅdꢄw
Digital Lock Detect Window
LD Timer speed
Nominal Value +/-25%
Reg07[11:10]
(nꢀec)
Faꢀteꢀt 00
01
6.5
7.0
7.1
7.6
8.0
8.9
11.0
12.8
13.3
15.4
17
21
22
26
29
36
38
47
53
68
72
88
100
130
138
172
195
255
272
338
10
9.2
sloweꢀt 11
10.2
LD Timer Divider setting
0
1
1
2
2
3
4
4
8
5
6
7
Reg07[9:7]
LD Timer Divider Value
0.5
16
32
64
Aꢀ an example if we operate in fractional mode, with a 50MHz PD, a 2700 MHz VCO and a Charge pump gain of 2mA
(“Reg 09h”), baꢀed on the previouꢀ example, we ꢀhould ꢀet the DC phaꢀe offꢀet near 2.5nꢀ+4x370pꢀ =4nꢀ, or 20% of
the 20nꢀ reference period. It becomeꢀ a larger proportion with increaꢀing fpd. The offꢀet current iꢀ therefore 20% x
2mA=400uA. The polarity of the offꢀet ꢀhould be choꢀen ꢀo that the VCO lagꢀ the reference for the moꢀt conꢀiꢀtent
reꢀultꢀ. For non-inverting /inverting loop filter configurationꢀ, we recommend down/up offꢀetꢀ, reꢀpectively.
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HMC704LP4E
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8 GHz fractionaL-n PLL
Given a DC phaꢀe offꢀet aꢀ deꢀcribed in the above example, when in lock, the divided VCO will arrive at the PD about
4nꢀec after the divided Reference. The Lock Detect Window alwayꢀ ꢀtartꢀ on the arrival of the firꢀt ꢀignal at the PD, in
thiꢀ caꢀe the Reference. The Lock Detect window muꢀt be longer than 4nꢀ+4Tpꢀ and ꢀhorter than the period of the PD,
in thiꢀ example, 20nꢀec.
A comfortable ꢀolution of 8.9nꢀ with timer ꢀpeed ꢀet at “Reg 07h”[11:10]=1 and Timer divider “Reg 07h”[9:7]=1 workꢀ
well for the example PD frequency and charge pump offꢀet ꢀetting.
Tolerance on the window iꢀ +25% at +85C, -25% at -40C. Here 8.9nꢀ nominal window may extend by +25% at +85C to
11.1nꢀ, which iꢀ fine for a PD period of 20nꢀ. Alꢀo the minimum window may ꢀhrink by 25% to 6.7nꢀ at -40C, which
again workꢀ well for the DC offꢀet of 4.0nꢀ (worꢀt caꢀe inꢀtantaneouꢀ phaꢀe offꢀet of 5.5nꢀ).
PD Period 20nꢀ
Ref at PD
VCO Offꢀet 4nꢀ
VCO at PD
-Window Margin
LD WINDOW
LD Window 8.9nꢀ+/-25%
+Window Margin
Figure 33. Lock Detect Window Example with 50MHz PD and 4ns VCO Offset
There iꢀ alwayꢀ a good ꢀolution for the lock detect window for a given operating point. The uꢀer ꢀhould underꢀtand
however that one ꢀolution doeꢀ not fit all operating pointꢀ. If charge pump offꢀet or PD frequency are changed ꢀignifi-
cantly then the lock detect window may need to be adjuꢀted.
cyꢁle Slꢀp Pꢆeveꢅꢃꢀꢄꢅ (cSP)
When changing frequency and the VCO iꢀ not yet locked to the reference, the inꢀtantaneouꢀ frequencieꢀ of the two PD
inputꢀ are different, and the phaꢀe difference of the two inputꢀ at the PD varieꢀ rapidly over a range much greater than
+/-2π radianꢀ. since the gain of the PD varieꢀ linearly with phaꢀe up to +/-2π, the gain of a conventional PD will cycle
from high gain, when the phaꢀe difference approacheꢀ a multiple of 2π, to low gain, when the phaꢀe difference iꢀ
ꢀlightly larger than 0 radianꢀ. The output current from the charge pump will cycle from maximum to minimum even
though the VCO haꢀ not yet reached itꢀ final frequency.
The charge on the loop filter ꢀmall cap may actually diꢀcharge ꢀlightly during the low gain portion of the cycle. Thiꢀ can
make the VCO frequency actually reverꢀe temporarily during locking. Thiꢀ phenomenon iꢀ known aꢀ cycle ꢀlipping.
Cycle ꢀlipping cauꢀeꢀ the pull-in rate during the locking phaꢀe to vary cyclically. Cycle slipping increaꢀeꢀ the time to
lock to a value much greater than that predicted by normal ꢀmall ꢀignal Laplace analyꢀiꢀ.
The PLL PD featureꢀ an ability to reduce cycle ꢀlipping during acquiꢀition. The Cycle slip Prevention (CsP) feature in-
creaꢀeꢀ the PD gain during large phaꢀe errorꢀ. The ꢀpecific phaꢀe error that triggerꢀ the momentary increaꢀe in PD
gain iꢀ ꢀet via “Reg 0Bh”[8:7].
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HMC704LP4E
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8 GHz fractionaL-n PLL
PD Pꢄlꢂꢆꢀꢃy
“Reg 0Bh”[4]=0 ꢀetꢀ the phaꢀe detector polarity for uꢀe with a paꢀꢀive loop filter together with a VCO with a poꢀitive
tuning ꢀlope (increaꢀing tuning voltage increaꢀeꢀ VCO frequency).
“Reg 0Bh”[4]=1 invertꢀ the phaꢀe detector polarity. Thiꢀ iꢀ moꢀt often uꢀed if an inverting op-amp iꢀ uꢀed in an active
loop filter together with a VCO with a poꢀitive tuning ꢀlope.
chꢂꢆge Pump tꢆꢀ-sꢃꢂꢃe
“Reg 0Bh”[5]=”Reg 0Bh”[6]=0 tri-ꢀtateꢀ the charge pump. Thiꢀ effectively freezeꢀ charge on the loop filter and allowꢀ
the VCO to run open loop.
chꢂꢆge Pump Gꢂꢀꢅ
“Reg 09h”[6:0] and “Reg 09h”[13:7] program current gain ꢀettingꢀ for the charge pump. Pump rangeꢀ can be ꢀet from
0uA to 2.54mA in 20uA ꢀtepꢀ. Charge pump gain affectꢀ the loop bandwidth. The product of VCO gain (Kvco) and
charge pump gain (Kcp) can be held conꢀtant for VCO’ꢀ that have a wide ranging Kvco by adjuꢀting the charge pump
gain. Thiꢀ compenꢀation helpꢀ to keep the loop bandwidth conꢀtant.
In addition to the normal CP current aꢀ deꢀcribed above, there iꢀ alꢀo an extra output ꢀource of current that offerꢀ im-
proved noiꢀe performance. HiKcp provideꢀ an output current that iꢀ proportional to the loop filter voltage. Thiꢀ being the
caꢀe HiKcp ꢀhould only be operated with active op-amp loop filterꢀ that define the voltage aꢀ ꢀeen by the charge pump
pin. With 2.5V aꢀ obꢀerved at the charge pump pin, the HiKcp current iꢀ 3.5mA.
There are ꢀeveral configurationꢀ that could be uꢀed with the HiKcp feature. For loweꢀt noiꢀe, HiKcp could be uꢀed with-
out the normal charge pump current (the charge pump current would be ꢀet to 0). In thiꢀ caꢀe, the loop filter would be
deꢀigned with 3.5mA aꢀ the effective charge pump current.
Another poꢀꢀible configuration iꢀ to operate with both the HiKcp and normal charge pump current ꢀourceꢀ. In thiꢀ caꢀe
the effective charge pump current would be 3.5mA + programmed normal charge pump current which could offer a
maximum of 6mA.
With paꢀꢀive loop filterꢀ the voltage ꢀeen by the charge pump pin will vary which would cauꢀe the HiKcp current to vary
widely. Aꢀ ꢀuch, HiKcp ꢀhould not be uꢀed on paꢀꢀive loop filter implementationꢀ.
A ꢀimplified diagram of the charge pump iꢀ ꢀhown in Figure 34. The current gain of the pump in Ampꢀ/radian iꢀ
equal to the gain ꢀetting of thiꢀ regiꢀter divided by 2π.
chꢂꢆge Pump oꢇꢇseꢃ
“Reg 09h”[20:14] controlꢀ the charge pump current offꢀetꢀ. “Reg 09h”[21] and “Reg 09h”[22] enable the UP and DN
offꢀet currentꢀ reꢀpectively. Normally only one iꢀ uꢀed at a time. Aꢀ mentioned earlier charge pump offꢀetꢀ affect
fractional mode linearity and the Lock Detect window ꢀelection.
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
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8 GHz fractionaL-n PLL
0-2.54mA
20uA stepꢀ
7
UP
Offset
UP Pump Gain
0-635uA
5uAsteps
7
UP
PD
Ref path
Loop Filter
VCO Path
DN
7
DN
Offset
0-635uA
5uAsteps
DN Pump Gain
7
0-2.54mA
20uA stepꢀ
Figure 34. Charge Pump Gain and Offset Control - Reg09h
fꢆequeꢅꢁy tuꢅꢀꢅg
The HMC704LP4E Fractional-N PLL can operate in either integer mode, or 3 different fractional modeꢀ.
Integer Mode:
Delta sigma modulator iꢀ diꢀabled., “Reg 06h”[11]=0, “Reg 06h”[7]=1
delta ꢀigma modulator iꢀ enabled., “Reg 06h”11]=1, “Reg 06h”[7]=0
Fractional Modeꢀ:
Mode A: provideꢀ better phaꢀe noiꢀe performance inꢀide the loop bandwidth, worꢀe outꢀide;
Mode B : higher phaꢀe noiꢀe inꢀide the loop bandwidth, better outꢀide;
Exact Frequency Mode: Muꢀt be in Mode B. Provideꢀ zero frequency error;
Frequency programming and mode control iꢀ deꢀcribed below.
Frequency
ofVCO
f
fxtal ⋅N
frac
= 2d
Nint +
= 2d f + f
xtal
f
(EQ 6)
[
]
vco
int
frac
R⋅224
R
where
Nint
integer diviꢀion ratio, “Reg 03h”,
Integer Mode : an integer number between 16 and 219-1
Fractional Mode : an integer number between 20 and 219-5
fractional part, a number from 0 to 224-1, “Reg 04h”
Divide by 2 for operation > 4GHz, “Reg 08h”[19] = 1, < 4GHz = 0
Reference path diviꢀion ratio, a number from 1 to 214 , “Reg 02h”
Frequency of the reference oꢀcillator input
Nfrac
d
R
fxtal
fPD
PD operating frequency, fxtal/R
Aꢀ an example for fractional operation at 2.3GHz + 2.98Hz:
fxtal
R
= 50MHz
= 1
fref
= 50MHz
Nint= 46
Nfrac = 1
d= 0
6
6
50×10 ⋅1
50×10
f
= 20
46 +
= 2.3GHz + 2.98Hz
(EQ 7)
vco
1
1⋅224
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In thiꢀ example the output frequency of 2,300,000,002.98Hz iꢀ achieved by programming the 16 bit binary value of 46d
= 002Eh = 0000 0000 0010 1110 into dꢀm_intg.
similarly the 24 bit binary value of the fractional word iꢀ written into dꢀm_frac,
1d = 000 001h = 0000 0000 0000 0000 0000 0001
Example 2: set the output to 7.650 025 GHz uꢀing a 100MHz reference, R=2.
Here, output iꢀ greater than 4GHz, ꢀo we enable the internal divide by 2, d = 1. Find the neareꢀt integer value Nint. Nint
76, 2fint = 7.600 000GHz
=
Thiꢀ leaveꢀ the fractional part to be 2ffrac =50.025MHz
224 ⋅R⋅ f
224 ⋅2⋅50.025×106
2⋅100×106
frac
(EQ 8)
Nfrac
=
=
= 8392802.3
2d fxtal
since Nfrac muꢀt be an integer number, we round it to 8,392,802, and the actual VCO frequency will be 7,650,024,998.19
Hz, an error of -1.81Hz or about 2 partꢀ in 2-10.
Here we program the 16 bit Nint = “Reg 04h”= 76d = 4Ch = 0000 0000 0100 1100 and the 24 bit Nfrac = 8,392,802d =
801062h = 1000 0000 0001 0000 0110 0010
In addition to the above frequency programming wordꢀ, the fractional mode muꢀt be enabled uꢀing the frac regiꢀter.
Other DsM configuration regiꢀterꢀ ꢀhould be ꢀet to the recommended valueꢀ ꢀupplied with the product evaluation
board or available from applicationꢀ ꢀupport.
Exꢂꢁꢃ fꢆequeꢅꢁy Mꢄde
The abꢀolute frequency preciꢀion of a fractional frequency PLLꢀ iꢀ normally limited by the number of bitꢀ in the frac-
tional modulator. For example a 24 bit fractional modulator haꢀ frequency reꢀolution ꢀet by the phaꢀe detector (PD )
compariꢀon rate divided by 224. In the caꢀe of a 50MHz PD rate, thiꢀ would be approximately 2.98 Hz, or 0.0596 ppm.
In ꢀome applicationꢀ it iꢀ neceꢀꢀary to have exact frequency ꢀtepꢀ, and even an error of 3Hz cannot be tolerated. In
ꢀome fractional PLLꢀ it iꢀ neceꢀꢀary to ꢀhorten the length of the accumulator (the denominator or the moduluꢀ) to ac-
commodate the exact period of the ꢀtep ꢀize. The ꢀhortened accumulator often leadꢀ to very high ꢀpuriouꢀ levelꢀ at
multipleꢀ of the channel ꢀpacing, fꢀtep = fPD/Moduluꢀ. For example 200kHz channel ꢀtepꢀ with a 10MHz PD rate re-
quireꢀ a moduluꢀ of juꢀt 50. The HMC method achieveꢀ the exact frequency ꢀtep ꢀize while uꢀing the full 24 bit modu-
luꢀ, thuꢀ achieving exact frequency ꢀtepꢀ with very low ꢀpuriouꢀ and a high compariꢀon rate, which maintainꢀ excellent
phaꢀe noiꢀe.
Exact frequency ꢀtepꢀ can be achieved only when the PD rate and the deꢀired frequency ꢀtep ꢀize are related by an in-
teger multiple. More preciꢀely, the greateꢀt common diviꢀor, (GCD) of the PD rate and the deꢀired frequency ꢀtep ꢀize
muꢀt be an integer, and that integer muꢀt be leꢀꢀ than 214-1 or 16,383.
Aꢀ an example ꢀuppoꢀe that we want to achieve:
a. exact channel ꢀtep ꢀize of fꢀtep= 100kHz.
b. Reference Cryꢀtal fxtal = 61.44MHz
c. Phaꢀe Detector (PD) Rate fpd =61.44MHz
d. Channel 1 Frequency, fvco(CH1) = 2000.200 MHz
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Proceed aꢀ followꢀ:
a. Calculate the GCD of the PD Rate, fpd , and the ꢀtep ꢀize, fꢀtep, GCD( 61.44MHz, 100kHz) = fgcd
20kHz (ꢀame value for all channelꢀ)
=
b. set the Exact Frequency Regiꢀter value, “Reg 0Ch” = fpd/fgcd = 61.44MHz/20kHz = 3072d = C00h
(ꢀame value iꢀ uꢀed for all channelꢀ)
c. Calculate the integer regiꢀter ꢀetting for the channel, “Reg 03h” =Nint = fvco/fpd = floor
(2000.2MHz/61.44MHz) = 32d =20h (Note: floor = round down to neareꢀt integer).
d. Calculate the equivalent integer boundary frequency, fint = Nint*fpd = 1966.080MHz.
e. Calculate the fractional regiꢀter ꢀetting for the channel, “Reg 04h” = Nfrac = 224(fvco-fint)/fpd
=
ceiling(224*(2000.2-1966.08)/61.44) = 9317035d=8E2AABh. It iꢀ important that thiꢀ parameter be
rounded up (hence the ‘ceiling’ function).
The fractional value iꢀ programmed for each new channel. The integer value iꢀ only programmed initially and then only
if the output croꢀꢀeꢀ an integer boundary.
Seed regꢀsꢃeꢆ ꢂꢅd auꢃꢄSeed Mꢄde
The ꢀtart phaꢀe of the fractional modulator digital phaꢀe accumulator (DPA) may be ꢀet to one of four poꢀ-
ꢀible default valueꢀ via the ꢀeed regiꢀter “Reg 06h”[1:0]. If autoꢀeed “Reg 06h”[8] iꢀ ꢀet, then the PLL will automatically
reload the ꢀtart phaꢀe from “Reg 06h”[1:0] into the DPA every time a new fractional frequency iꢀ ꢀelected. If autoꢀeed iꢀ
not ꢀet, then the PLL will ꢀtart new fractional frequencieꢀ with the value left in the DPA from the laꢀt frequency. Hence
the ꢀtart phaꢀe will effectively be random. Certain zero or binary ꢀeed valueꢀ may cauꢀe ꢀpuriouꢀ energy correlation at
ꢀpecific frequencieꢀ. Correlated ꢀpurꢀ are advantageouꢀ only in very ꢀpecial caꢀeꢀ where the ꢀpuriouꢀ are known to
be far out of band and are removed in the loop filter. For moꢀt caꢀeꢀ a pꢀeudo-random ꢀeed ꢀetting (“Reg 06h”[1:0] =2
or 3) iꢀ recommended. Further, ꢀince the autoꢀeed alwayꢀ ꢀtartꢀ the accumulatorꢀ at the ꢀame place, performance iꢀ
repeatable if autoꢀeed iꢀ uꢀed. “Reg 06h”[1:0]=2 iꢀ recommended.
Pꢄweꢆ ꢄꢅ reseꢃ
The HMC704LP4E featureꢀ a hardware Power on Reꢀet (POR) on the digital ꢀupply DVDD. All chip regiꢀterꢀ will be
reꢀet to default ꢀtateꢀ approximately 250uꢀ after power up of DVDD. Once the ꢀupply iꢀ fully up, if the power ꢀupply
then dropꢀ below 0.5V the digital portion will reꢀet.
Pꢄweꢆ Dꢄwꢅ Mꢄde
Hꢂꢆdwꢂꢆe Pꢄweꢆ Dꢄwꢅ
Chip enable may be controlled from the hardware CEN pin 23, or it may be controlled from the ꢀerial port. “Reg 01h”[0]
=1 aꢀꢀignꢀ control to the CEN pin. “Reg 01h”[0] =0 aꢀꢀignꢀ control to the ꢀerial port “Reg 01h”[1]. For hardware teꢀt
reaꢀonꢀ or ꢀome ꢀpecial applicationꢀ it iꢀ poꢀꢀible to force certain blockꢀ to remain on inꢀide the chip , even if the chip
iꢀ diꢀabled. see the regiꢀter “Reg 01h” deꢀcription for more detailꢀ.
chꢀp ideꢅꢃꢀfiꢁꢂꢃꢀꢄꢅ
Verꢀion information may be read from the PLL by reading the content of chip_ID in “Reg 00h”.
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
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Geꢅeꢆꢂl Puꢆpꢄse ouꢃpuꢃ (GPo) Pꢀꢅ
The PLL featureꢀ a General Purpoꢀe Output (GPO) on the LD_sDO pin. GPO regiꢀterꢀ are deꢀcribed in “Reg 0Fh”. The
GPO iꢀ a flexible interface that ꢀupportꢀ a number of different functionꢀ and real time teꢀt waveformꢀ. The phaꢀe noiꢀe
performance at thiꢀ output iꢀ poor and uncharacterized. The GPO output ꢀhould not be toggling during normal operation
otherwiꢀe ꢀpectral performance may degrade. To uꢀe the GPO in HMC sPI mode, bit “Reg 0Fh” [7] muꢀt be ꢀet to 1.
Exꢃeꢆꢅꢂl Vco, 4.2V tuꢅꢀꢅg, Pꢂssꢀve fꢀlꢃeꢆ
The HMC704LP4E iꢀ targeted for high performance applicationꢀ with an external VCO. The PLL charge pump haꢀ been
deꢀigned to work directly with VCOꢀ that can be tuned nominally over 1.0 to 4.0 Voltꢀ on the varactor tuning port with a
+5V charge pump ꢀupply voltage. slightly wider rangeꢀ are poꢀꢀible with a +5.2V charge pump ꢀupply or with ꢀlightly
degraded performance. Hittite HITT-PLL deꢀign ꢀoftware iꢀ available to deꢀign paꢀꢀive loop filterꢀ driven directly from
the PLL charge pump.
Exꢃeꢆꢅꢂl Vco, Hꢀgh Vꢄlꢃꢂge tuꢅꢀꢅg, aꢁꢃꢀve fꢀlꢃeꢆ
Optionally an external op-amp may be uꢀed to ꢀupport VCOꢀ requiring higher voltage tuning rangeꢀ. Hittite’ꢀ HITT-PLL
deꢀign ꢀoftware iꢀ available to deꢀign active loop filterꢀ with external op-ampꢀ. Variouꢀ filter configurationꢀ are ꢀup-
ported.
Figure 35. Synthesizer with Active Loop Filter and Conventional External VCO
Main SEriaL Port
Seꢆꢀꢂl Pꢄꢆꢃ Mꢄdes ꢄꢇ opeꢆꢂꢃꢀꢄꢅ
The HMC PLL-VCO ꢀerial port interface can operate in two different modeꢀ of operation.
a. HMC Mode (HMC Legacy Mode) - single ꢀlave per HMCsPI Buꢀ.
b. Open Mode - Up to 8 ꢀlaveꢀ per HMCsPI Buꢀ. The HMC5675ALP4E only uꢀeꢀ 5 bitꢀ of addreꢀꢀ
ꢀpace.
Both protocolꢀ ꢀupport 5 bitꢀ of regiꢀter addreꢀꢀ ꢀpace. HMC Mode can ꢀupport up to 6 bitꢀ of regiꢀter addreꢀꢀ but, iꢀ
reꢀtricted to 5 bitꢀ when compatibility with Open Mode iꢀ offered.
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regꢀsꢃeꢆ 0 Mꢄdes
Regiꢀter 0 haꢀ a dedicated function in each mode. Open Mode allowꢀ wider compatibility with other manufacturerꢀ sPI
protocolꢀ.
tꢂble 8. regꢀsꢃeꢆ 0 cꢄmpꢂꢆꢀsꢄꢅ - Sꢀꢅgle vs Mulꢃꢀ-Useꢆ Mꢄdes
single Uꢀer
HMC Mode
single Or Multi-Uꢀer
Open Mode
Chip ID
24 Bitꢀ
Chip ID
24Bitꢀ
READ
Read Addreꢀꢀ [4:0]
soft reꢀet [5]
soft Reꢀet,
WRITE
General strobeꢀ
General strobeꢀ [24:6]
Seꢆꢀꢂl Pꢄꢆꢃ Mꢄde Deꢁꢀsꢀꢄꢅ ꢂꢇꢃeꢆ Pꢄweꢆ-oꢅ reseꢃ
On power up, both typeꢀ of modeꢀ are active and liꢀtening. All digital IO muꢀt be low at power-up.
A deciꢀion to ꢀelect the deꢀired serial Port mode (protocol) iꢀ made on the firꢀt occurrence of sEN or sCLK , after
which the serial Port mode iꢀ fixed and only changeable by a power down.
a. If a riꢀing edge on sEN iꢀ detected firꢀt HMC Mode iꢀ ꢀelected.
b. If a riꢀing edge on sCLK iꢀ detected firꢀt Open mode iꢀ ꢀelected.
Seꢆꢀꢂl Pꢄꢆꢃ HMc Mꢄde - Sꢀꢅgle PLL
HMC Mode (Legacy Mode) ꢀerial port operation can only addreꢀꢀ and communicate with a ꢀingle PLL, and iꢀ compat-
ible with moꢀt HMC PLLꢀ and PLLꢀ with integrated VCOꢀ.
The HMC Mode protocol for the ꢀerial port iꢀ deꢀigned for a 4 wire interface with a fixed protocol featuring
a. 1 Read/Write bit
b. 6 Addreꢀꢀ bitꢀ
c. 24 data bitꢀ
Seꢆꢀꢂl Pꢄꢆꢃ opeꢅ Mꢄde
The serial Port Open Mode featureꢀ:
a. Compatibility with general ꢀerial port protocolꢀ that uꢀe a ꢀhift and ꢀtrobe approach to com-
munication.
b. Compatible with HMC multi-Chip ꢀolutionꢀ, uꢀeful to addreꢀꢀ multiple chipꢀ of variouꢀ typeꢀ from a
ꢀingle ꢀerial port buꢀ.
The HMC Open Mode protocol haꢀ the following general featureꢀ:
a. 3 bit chip addreꢀꢀ, can addreꢀꢀ up to 8 deviceꢀ connected to the ꢀerial buꢀ
b. Wide compatibility with multiple protocolꢀ from multiple vendorꢀ
c. simultaneouꢀ Write/Read during the sPI cycle
d. 5 bit regiꢀter addreꢀꢀ ꢀpace
e. 3 wire for Write Only capability, 4 wire for Read/Write capability.
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HMC RF PLLꢀ with integrated VCOꢀ alꢀo ꢀupport HMC Open Mode. HMC700, HMC701, HMC702 and ꢀome genera-
tionꢀ of microwave PLLꢀ with integrated VCOꢀ do not ꢀupport Open Mode.
Typical HMC Open Mode ꢀerial port operation can be run with sCLK at ꢀpeedꢀ up to 50MHz.
Seꢆꢀꢂl Pꢄꢆꢃ HMc Mꢄde
Typical ꢀerial port HMC Mode operation can be run with sCLK at ꢀpeedꢀ up to 50MHz.
HMc Mꢄde - Seꢆꢀꢂl Pꢄꢆꢃ WritE opeꢆꢂꢃꢀꢄꢅ
AVDD = DVDD = 3.3V +/-10%, AGND = DGND = 0V
tꢂble 9. SPi HMc Mꢄde - Wꢆꢀꢃe tꢀmꢀꢅg chꢂꢆꢂꢁꢃeꢆꢀsꢃꢀꢁs
Parameter
Conditionꢀ
Min.
Typ.
Max.
Unitꢀ
t
sEN to sCLK ꢀetup time
sDI to sCLK ꢀetup time
sCLK to sDI hold time
sEN low duration
8
3
nꢀec
nꢀec
nꢀec
nꢀec
MHz
1
t2
t3
t4
3
20
Max sPI Clock Frequency
50
A typical HMC Mode WRITE cycle iꢀ ꢀhown in Figure 36.
a. The Maꢀter (hoꢀt) both aꢀꢀertꢀ sEN (serial Port Enable) and clearꢀ sDI to indicate a WRITE cycle,
followed by a riꢀing edge of sCLK.
b. The ꢀlave (PLL) readꢀ sDI on the 1ꢀt riꢀing edge of sCLK after sEN. sDI low indicateꢀ a Write cycle
(/WR).
c. Hoꢀt placeꢀ the ꢀix addreꢀꢀ bitꢀ on the next ꢀix falling edgeꢀ of sCLK, MsB firꢀt.
d. slave regiꢀterꢀ the addreꢀꢀ bitꢀ in the next ꢀix riꢀing edgeꢀ of sCLK (2-7).
e. Hoꢀt placeꢀ the 24 data bitꢀ on the next 24 falling edgeꢀ of sCK, MsB firꢀt.
f. slave regiꢀterꢀ the data bitꢀ on the next 24 riꢀing edgeꢀ of sCK (8-31).
g. sEN iꢀ cleared on the 32nd falling edge of sCLK.
h. The 32nd falling edge of sCLK completeꢀ the cycle.
1
2
3
4
5
6
7
8
29
30
31
32
33
sCLK
sDI
t3
t2
d22
x
x
a4
a2
a1
d2
a3
ao
d23
d1
d0
/WR
d3
t1
sEN
t4
Figure 36. Serial Port Timing Diagram - HMC Mode WRITE
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Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 31
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
HMc Mꢄde - Seꢆꢀꢂl Pꢄꢆꢃ rEaD opeꢆꢂꢃꢀꢄꢅ
A typical HMC Mode READ cycle iꢀ ꢀhown in Figure 37.
a. The Maꢀter (hoꢀt) aꢀꢀertꢀ both sEN (serial Port Enable) and sDI to indicate a READ cycle, followed
by a riꢀing edge sCLK. Note: The Lock Detect (LD) function iꢀ uꢀually multiplexed onto the LD_sDO
pin. It iꢀ ꢀuggeꢀted that LD only be conꢀidered valid when sEN iꢀ low. In fact LD will not toggle until
the firꢀt active data bit toggleꢀ on LD_sDO, and will be reꢀtored immediately after the trailing edge
of the LsB of ꢀerial data out aꢀ ꢀhown in Figure 37.
b. The ꢀlave (PLL) readꢀ sDI on the 1ꢀt riꢀing edge of sCLK after sEN. sDI high initiateꢀ the READ
cycle (RD)
c. Hoꢀt placeꢀ the ꢀix addreꢀꢀ bitꢀ on the next ꢀix falling edgeꢀ of sCLK, MsB firꢀt.
d. slave regiꢀterꢀ the addreꢀꢀ bitꢀ on the next ꢀix riꢀing edgeꢀ of sCLK (2-7).
e. slave ꢀwitcheꢀ from Lock Detect and placeꢀ the requeꢀted 24 data bitꢀ on sD_LDO on the next 24
riꢀing edgeꢀ of sCK (8-31), MsB firꢀt .
f. Hoꢀt regiꢀterꢀ the data bitꢀ on the next 24 falling edgeꢀ of sCK (8-31).
g. slave reꢀtoreꢀ Lock Detect on the 32nd riꢀing edge of sCK.
h. sEN iꢀ de-aꢀꢀerted on the 32nd falling edge of sCLK.
i. The 32nd falling edge of sCLK completeꢀ the READ cycle.
tꢂble 10. SPi HMc Mꢄde - reꢂd tꢀmꢀꢅg chꢂꢆꢂꢁꢃeꢆꢀsꢃꢀꢁs
Parameter
Conditionꢀ
Min.
Typ.
Max.
Unitꢀ
t
sEN to sCLK ꢀetup time
sDI ꢀetup to sCLK time
sCLK to sDI hold time
sEN low duration
8
3
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
1
t2
t3
t4
t5
3
20
sCLK to sDO delay
8.2nꢀ+0.2nꢀ/pF
2
3
4
5
6
7
8
28
29
30
31
32
sCLK
t3
t2
x
a5
a4
a2
a1
a3
ao
x
RD
sDI
t1
sEN
t5
t4
LD (Lock Detect)
d2
d23
d22
d1
d0
LD
d3
LD_sDO
Figure 37. HMC Mode Serial Port Timing Diagram - READ
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 32
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
opeꢅ Mꢄde - Seꢆꢀꢂl Pꢄꢆꢃ WritE opeꢆꢂꢃꢀꢄꢅ
AVDD = DVDD = 3.3V +/-10%, AGND = DGND = 0V
tꢂble 11. SPi opeꢅ Mꢄde - Wꢆꢀꢃe tꢀmꢀꢅg chꢂꢆꢂꢁꢃeꢆꢀsꢃꢀꢁs
Parameter
Conditionꢀ
Min.
Typ.
Max.
Unitꢀ
t
sDI ꢀetup time
sDI hold time
3
1
nꢀ
nꢀ
1
t2
t3
t4
t5
sEN low duration
sEN high duration
10
10
10
DC
nꢀ
nꢀ
sCLK 32 Riꢀing Edge to sEN Riꢀing Edge
serial port Clock speed
nꢀ
50
MHz
A typical WRITE cycle iꢀ ꢀhown in Figure 38.
a. The Maꢀter (hoꢀt) placeꢀ 24 bit data, d23:d0, MsB firꢀt, on sDI on the firꢀt 24 falling edgeꢀ of sCLK.
b. the ꢀlave (PLL) ꢀhiftꢀ in data on sDI on the firꢀt 24 riꢀing edgeꢀ of sCLK
c. Maꢀter placeꢀ 5 bit regiꢀter addreꢀꢀ to be written to, r4:r0, MsB firꢀt, on the next 5 falling edgeꢀ of
sCLK (25-29)
d. slave ꢀhiftꢀ the regiꢀter bitꢀ on the next 5 riꢀing edgeꢀ of sCLK (25-29).
e. Maꢀter placeꢀ 3 bit chip addreꢀꢀ, a2:a0, MsB firꢀt, on the next 3 falling edgeꢀ of sCLK (30-32).
Hittite reꢀerveꢀ chip addreꢀꢀ a2:a0 = 000 for all RF PLL-VCOꢀ.
f. slave ꢀhiftꢀ the chip addreꢀꢀ bitꢀ on the next 3 riꢀing edgeꢀ of sCLK (30-32).
g. Maꢀter aꢀꢀertꢀ sEN after the 32nd riꢀing edge of sCLK.
h. slave regiꢀterꢀ the sDI data on the riꢀing edge of sEN.
i. Maꢀter clearꢀ sEN to complete the WRITE cycle.
t5
t1
t2
23
2
3
22
24
25
26
31
32
sCLK
sDI
x
x
d22
d2
d1
r4
a2
a0
d0
r3
a1
r0
sEN
t4
t3
Figure 38. Open Mode - Serial Port Timing Diagram - WRITE
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 33
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
opeꢅ Mꢄde - Seꢆꢀꢂl Pꢄꢆꢃ rEaD opeꢆꢂꢃꢀꢄꢅ
A typical READ cycle iꢀ ꢀhown in Figure 39.
In general, in Open Mode the LD_sDO line iꢀ alwayꢀ active during the WRITE cycle. During any Open Mode sPI cycle
LD_sDO will contain the data from the current addreꢀꢀ written in “Reg 00h”[4:0]. If “Reg 00h”[4:0] iꢀ not changed then
the ꢀame data will alwayꢀ be preꢀent on LD_sDO when an Open Mode cycle iꢀ in progreꢀꢀ. If it iꢀ deꢀired to READ from
a ꢀpecific addreꢀꢀ, it iꢀ neceꢀꢀary in the firꢀt sPI cycle to write the deꢀired addreꢀꢀ to “Reg 00h”[4:0], then in the next
sPI cycle the deꢀired data will be available on LD_sDO.
An example of the Open Mode two cycle procedure to read from any random addreꢀꢀ iꢀ aꢀ followꢀ:
a. The Maꢀter (hoꢀt), on the firꢀt 24 falling edgeꢀ of sCLK placeꢀ 24 bit data, d23:d0, MsB firꢀt, on sDI
aꢀ ꢀhown in Figure 39. d23:d5 ꢀhould be ꢀet to zero. d4:d0 = addreꢀꢀ of the regiꢀter to be READ on
the next cycle.
b. the ꢀlave (PLL) ꢀhiftꢀ in data on sDI on the firꢀt 24 riꢀing edgeꢀ of sCLK
c. Maꢀter placeꢀ 5 bit regiꢀter addreꢀꢀ , r4:r0, ( the addreꢀꢀ the READ ADDREss regiꢀter), MsB firꢀt,
on the next 5 falling edgeꢀ of sCLK (23-29). r4:r0=00000.
d. slave ꢀhiftꢀ the regiꢀter bitꢀ on the next 5 riꢀing edgeꢀ of sCLK (23-29).
e. Maꢀter placeꢀ 3 bit chip addreꢀꢀ, a2:a0, MsB firꢀt, on the next 3 falling edgeꢀ of sCLK (30-32).Chip
addreꢀꢀ iꢀ alwayꢀ 000 for RF PLL-VCOꢀ.
f. slave ꢀhiftꢀ the chip addreꢀꢀ bitꢀ on the next 3 riꢀing edgeꢀ of sCLK (30-32).
g. Maꢀter aꢀꢀertꢀ sEN after the 32nd riꢀing edge of sCLK.
h. slave regiꢀterꢀ the sDI data on the riꢀing edge of sEN.
i. Maꢀter clearꢀ sEN to complete the addreꢀꢀ tranꢀfer of the two part READ cycle.
j. If we do not wiꢀh to write data to the chip at the ꢀame time aꢀ we do the ꢀecond cycle , then it iꢀ
recommended to ꢀimply rewrite the ꢀame contentꢀ on sDI to Regiꢀter zero on the READ back part
of the cycle.
k. Maꢀter placeꢀ the ꢀame sDI data aꢀ the previouꢀ cycle on the next 32 falling edgeꢀ of sCLK.
l. slave (PLL) ꢀhiftꢀ the sDI data on the next 32 riꢀing edgeꢀ of sCLK.
m. slave placeꢀ the deꢀired data (i.e. data from addreꢀꢀ in “Reg 00h”[4:0 ]) on LD_sDO on the next 32
riꢀing edgeꢀ of sCLK. Lock Detect iꢀ diꢀabled.
n. Maꢀter aꢀꢀertꢀ sEN after the 32nd riꢀing edge of sCLK to complete the cycle and revert back to
Lock Detect on LD_sDO.
Note that if the chip addreꢀꢀ bitꢀ are unrecognized (a2:a0), the ꢀlave will tri-ꢀtate the LD_sDO output to prevent a poꢀ-
ꢀible contention iꢀꢀue.
tꢂble 12. SPi opeꢅ Mꢄde - reꢂd tꢀmꢀꢅg chꢂꢆꢂꢁꢃeꢆꢀsꢃꢀꢁs
Parameter
Conditionꢀ
Min.
Typ.
Max.
Unitꢀ
t
sDI ꢀetup time
sDI hold time
3
3
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
1
t2
t3
t4
t5
sEN low duration
sEN high duration
10
10
sCLK Riꢀing Edge to sDO time
8.2+0.2nꢀ/pF
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 34
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
FIRST CYCLE
t1
t2
29
2
19
20
21
24
25
26
30
31
32
sCLK
sDI
x
d5
d4
d0
a2
a0
r4
a1
r0
x
READ Addreꢀꢀ
x
Regiꢀter Addreꢀꢀ =00000
Chip Addreꢀꢀ =000
t5
x
x
x
x
x
x
x
x
x
x
LD
LD_sDO
LD
sEN
t4
t6
SECOND CYCLE
2
19
20
21
24
25
26
30
31
32
sCLK
sDI
x
d23
d5
d4
d0
a2
x
a0
r4
a1
r0
d31
d30
d10
d9
d8
d7
d6
d3
d2
d1
d0
LD**
LD
LD_sDO
sEN
t3
**Note: Read-back on LD_sDO can function without sEN, however sEN
riꢀing edge iꢀ required to return the LD_sDO to the LD ꢀtate
Figure 39. Open Mode - Serial Port Timing Diagram - READ Operation 2-Cycles
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 35
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
aUX SEriaL Port
The PLL alꢀo featureꢀ a general purpoꢀe 16 bit Aux serial Port (AuxsPI). The auxiliary ꢀerial port may be uꢀed to con-
trol other chipꢀ if available, via the Open mode protocol.
The AuxsPI outputꢀ the contentꢀ of “Reg 05h” upon receipt of a frequency change command. The AuxsPIdata iꢀ out-
put at the AuxsPI clock rate which iꢀ fpd (“Reg 05h”[6]). A ꢀingle AuxsPI tranꢀfer requireꢀ 16 AuxsPI cycleꢀ pluꢀ 4
overhead cycleꢀ.
rEGiStEr MaP
tꢂble 13. reg 00h iD regꢀsꢃeꢆ (reꢂd oꢅly)
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
[23:0]
RO
chip_ID
24
A7975h
PLL subꢀyꢀtem ID, 94075
tꢂble 13. reg 00h opeꢅ Mꢄde ꢂꢅd HMc Mꢄde reseꢃ Sꢃꢆꢄbe regꢀsꢃeꢆ (Wꢆꢀꢃe oꢅly)
(Continued)
BIT
[5]
TYPE
WO
NAME
W
1
DEFLT
-
DEsCRIPTION
strobe (WRITE ONLY) generateꢀ ꢀoft reꢀet. Reꢀetꢀ all digital and
regiꢀterꢀ to default ꢀtateꢀ
rꢀt_ꢀwrꢀt
tꢂble 13. reg 00h opeꢅ Mꢄde reꢂd addꢆess regꢀsꢃeꢆ (Wꢆꢀꢃe oꢅly) (Continued)
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
[4:0]
WO
Open Mode Read Addreꢀꢀ
5
-
specifieꢀ addreꢀꢀ to read when in Open Mode 2 cycle read
tꢂble 14. reg 01h PoWErDn regꢀsꢃeꢆ
BIT
TYPE
NAME
W
DEFLT
0
DEsCRIPTION
1 = chip enable via CEN pin, Reg01[0]=1 and CEN pin low putꢀ
PLL in Power Down Mode, ꢀee Power Down Mode deꢀcription
0 = PLL subꢀyꢀtem chip enable via sPI (rꢀt_chipen_from_ꢀpi)
Reg01[1]
[0]
R/W
chipen_pin_ꢀelect
1
Controlꢀ PLL subꢀyꢀtem Chip Enable (Power Down) if rꢀt_chipen_
pin_ꢀelect
[1]
R/W
chipen_from_ꢀpi
1
1
Reg01[0]=0 and Reg01[1]=1 = chip enabled, CEN don’t care
Reg01[0]=0 and Reg01[1]=0 = chip diꢀabled, CEN don’t care
ꢀee Power Down Mode deꢀcription and cꢀp_enable
[2]
[3]
[4]
[5]
[6]
[7]
[8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Keep_Biaꢀ On
Keep_PFD_on
Keep_CP_On
1
1
1
1
1
1
1
0
0
0
0
0
0
0
keepꢀ internal biaꢀ generatorꢀ on, ignoreꢀ Chip enable control
keepꢀ PFD circuit on, ignoreꢀ Chip enable control
keepꢀ Charge Pump on, ignoreꢀ Chip enable control
keepꢀ Reference buffer block on, ignoreꢀ Chip enable control
keepꢀ VCO divider buffer on, ignoreꢀ Chip enable control
keepꢀ GPO output Driver ON, ignoreꢀ Chip enable control
reꢀerved
Keep_Ref_buf ON
Keep_VCO_on
Keep_GPO_driver ON
reꢀerved
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 36
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
tꢂble 15. reg 02h rEfDiV regꢀsꢃeꢆ
BIT
TYPE
NAME
W
DEFLT
1
DEsCRIPTION
Reference Divider ’R’ Value (EQ 8)
Divider uꢀe alꢀo requireꢀ refBufEn Reg08[3]=1
[13:0]
R/W
rdiv
14
min 0d
max 16383d
tꢂble 16. reg 03h fꢆequeꢅꢁy regꢀsꢃeꢆ - iꢅꢃegeꢆ Pꢂꢆꢃ
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
VCO Divider Integer part, uꢀed in all modeꢀ, ꢀee (EQ 10)
Fractional Mode
min 20d
max 2 -4 = 7FFFCh = 524,284d
200d
C8h
19
[18:0]
R/W
intg
19
Integer Mode
min 16d
19
max 2 -1 = 7FFFFh = 524,287d
tꢂble 17. reg 04h fꢆequeꢅꢁy regꢀsꢃeꢆ - fꢆꢂꢁꢃꢀꢄꢅꢂl Pꢂꢆꢃ
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
VCO Divider Fractional part (24 bit unꢀigned) ꢀee Fractional Fre-
quency Tuning
Fractional Diviꢀion Value = Reg4[23:0]/2^24
Uꢀed in Fractional Mode only
[23:0]
R/W
frac
24
0
min 0d
max 2^24-1 = FFFFFFh = 16,777,215d
tꢂble 18. reg 05h aux SPi regꢀsꢃeꢆ
BIT
TYPE
R/W
NAME
W
DEFLT
0
DEsCRIPTION
[15:0]
Aux Data
16
Data to be output on AsD pin
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 37
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
tꢂble 19. reg 06h SD cfG regꢀsꢃeꢆ
BIT
TYPE
NAME
W
2
DEFLT
DEsCRIPTION
selectꢀ the seed in Fractional Mode
00: 0 ꢀeed
01: lꢀb ꢀeed
02: B29D08h ꢀeed
03: 50F1CDh ꢀeed
[1:0]
R/W
ꢀeed ꢀelect
2
Note; Writeꢀ to thiꢀ regiꢀter are ꢀtored in the PLL and are only
loaded into the modulator when a frequency change iꢀ executed
and if autoꢀeed Reg06h[13] =1
select the Delta sigma Modulator Type
0: Reꢀerved
1: Reꢀerved
[3:2]
[6:4]
[7]
R/W
R/W
R/W
Modulator order
Reꢀerved
2
3
1
2
7
0
2: Mode B Offerꢀ better out of band ꢀpectral performance. Mode B
Required for Exact Frequency Mode.
3: Mode A Offerꢀ better in band ꢀpectral performance
0: Uꢀe Modulator, Required for Fractional Mode,
1: Bypaꢀꢀ Modulator, Required for Integer Mode
Note: In bypaꢀꢀ fractional modulator output iꢀ ignored, but frac-
tional modulator continueꢀ to be clocked if frac_rꢀtb =1, Can be
uꢀed to teꢀt the iꢀolation of the digital fractional modulator from the
VCO output in integer mode
frac_bypaꢀꢀ
1: loadꢀ the modulator ꢀeed (ꢀtart phaꢀe) whenever the frac regiꢀ-
ter iꢀ written
0: when frac regiꢀter write changeꢀ frequency, modulator ꢀtartꢀ
with previouꢀ contentꢀ
[8]
R/W
autoꢀeed
1
1
ꢀelectꢀ the modulator core clock ꢀource- for Teꢀt Only
1: VCO divider clock
0: Ref divider clock
[9]
[10]
[11]
R/W
R/W
R/W
clkrq_refdiv_ꢀel
Modulator Core Clk select
frac_rꢀtb
1
1
1
1
0
1
Ignored if bitꢀ [10] or [21] are ꢀet
0 - Modulator auxclk, 1- Modulator VCO Clock delay
0: diꢀable Modulator, uꢀe for Integer Mode or Integer Mode with
CsP
1: Enable Modulator Core, required for Fractional Mode, or Integer
iꢀolation teꢀting
[12]
[13]
R/W
R/W
R/W
R/W
R/W
Reꢀerved
Reꢀerved
Reꢀerved
Reꢀerved
BIsT Enable
1
1
2
2
1
0
0
0
0
0
[15:14]
[17:16]
[18]
Reꢀerved
Program to 3 decimal “11” binary
Enable Built in self Teꢀt
0:1023
1:2047
2:3071
3:4095
[20:19]
R/W
RDIV BIsT Cycleꢀ
2
0
[21]
[22]
R/W
R/W
Reꢀerved
Reꢀerved
1
1
0
0
Reꢀerved
Reꢀerved
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 38
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
tꢂble 20. reg 07h Lꢄꢁk Deꢃeꢁꢃ regꢀsꢃeꢆ
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
Lock Detect window
ꢀetꢀ the number of conꢀecutive countꢀ of divided VCO that muꢀt
land inꢀide the Lock Detect Window to declare LOCK
0: 5
1: 32
[2:0]
R/W
lkd_wincnt_max
3
5
2: 96
3: 256
4: 512
5: 2048
6: 8192
7: 65535
[3]
R/W
R/W
Enable Internal Lock Detect
Reꢀerved
1
2
1
0
Enable Internal Lock Detect
Reꢀerved
[5:4]
Lock Detection Window Timer selection
1: Digital programmable timer
[6]
R/W
Lock Detect Window type
1
0
0: Analog one ꢀhot, nominal +/-10nꢀec window
Lock Detection - Digital Window Duration
0: 1/2 cycle
1: 1 cycle
2: 2 cycleꢀ
3: 4 cycleꢀ
4: 8 cycleꢀ
5: 16 cycleꢀ
6: 32 cycleꢀ
7: 64 cycleꢀ
[9:7]
R/W
LD Digital Window duration
3
0
Lock Detect Digital Timer Frequency Control
“00” faꢀteꢀt “11” ꢀloweꢀt
[11:10]
[12]
R/W
R/W
R/W
LD Digital Timer Freq Control
LD Timer Teꢀt Mode
2
1
1
0
0
0
1: Force Timer ON Continuouꢀly - For Teꢀt Only
0: Normal Timer operation - one ꢀhot
1: Attemptꢀ to relock if Lock Detect failꢀ for any reaꢀon
Only trieꢀ once.
[13]
Auto Relock - One Try
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 39
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
tꢂble 21. reg 08h aꢅꢂlꢄg En regꢀsꢃeꢆ
BIT
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NAME
W
DEFLT
DEsCRIPTION
0
biaꢀ_en
1
1
1
1
1
1
1
1
1
0
1
Enableꢀ main chip biaꢀ reference
1
cp_en
1
Charge pump enable
PD enable
2
pd_en
1
3
refbuf_en
Reference path buffer enable
VCO path RF buffer enable
0 - Pin LD_sDO diꢀabled
ꢀpare
4
vcobuf_en
1
1
1
1
1
1
5
GPO/LDO/sDO_pad_en
ꢀpare
6
7
VCO_Div_Clk_to_dig_en
Reꢀerved
VCO Divider Clock to Digital Enable
Reꢀerved
8
9
Preꢀcaler Clock enable
Preꢀcaler clock enable
VCO Buffer and Preꢀcaler Biaꢀ
Enable
[10]
[11]
R/W
R/W
1
1
1
1
VCO Buffer and Preꢀcaler Biaꢀ Enable
Charge Pump Internal Opamp enable
Charge Pump Internal Opamp
enable
[14:12]
[17:15]
[18]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RF Buffer En/Biaꢀ
Div Reꢀync En/Biaꢀ
Reꢀerved
3
3
1
1
1
1
1
1
3
3
0
0
0
0
1
1
0: Diꢀabled, 1: Low Biaꢀ,...7: High Biaꢀ
0: Diꢀabled, 1: Low Biaꢀ,...7: High Biaꢀ
Reꢀerved Program 0
[19]
8GHz Divide by 2 En
Reꢀerved
8GHz Divide by 2 Enable
Reꢀerved Program 0
[20]
[21]
Hi Frequency Reference
Reꢀerved
Program 1 for XTAL > 200 MHz
Reꢀerved
[22]
[23]
Reꢀerved
Reꢀerved
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 40
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
tꢂble 22. reg 09h chꢂꢆge Pump regꢀsꢃeꢆ
BIT
TYPE
NAME
W
DEFLT
10d
DEsCRIPTION
Charge Pump DN Gain Control 20uA/ꢀtep
Affectꢀ fractional phaꢀe noiꢀe and lock detect ꢀettingꢀ
0d = 0uA
1d = 20uA
2d = 40uA
...
[6:0]
R/W
CP DN Gain
7
127d = 2.54mA
Charge Pump UP Gain Control 20uA/ꢀtep
Affectꢀ fractional phaꢀe noiꢀe and lock detect ꢀettingꢀ
0d = 0uA
1d = 20uA
2d = 40uA
...
[13:7]
R/W
R/W
CP UP Gain
7
7
10d
127d = 2.54mA
Charge Pump Offꢀet Control 5uA/ꢀtep
Affectꢀ fractional phaꢀe noiꢀe and ꢀpurꢀand lock detect ꢀettingꢀ
0d = 0uA
1d = 5uA
2d = 110uA
...
[20:14]
Offꢀet Current
0
127d = 635uA
[21]
[22]
R/W
R/W
Offꢀet Current UP
Offꢀet Current DN
1
1
0
1
1 - setꢀ Direction of Reg[20:14] Up, 0- UP Offꢀet Off
1 - setꢀ Direction of Reg[20:14] Down, 0- DN Offꢀet Off
Hi Kcp Charge Pump - Very Low Noiꢀe, Narrow Compliance range,
requireꢀ Opamp
[23]
R/W
HiK charge pump Mode
1
0
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 41
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
tꢂble 23. reg 0ah auxSPi tꢆꢀggeꢆ regꢀsꢃeꢆ
BIT
[11:0]
[12]
TYPE
R/W
R/W
R/W
R/W
NAME
W
12
1
DEFLT
DEsCRIPTION
Reꢀerved
0
0
0
0
Reꢀerved
No AuxsPI Trigger
reꢀerved
No AuxsPI trigger on Reg5 Write
Reꢀerved
[15:13]
[16]
3
Force RDivider Bypaꢀꢀ
1
Force the R Divider Bypaꢀꢀ, ignore Reg03
tꢂble 24. reg 0Bh PD regꢀsꢃeꢆ
BIT
[2:0]
[3]
TYPE
R/W
R/W
NAME
W
3
DEFLT
DEsCRIPTION
setꢀ PD reꢀet path delay
pd_del_ꢀel
1
0
short PD Inputꢀ
1
shortꢀ the inputꢀ to the Phaꢀe Detector - Teꢀt Only
Invertꢀ the PD polarity
0 - Uꢀe with a poꢀitive tuning ꢀlope VCO and paꢀꢀive loop filter
(default).
[4]
R/W
pd_Invert
1
0
1 - Uꢀe with a negative ꢀlope VCO or with an inverting active loop
filter with a poꢀitive ꢀlope VCO.
[5]
[6]
R/W
R/W
pd_up_en
pd_dn_en
1
1
1
1
Enableꢀ the PD UP output, ꢀee alꢀo Reg0B[9]
enableꢀ the PD DN output, ꢀee alꢀo Reg0B[9]
Cycle slip Prevention Mode
0: CsP Diꢀabled
[8:7]
R/W
CsP Mode
2
0
1: CP Gain increaꢀed if Phaꢀe Error > 2 nꢀec
2: CP Gain increaꢀed if Phaꢀe Error > 4 nꢀec
3: CP Gain increaꢀed if Phaꢀe Error > 6 nꢀec
[9]
[10]
[11]
R/W
R/W
R/W
Force CP UP
Force CP DN
1
1
1
0
0
0
Forceꢀ CP UP output on - Uꢀe for Teꢀt only
Forceꢀ CP DN output on - Uꢀe for Teꢀt only
Force CP MId Rail - Uꢀe for Teꢀt only
Force CP MId Rail
Preꢀcaler Biaꢀ
0: Nominal
[14:12]
[16:15]
[18:17]
R/W
R/W
R/W
Ps Biaꢀ
3
2
2
0
3
3
1: +20% RF Buffer
2: +25% Rꢀync
3: +50%
CP Internal OpAmp Biaꢀ
MCounter Clock Gating
CP Internal OpAmp Biaꢀ
MCounter Clock Gating
0: MCounter Off for N<32
1: N<128
2: N< 1023
3: All Clockꢀ ON
[19]
R/W
R/W
R/W
Reꢀerved
Divider Pulꢀe Width
Reꢀerved
1
2
2
1
0
0
[21:20]
[23:22]
0: ꢀhorteꢀt, ... 3: Longeꢀt
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 42
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
tꢂble 25. reg 0ch Exꢂꢁꢃ fꢆequeꢅꢁy regꢀsꢃeꢆ
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
Compariꢀon Frequency divided by the channel ꢀpacing. Muꢀt be an
integer. Frequencieꢀ at multipleꢀ of the channel ꢀpacing will have
zero frequency error. Only workꢀ in modulator Mode B. Muꢀt be 0
[13:0]
R/W
Number of Channelꢀ per Fpd
14
0
otherwiꢀe
0: Diꢀabled
1: Diꢀabled
2 to16383d (3FFFh) allowed
tꢂble 26. reg 0fh GPo regꢀsꢃeꢆ
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
signal ꢀelected here iꢀ output to sDO pin when enabled
0: Data from Reg0F[5]
1: Lock Detect Output
2. Lock Detect Trigger
3: Lock Detect Window Output
4: Ring Oꢀc Teꢀt
5. Pullup Hard from CsP
6. PullDN hard from CsP
7. Reꢀerved
8: Reference Buffer Output
9: Ref Divider Output
10: VCO divider Output
11. Modulator Clock from VCO divider
12. Auxiliary Clock
[4:0]
R/W
gpo_ꢀelect
5
1
13. Aux sPI Clock
14. Aux sPI Enable
15. Aux sPI Data Out
16. PD DN
17. PD UP
18. sD3 Clock Delay
19. sD3 Core Clock
20. Autostrobe Integer Write
21. Autoꢀtrobe Frac Write
22. Autoꢀtrobe Aux sPI
23. sPI Latch Enable
24. VCO Divider sync Reꢀet
25. seed Load strobe
26.-29 Not Uꢀed
30. sPI Output Buffer En
31. soft RsTB
[5]
[6]
R/W
R/W
GPO Teꢀt Data
1
1
0
0
1 - GPO Teꢀt Data when GPO_select = 0
Prevent Automux sDO
1- inhibitꢀ Automux of the sPI sDO line with Lock Detect
1- Preventꢀ sPI from diꢀabling sDO. should be 1 if uꢀing HMC sPI
mode.
[7]
R/W
Prevent Driver Diꢀable
1
0
[8]
[9]
R/W
R/W
Diꢀable PFET
Diꢀable NFET
1
1
0
0
Diꢀable PFET
Diꢀable NFET
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 43
HMC704LP4E
v02.0411
8 GHz fractionaL-n PLL
tꢂble 27. reg 10h reseꢆve regꢀsꢃeꢆ (reꢂd oꢅly)
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
DESCRIPTION
DEsCRIPTION
[8:0]
RO
Reꢀerved
9
0
Reꢀerved
tꢂble 28. reg 11h reseꢆve regꢀsꢃeꢆ (reꢂd oꢅly)
BIT
TYPE
NAME
W
DEFLT
[18:0]
RO
Reserved
19
0
Reserved
tꢂble 29. reg 12h GPo2 regꢀsꢃeꢆ (reꢂd oꢅly)
BIT
TYPE
NAME
W
DEFLT
[0]
RO
GPO
1
0
0
GPO
[1]
RO
Lock Detect
1
Lock Detect
tꢂble 30. reg 13h BiSt regꢀsꢃeꢆ
BIT
[15:0]
[16]
TYPE
NAME
W
16
1
DEFLT
DEsCRIPTION
RO
BIsT signature
BIsT Buꢀy
0
0
Digital Built-In self Teꢀt signature
BIsT Buꢀy
RO
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5 - 44
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