HMCAD1512 [HITTITE]
Coarse and Fine Gain Control; 粗，细增益控制
| 型号： | HMCAD1512 |
| 厂家： | 
HITTITE MICROWAVE CORPORATION |
| 描述： | Coarse and Fine Gain Control |
| 文件： | 总30页 (文件大小：675K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Features
• 8-bit High Speed Single/ Dual ADC
Single Channel Mode: FSmax = 900 MSPS
Dual Channel Mode: FSmax = 450 MSPS
• Internal Offset Correction
• 1.8V Supply Voltage
• 1.7 - 3.6V CMOS Logic on Control Interface Pins
• Serial LVDS/RSDS Output
• Integrated Cross Point Switches (Mux Array)
• 7x7 mm QFN 48 (LP7D) Package
• 1X to 50X Digital Gain
No Missing Codes up to 32X
Typical Applications
• 1X Gain: 48.8 dB SNR. 10X Gain: 48 dB SNR
• Internal Low Jitter Programmable Clock Divider
• Point-to-point Microwave Links
• Digital Oscilloscopes
• Ultra Low Power Dissipation
650 mW including I/O at 900 MSPS
• Satellite Receivers
• 0.5 µs Start-up Time from Sleep,
15 µs from Power Down
Related Products
• HMCAD1512 is pin compatible with HMCAD1520
and HMCAD1511
• Internal Reference Circuitry with no
External Components Required
• HMCAD1511 is similar functionality as
the HMCAD1512 with quad channel option
and higher speed.
• Coarse and Fine Gain Control
• Digital Fine Gain Adjustment for each ADC
Functional Diagram
Figure 1. Functional Block Diagram
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
1
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
General Description
The HMCAD1512 is a versatile high performance low power analog-to-digital converter (ADC), utilizing time-interleaving
to increase sampling rate. Integrated Cross Point Switches activate the input selected by the user.
The device contains 2 ADCs that can be interleaved by the user to act as a single channel or two channels. In single
channel mode, either of the two inputs can be selected as a valid input to the single ADC channel. In dual channel
mode, either of the two inputs can be selected for each ADC channel. (The HMCAD1512 does not support the quad-
channel mode. The HMCAD1511 should be used for this purpose).
An internal, low jitter and programmable clock divider makes it possible to use a single clock source for all operational
modes.
The HMCAD1512 is based on a proprietary structure, and employs internal reference circuitry, a serial control
interface and serial LVDS/RSDS output data. Data and frame synchronization clocks are supplied for data capture
at the receiver. Internal 1 to 50X digital coarse gain with ENOB > 7.5 up to 16X gain, allows digital implementation of
oscilloscope gain settings. Internal digital fine gain can be set separately for each ADC to calibrate for gain errors.
Various modes and configuration settings can be applied to the ADC through the serial control interface (SPI). Each
channel can be powered down independently and data format can be selected through this interface. A full chip idle
mode can be set by a single external pin. Register settings determine the exact function of this pin.
HMCAD1512 is designed to easily interface with Field Programmable Gate Arrays (FPGAs) from several vendors.
Electrical Specifications
DC Specifications
AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, FS = 250 MSPS, Dual Channel Mode, 50% clock duty cycle, -1 dBFS 70 MHz input
signal, 1x/0 dB digital gain (fine and coarse), unless otherwise noted
Parameter
DC accuracy
Description
Min
Typ
Max
Unit
No missing codes
Guaranteed
Offset
Gabs
Offset error after internal digital offset correction
Gain error
0.05
0.5
LSB
6
%FS
Gain matching between channels. 3 sigma value at worst
case conditions
Grel
%FS
DNL
Differential non linearity
Integral non linearity
0.2
0.5
LSB
LSB
INL
VCM,out
Common mode voltage output
VAVDD/2
Analog Input
VCM,in
Analog input common mode voltage
Differential input voltage full scale range
VCM -0.1
VCM +0.2
V
Vpp
pF
FSR
2
7
Cin,D
Differential input capacitance, Dual channel mode
Differential input capacitance, Single channel mode
Cin,S
11
pF
Power Supply
VAVDD
Analog Supply Voltage
1.7
1.7
1.7
1.8
1.8
1.8
2
2
V
V
V
VDVDD
Digital and output driver supply voltage
Digital CMOS Input Supply Voltage
VOVDD
3.6
Temperature
TA
Operating free-air temperature
-40
85
°C
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
2
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
AC Specifications
AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50% clock duty cycle, -1 dBFS 71 MHz input signal, Gain = 1X, RSDS output data levels unless
otherwise noted
Parameter
Description
Min
Typ
Max
Unit
Performance
SNR
Signal to Noise Ratio, excluding interleaving spurs
Single Ch Mode, FS = 900 MSPS
47.5
48
48.8
48.5
48
dBFS
dBFS
dBFS
dBFS
Single Ch Mode, FS = 900 MSPS, FIN = 170 MHz
Single Ch Mode, FS = 900 MSPS, Gain = 10X
Dual Ch Mode, FS = 450 MSPS
49
Signal to Noise and Distortion Ratio, including interleaving
spurs
SINADincl
SINADexcl
Single Ch Mode, FS = 900 MSPS
Dual Ch Mode, FS = 450 MSPS
44.8
43.5
dBFS
dBFS
Signal to Noise and Distortion Ratio, excluding interleaving
spurs
Single Ch Mode, FS = 900 MSPS
47
48.3
46.5
47.3
48.3
dBFS
dBFS
dBFS
dBFS
Single Ch Mode, FS = 900 MSPS, FIN = 170 MHz
Single Ch Mode, FS = 900 MSPS, Gain = 10X
Dual Ch Mode, FS = 450 MSPS
47.5
SFDRincl
SFDRexcl
Spurious Free Dynamic Range, including interleaving spurs
Single Ch Mode, FS = 900 MSPS
49
44
dBc
dBc
Dual Ch Mode, FS = 450 MSPS
Spurious Free Dynamic Range, excluding interleaving spurs
Single Ch Mode, FS = 900 MSPS
55
64
63
62
63
dBc
dBc
dBc
dBc
Single Ch Mode, FS = 900 MSPS, FIN = 170 MHz
Single Ch Mode, FS = 900 MSPS, Gain = 10X
Dual Ch Mode, FS = 450 MSPS
55
60
HD2/3
Worst of HD2/HD3
Single Ch Mode, FS = 900 MSPS
65
65
63
63
dBc
dBc
dBc
dBc
Single Ch Mode, FS = 900 MSPS, FIN = 170 MHz
Single Ch Mode, FS = 900 MSPS, Gain = 10X
Dual Ch Mode, FS = 450 MSPS
57
ENOBexcl
Effective number of Bits, excluding interleaving spurs
Single Ch Mode, FS = 900 MSPS
7.7
7.4
7.5
7.7
bits
bits
bits
bits
Single Ch Mode, FS = 900 MSPS, FIN = 170 MHz
Single Ch Mode, FS = 900 MSPS, Gain = 10X
Dual Ch Mode, FS = 450 MSPS
CrossTalk Dual Ch Mode. Signal applied to 1 channel (FIN0).
Xtlk,2
Measurement taken on one channel with full scale at FIN1
.
-90
dBc
FIN1 = 71 MHz, FIN0 = 70 MHz
Single Ch: FS = 900 MS/s, Dual Ch: FS = 450 MS/s
Analog Supply Current
Power Supply
IAVDD
250
112
450
200
650
15
mA
mA
IDVDD
Digital and output driver Supply Current
Analog Power
PAVDD
mW
mW
mW
µW
PDVDD
PTOT
Digital Power
Total Power Dissipation
PPD
Power Down Mode dissipation
Deep sleep Mode power dissipation
PSLP
72
mW
Power dissipation with all channels in sleep channel mode
(Light sleep)
PSLPCH
153
248
mW
mW
Power dissipation savings per channel off
(Duel Channel mode)
PSLPCH_SAV
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
3
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
AC Specifications
AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50% clock duty cycle, -1 dBFS 71 MHz input signal, Gain = 1X, RSDS output data levels unless
otherwise noted
Parameter
Description
Min
Typ
Max
Unit
Analog Input
FPBW
Full Power Bandwidth
650
MHz
Clock Inputs
Max. Conversion Rate in Modes: Single Ch
900 /450
FSmax
MSPS
MSPS
Dual Ch
Min. Conversion Rate in Modes: Single Ch
Dual Ch
120 /
60 /
Fsmin
Digital and Switching Specifications
AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, RSDS output data levels, unless otherwise noted
Parameter
Clock Inputs
DC
Description
Min
Typ
Max
Unit
% high
mVpp
Duty Cycle
45
55
Compliance
VCK,sine
LVDS supported up to 700 MHz
LVPECL, Sine wave, CMOS, LVDS
Differential input voltage swing, sine wave clock input
Voltage input range CMOS (CLKN connected to ground)
1500
VCK,CMOS
VOVDD
Input common mode voltage. Keep voltages within ground and
voltage of OVDD
VCM,CK
0.3
VOVDD -0.3
V
CCK
Differential Input capacitance
3
pF
Logic inputs (CMOS)
VHI
High Level Input Voltage. VOVDD ≥ 3.0V
High Level Input Voltage. VOVDD = 1.7V – 3.0V
Low Level Input Voltage. VOVDD ≥ 3.0V
Low Level Input Voltage. VOVDD = 1.7V – 3.0V
High Level Input leakage Current
Low Level Input leakage Current
2
V
V
VHI
0.8 ·VOVDD
VLI
0
0
0.8
0.2 ·VOVDD
+/-10
V
VLI
V
IHI
µA
µA
pF
ILI
+/-10
CI
Input Capacitance
3
Data Outputs
Compliance
VOUT
LVDS / RSDS
Differential output voltage, LVDS
Differential output voltage, RSDS
Output common mode voltage
Default/optional
350
150
1.2
mV
mV
V
VOUT
VCM
Output coding
Offset Binary/ 2’s complement
Timing Characteristics
tA
Aperture delay
1.5
160
2.5
ns
tj
Aperture jitter, One bit set to ‘1’ in jitter_ctrl<7:0>
Timing skew between ADC channels
fsrms
psrms
Tskew
Start up time from Power Down Mode and Deep Sleep Mode to
Active Mode in µs. See section “Clock Frequency” for details.
TSU
15
µs
TSLPCH
TOVR
TLATHSMD
TLATHSMS
Start up time from Sleep Channel Mode to Active Mode
Out of range recovery time
µs
1
clock cycles
clock cycles
clock cycles
Pipeline delay, Dual Channel Mode
Pipeline delay, Single Channel Mode
64
128
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
4
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Digital and Switching Specifications
AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, RSDS output data levels, unless otherwise noted
Parameter
Description
Min
Typ
Max
Unit
LVDS Output Timing Characteristics
tdata
LCLK to data delay time (excluding programmable phase shift)
Clock propagation delay.
50
ps
TPROP
6*TLVDS +2.2
45
7*TLVDS +3.5
7*TLVDS +5.0
ns
% LCLK cycle
% LCLK cycle
ns
LVDS bit-clock duty-cycle
55
Frame clock cycle-to-cycle jitter
2.5
TEDGE
Data rise- and fall time 20% to 80%
Clock rise- and fall time 20% to 80%
0.7
0.7
TCLKEDGE
ns
Table 1: Maximum Voltage Ratings
Table 2: Maximum Temperature Ratings
Pin
Reference pin
Rating
Operating Temperature
-40 to +85 °C
-60 to +150 °C
110 °C
AVDD
AVSS
-0.3V to +2.3V
-0.3V to +2.3V
-0.3V to +3.9V
-0.3V to +0.3V
Storage Temperature
DVDD
DVSS
Maximum Junction Temperature
Thermal Resistance (Rth)
Soldering Profile Qualification
ESD Sensivity HBM
OVDD
AVSS
29 °C/W
AVSS / DVSS
DVSS / AVSS
J-STD-020
Class 1C
Analog inputs
and outputs
AVSS
-0.3V to +2.3V
ESD Sensivity CDM
Class III
CLKx
AVSS
DVSS
DVSS
-0.3V to +3.9V
-0.3V to +2.3V
-0.3V to +3.9V
LVDS outputs
Digital inputs
Applying voltages to the pins beyond those specified in
Table 1 could cause permanent damage to the circuit.
ELECTROSTATIC SENSITIVE DEVICE
OBSERVE HANDLING PRECAUTIONS
Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in
the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
5
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Pin Configuration and Description
Figure 2: Package diagram
Table 3: Pin Descriptions
Pin Name
Description
Analog power supply, 1.8V
Chip select enable. Active low
Serial data input
Pin Number
# Of Pins
AVDD
1, 36
2
1
1
1
1
CSN
2
3
4
5
SDATA
SCLK
Serial clock input
RESETN
Reset SPI interface. Active low
Power-down input. Activate after applying power in order to initialize the ADC correctly.
Alternatively use the SPI power down feature
PD
6
1
DVDD
DVSS
DP1A
DN1A
DP1B
DN1B
DP2A
DN2A
DP2B
DN2B
LCLKP
LCLKN
Digital and I/O power supply, 1.8V
Digital ground
7, 30
8, 29
9
2
2
1
1
1
1
1
1
1
1
1
1
LVDS channel 1A, positive output
LVDS channel 1A, negative output
LVDS channel 1B, positive output
LVDS channel 1B, negative output
LVDS channel 2A, positive output
LVDS channel 2A, negative output
LVDS channel 2B, positive output
LVDS channel 2B, negative output
LVDS bit clock, positive output
LVDS bit clock, negative output
10
11
12
13
14
15
16
17
18
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
6
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Table 3: Pin Descriptions
Pin Name
FCLKP
FCLKN
DP3A
Description
Pin Number
# Of Pins
LVDS frame clock (1X), positive output
LVDS frame clock (1X), negative output
LVDS channel 3A, positive output
LVDS channel 3A, negative output
LVDS channel 3B, positive output
LVDS channel 3B, negative output
LVDS channel 4A, positive output
LVDS channel 4A, negative output
LVDS channel 4B, positive output
LVDS channel 4B, negative output
Analog ground domain 2
19
20
21
22
23
24
25
26
27
28
31
32
33
34
35
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DN3A
DP3B
DN3B
DP4A
DN4A
DP4B
DN4B
AVSS2
AVDD2
OVDD
CLKN
CLKP
Analog power supply domain 2, 1.8V
Digital CMOS Inputs supply voltage
Negative differential input clock.
Positive differential input clock
39, 40, 41, 42,
43, 44, 45
AVSS
Analog ground
7
IN2
IP2
Negative differential input signal, channel 2
Positive differential input signal, channel 2
Negative differential input signal, channel 1
Positive differential input signal, channel 1
Common mode output pin, 0.5*AVDD
37
38
46
47
48
1
1
1
1
1
IN1
IP1
VCM
Start up Initialization
As part of the HMCAD1512 power-on sequence both a reset and a power down cycle have to be applied to ensure
correct start-up initialization. Make sure that the supply voltages are properly settled before the start up initialization
is being performed. Reset can be done in one of two ways:
1. By applying a low-going pulse (minimum 20 ns) on the RESETN pin (asynchronous).
2. By using the serial interface to set the ‘rst’ bit high. Internal registers are reset to default values when
this bit is set. The ‘rst’ bit is self-reset to zero. When using this method, do not apply any low-going
pulse on the RESETN pin.
Power down cycling can be done in one of two ways:
1. By applying a high-going pulse (minimum 20 ns) on the PD pin (asynchronous).
2. By cycling the ‘pd’ bit in register 0Fhex to high (reg value ‘0200’hex) and then low (reg value ‘0000’hex).
IMPORTANT: The Operating Mode must be selected (Dual Channel or Single Channel) in register
0x31 after power-up, reset and/or power cycling.
Serial Interface
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
7
Application Support: Phone: 978-250-3343 or apps@hittite.com
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
The HMCAD1512 configuration registers can be accessed through a serial interface formed by the input-only pins
SDATA (serial interface data), SCLK (serial interface clock) and CSN (chip select, active low). The following occurs
when CSN is set low:
•
•
•
Serial data are shifted into the chip
At every rising edge of SCLK, the value present at SDATA is latched
SDATA is loaded into the register every 24th rising edge of SCLK
Multiples of 24-bit words data can be loaded within a single active CSN pulse. If more than 24 bits are loaded into
SDATA during one active CSN pulse, only the first 24 bits are kept. The excess bits are ignored. Every 24-bit word is
divided into two parts:
•
•
The first eight bits form the register address
The remaining 16 bits form the register data
Acceptable SCLK frequencies are from 20MHz down to a few hertz. Duty-cycle does not have to be tightly controlled.
Timing Diagram
Figure 4 shows the timing of the serial port interface. Table 4 explains the timing variables used in figure 4.
t
chi
t
t
ck
t
t
s
t
hi
t
cs
ch
t
CSN
SCLK
h
lo
SDATA
A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 3: Serial Port Interface timing
Table 4: Serial Port Interface Timing Definitions
Parameter
Description
Setup time between CSN and SCLK
Hold time between CSN and SCLK
SCLK high time
Minimum value
Unit
ns
tcs
tch
thi
tlo
tck
ts
8
8
ns
20
20
50
5
ns
SCLK low time
ns
SCLK period
ns
Data setup time
ns
th
Data hold time
5
ns
Timing Diagrams
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
8
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
N+63
N+62
N+64
N+65
N+66
Analog input
Input clock
N+70
N+67
N+68
N+69
TLVDS
LCLKP
LCLKN
FCLKP
FCLKN
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-8 N-8 N-8 N-8 N-8 N-8 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N-4
Dx1A / Dx3A
Dx1B / Dx3B
Dx2A / Dx4A
Dx2B / Dx4B
N
N
N
N
N
N
N
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-7 N-7 N-7 N-7 N-7 N-7 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N+1 N+1 N+1 N+1 N+1 N+1 N+1
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-6 N-6 N-6 N-6 N-6 N-6 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N+2 N+2 N+2 N+2 N+2 N+2 N+2
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-5 N-5 N-5 N-5 N-5 N-5 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N+3 N+3 N+3 N+3 N+3 N+3 N+3
TPROP
Figure 4: Dual channel - LVDS timing 8-bit output
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
9
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
N+126
N+124
N+128
N+130
N+132
Analog input
Input clock
N+140
N+134
N+138
N+136
TLVDS
LCLKP
LCLKN
FCLKP
FCLKN
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-16 N-16 N-16 N-16 N-16 N-16 N-8 N-8 N-8 N-8 N-8 N-8 N-8 N-8
Dx1A
Dx1B
Dx2A
Dx2B
Dx3A
Dx3B
Dx4A
Dx4B
N
N
N
N
N
N
N
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-15 N-15 N-15 N-15 N-15 N-15 N-7 N-7 N-7 N-7 N-7 N-7 N-7 N-7 N+1 N+1 N+1 N+1 N+1 N+1 N+1
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-14 N-14 N-14 N-14 N-14 N-14 N-6 N-6 N-6 N-6 N-6 N-6 N-6 N-6 N+2 N+2 N+2 N+2 N+2 N+2 N+2
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-13 N-13 N-13 N-13 N-13 N-13 N-5 N-5 N-5 N-5 N-5 N-5 N-5 N-5 N+3 N+3 N+3 N+3 N+3 N+3 N+3
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-12 N-12 N-12 N-12 N-12 N-12 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N+4 N+4 N+4 N+4 N+4 N+4 N+4
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-11 N-11 N-11 N-11 N-11 N-11 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N+5 N+5 N+5 N+5 N+5 N+5 N+5
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N+6 N+6 N+6 N+6 N+6 N+6 N+6
N-10 N-10 N-10 N-10 N-10 N-10
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-9 N-9 N-9 N-9 N-9 N-9 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N+7 N+7 N+7 N+7 N+7 N+7 N+7
TPROP
Figure 5: Single channel - LVDS timing 8-bit output
TLVDS
LCLKP
LCLKN
Dxxx
TLVDS /2
tdata
Figure 6: LVDS data timing
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10
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Register Map Summary
Table 5: Register Map
Hex
Address
Name
Description
Default
Inactive
Inactive
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
rst *
Self-clearing software reset.
X
0x00
sleep2_ch
<2:1>
Channel-specific sleep mode for a Dual
Channel setup.
X
X
Channel-specific sleep mode for a
Single Channel setup.
sleep1_ch1
Inactive
X
sleep
pd
Go to sleep-mode.
Go to power-down.
Inactive
Inactive
X
0x0F
X
PD pin configured
for power-down
mode
pd_pin_cfg
<1:0>
Configures the PD pin function.
X
X
ilvds_lclk
<2:0>
LVDS current drive programmability for
LCLKP and LCLKN pins.
3.5 mA drive
3.5 mA drive
3.5 mA drive
X
X
X
ilvds_frame
<2:0>
LVDS current drive programmability for
FCLKP and FCLKN pins.
X
X
X
X
X
0x11
ilvds_dat
<2:0>
LVDS current drive programmability for
output data pins.
X
X
X
X
X
X
term_dat
<2:0>
Programmable termination for output
data buffers.
Termination
disabled
1
Channel specific swapping of the
analog input signal for a Dual Channel
setup.
invert2_ch
<2:1>
IPx is positive
input
0x24
0x25
Channel specific swapping of the
analog input signal for a Single
Channel setup.
IPx is positive
input
invert1_ch1
X
Enables a repeating full-scale ramp
pattern on the outputs.
en_ramp
Inactive
Inactive
X
0
0
0
0
Enable the mode wherein the output
toggles between two defined codes.
custom_pat
X
Bits for the single custom pattern and
for the first code of the dual custom
pattern.
bits_custom1
<7:0>
0x00
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0x26
0x27
bits_custom2
<7:0>
Bits for the second code of the dual
custom pattern.
0x00
1x gain
cgain2_ch1
<3:0>
Programmable coarse gain channel 1
in a Dual Channel setup.
X
X
X
X
X
cgain2_ch2
<3:0>
Programmable coarse gain channel 2
in a Dual Channel setup.
1x gain
X
X
X
X
X
X
X
X
0x2B
cgain1_ch1
<3:0>
Programmable coarse gain channel 1
in a Single Channel setup.
1x gain
X
X
X
X
X
X
jitter_ctrl
<7:0>
Clock jitter adjustment.
160 fsrms
4 channels
Divide by 1
X
X
X
X
X
X
0x30
0x31
channel_
num <2:0> *
Set number of channels:
1, or 2 channels.
clk_divide
<1:0>*
Define clock divider factor: 1, 2, 4
coarse_
gain_cfg
Configures the coarse gain setting
Enable use of fine gain.
x-gain enabled
Disabled
X
X
0x33
0x34
fine_gain_en
X
X
fgain_
branch1
<6:0>
Programmable fine gain for branch1.
Programmable fine gain for branch 2.
Programmable fine gain for branch 3.
Programmable fine gain for branch 4.
0dB gain
0dB gain
0dB gain
0dB gain
X
X
X
X
X
X
X
X
X
X
fgain_
branch2
<6:0>
X
X
X
X
X
X
X
X
X
X
X
X
X
X
fgain_
branch3
<6:0>
X
X
0x35
fgain_
branch4
<6:0>
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Table 5: Register Map
Hex
Address
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
fgain_
branch5
<6:0>
Programmable fine gain for branch 5.
0dB gain
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0x36
fgain_
branch6
<6:0>
Programmable fine gain for branch 6.
Programmable fine gain for branch 7.
Programmable fine gain for branch 8.
0dB gain
0dB gain
0dB gain
X
X
X
X
X
X
X
X
X
X
X
X
X
X
fgain_
branch7
<6:0>
0x37
0x3A
fgain_
branch8
<6:0>
inp_sel_adc1
<4:0>
Signal input:
IP1/IN1
Input select for adc 1.
Input select for adc 2.
Input select for adc 3.
Input select for adc 4.
X
X
X
X
X
X
X
X
0
0
inp_sel_adc2
<4:0>
Signal input:
AVSS
X
X
X
X
X
X
X
X
0
0
inp_sel_adc3
<4:0>
Signal input:
AVSS
0x3B
0x42
0x46
inp_sel_
adc4<4:0>
Signal input: IP2/
IN2
phase_ddr
<1:0>
Controls the phase of the LCLK output
relative to data.
90 degrees
X
X
Binary two’s complement format for
ADC output data.
Straight offset
binary
btc_mode
msb_first
X
X
Serialized ADC output data comes out
with MSB first.
LSB first
Nominal
X
adc_curr
<2:0>
ADC current scaling.
X
X
X
0x50
0x52
ext_vcm_bc
<1:0>
VCM buffer driving strength control.
Controls LVDS power down mode
Nominal
X
X
lvds_pd_
mode
High z-mode
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Table 5: Register Map
Hex
Address
Name
Description
Default
Inactive
Inactive
Inactive
0% change
‘000’
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
low_clk_
freq *
Low clock frequency used.
X
X
0
0
0
X
X
0
0
0
X
X
0
0
0
X
X
lvds_
advance
Advance LVDS data bits and frame
clock by one clock cycle
0
X
X
X
0
0x53
Delay LVDS data bits and frame clock
by one clock cycle
lvds_delay
fs_cntrl
<5:0>
Fine adjust ADC full scale range
Controls start-up time.
X
0x55
0x56
startup_ctrl
<2:0> *
Undefined register addresses must not be written to; incorrect behavior may be the result.
Unused register bits (blank table cells) must be set to ‘0’ when programming the registers.
All registers can be written to while the chip is in power down mode.
* These registers require a power down cycle when written to (See Start up Initialization).
Register Description
Software Reset
Hex
Address
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
rst
Self-clearing software reset.
Inactive
X
0x00
Setting the rst register bit to ‘1’, restores the default value of all the internal registers including the rst register bit
itself.
Modes of Operation and Clock Divide Factor
Hex
Address
Name
Description
Set number of channels: 1or 2 channels. 4 channels
Define clock divider factor: 1, 2, or 4 Divide by 1
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
channel_
num <1:0>
X
X
X
0x31
clk_divide
<1:0>
X
X
The HMCAD1512 has three main operating modes controlled by the register bits channel_num<2:0> as defined in
table 6. Power down mode, as described in section ‘Startup Initialization’, must be activated after or during a change
of operating mode to ensure correct operation. All active operating modes utilize interleaving to achieve high sampling
speed. Dual channel mode interleaves 2 ADCs each, while single channel mode interleaves all 4 ADCs.
Table 6: Modes of operation
channel_num <2:0> Mode of operation
Description
0
0
0
1
1
0
Single channel
Dual channel
Single channel by interleaving ADC1 to ADC4
Dual channel where channel 1 is made by
interleaving ADC1 and ADC2, channel 2 by
interleaving ADC3 and ADC4
1
0
0
Quad channel
Mode not supported on HMCAD1512.
Only one of the 3bits should be activated at the same time.
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
clk_divide<1:0> allows the user to apply an input clock frequency higher than the sampling rate. The clock divider
will divide the input clock frequency by a factor of 1, 2, 4 defined by the clk_divide<1:0> register. By setting the
clk_divide<1:0> value relative to the channel_num<2:0> value, the same input clock frequency can be used for all set-
tings on number of channels. e.g: When increasing the number of channels from 1 to 2, the maximum sampling rate
is reduced by a factor of 2. By letting clk_divide<1:0> follow the channel_num<2:0> value, and changing it from 1 to
2, the internal clock divider will provide the reduction of the sampling rate without changing the input clock frequency.
Table 7: Clock Divider Factor
clk_divide<1:0>
Clock Divider Factor
Sampling rate (FS)
Input clock frequency / 1
Input clock frequency / 2
Input clock frequency / 4
Do not use
00 (default)
1
2
01
10
11
4
n/a
Input Select
Hex
Address
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Signal input:
IP1/IN1
inp_sel_adc1 <4:0> Input select for adc 1.
inp_sel_adc2 <4:0> Input select for adc 2.
inp_sel_adc3 <4:0> Input select for adc 3.
inp_sel_adc4 <4:0> Input select for adc 4.
X
X
X
X
0
0x3A
0x3B
Signal input:
AVSS
X
X
X
X
0
Signal input:
AVSS
X
X
X
X
0
Signal input:
IP2/IN2
X
X
X
X
0
Each ADC is connected to the two input signals via a full flexible cross point switch, set up by inp_sel_adcx. In single
channel mode, any one of the two inputs can be selected as valid input to the single ADC channel. In dual channel
mode, either of the two inputs can be selected to each ADC channel. The switching of inputs can be done during
normal operation, and no additional actions are needed. The switching will occur instantaneously at the end of each
SPI command.
Table 8: Select
inp_sel_adcx<4:0>
Selected Input
IP1/IN1
0001 0
0010 0
AVSS (pins 43, 44)
AVSS (pins 40, 41)
IP2/IN2
0100 0
1000 0
other
Do not use
On the HMCAD1512, if the dual-channel mode is selected in register 0x31, the input selection for ADC1 and ADC2
must be: 00010 (i.e., IP1/IN1); the input selection for ADC3 and ADC4 must be: 10000 (i.e., IP2/IN2). In the single-
channel mode, the input selection for all ADCs may be either 00010 (i.e., IP1/IN1) OR 10000 (i.e., IP2/IN2).
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Figure 8: ADC input signals through Cross Point Switch
Full-Scale Control
Hex
Address
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
fs_cntrl
<5:0>
Fine adjust ADC full scale range
0% change
X
X
X
X
X
X
0x55
The full-scale voltage range of HMCAD1512 can be adjusted using an internal 6-bit DAC controlled by the fs_cntrl
register. Changing the value in the register by one step, adjusts the full-scale range by approximately 0.3%. This
leads to a maximum range of 10% adjustment. Table 9 shows how the register settings correspond to the full-scale
range. Note that the values for full-scale range adjustment are approximate. The DAC is, however, guaranteed to be
monotonous.
The full-scale control and the programmable gain features differ in two major ways:
1. The full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the
programmable gain is a digital feature.
2. The programmable gain feature has much coarser gain steps and larger range than the full-scale
control.
Table 9: Register Values with
Corresponding Change in Full-Scale Range
fs_cntrl<5:0>
Full-Scale Range Adjustment
111111
9.70%
9.40%
111110
100001
100000
011111
0.30%
0%
-0.3%
000001
000000
-9.7%
-10%
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Current Control
Hex
Address
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
adc_curr<2:0>
ADC current scaling.
Nominal
Nominal
X
X
X
0x50
ext_vcm_bc<1:0> VCM buffer driving strength control.
X
X
There are two registers that impact performance and power dissipation.
The adc_curr register scales the current consumption in the ADC core. The performance is guaranteed at the nomi-
nal setting. Lower power consumption can be achieved by reducing the adc_curr value, see table 10. The impact on
performance is low for settings down to minimum, but will depend on the ADC sampling rate.
Table 10: ADC Current Control Settings
adc_curr<2:0>
ADC Core Current
100
101
-40% (lower performance)
-30%
-20%
110
111
-10%
000 (default)
Nominal
001
Do not use
010
011
Do not use
Do not use
The ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the VCM pin. If this pin is
not in use, the buffer can be switched off. If current is drawn from the VCM pin, the driving strength can be increased
to keep the voltage on this pin at the correct level.
Table 11: External Common Mode Voltage
Buffer Driving Strength
VCM buffer driving strength (µA) Max
ext_vcm_bc<1:0>
current sinked/sourced from VCM pin with
< 20 mV voltage change.
00
01 (default)
10
Off (VCM floating)
20
400
700
11
Start-up and Clock Jitter Control
Hex
Address
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
startup_ctrl<2:0>
jitter_ctrl<7:0>
Controls start-up time.
Clock jitter adjustment.
'000'
X
X
X
X
X
X
0x56
0x30
160 fsrms
X
X
X
X
X
To optimize start up time, a register is provided where the start-up time in number of clock cycles can be set. Some
internal circuitry have start up times that are clock frequency independent. Default counter values are set to accom-
modate these start up times at the maximum clock frequency (sampling rate). This will lead to increased start up times
at low clock frequencies. Setting the value of this register to the nearest higher clock frequency will reduce the count
values of the internal counters, to better fit the actual start up time, such that the start up time will be reduced. The
start up times from power down and sleep modes are changed by this register setting. If the clock divider is used (set
to other than 1), the input clock frequency must be divided by the divider factor to find the correct clock frequency
range (see table 7).
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Table 12: Start-Up Time Control Settings
Single Channel
Dual Channel
Clock
Clock
startup_ctrl
<2:0>
Startup Delay Startup delay
startup_ctrl
<2:0>
Startup Delay Startup Delay
frequency
range (MSPS)
Frequency
(clock cycles)
(µs)
(clock cycles)
(µs)
Range (MSPS)
100
000
001
101
640 - 900
400 - 640
260 - 400
160 - 260
120 - 160
Do not use
12288
7936
5120
3360
2080
-
12.3 - 19.2
12.4 - 19.8
12.8 - 19.7
12.9 - 21
13 - 17.3
-
100
000
001
101
320 - 450
200 - 320
130 – 200
80 - 130
6144
3968
2560
1680
1040
-
12.3 - 19.2
12.4 - 19.8
12.8 - 19.7
12.9 - 21
13 - 17.3
-
011
011
60 – 80
other
other
Do not use
jitter_ctrl<7:0> allows the user to set a trade-off between power consumption and clock jitter. If all bits in the register
is set low, the clock signal is stopped. The clock jitter depends on the number of bits set to ‘1’ in the jitter_ctrl<7:0>
register. Which bits are set high does not affect the result.
Table 13: Clock Jitter Performance
Number of bits to '1' in
Clock Jitter
Module Current
jitter_ctrl<7:0>
Performance (fsrms)
Consumption (mA)
1
2
3
4
5
6
7
8
0
160
1
2
3
4
5
6
7
8
150
136
130
126
124
122
120
Clock stopped
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
LVDS Output Configuration and Control
Hex
Address
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
low_clk_freq
Low clock frequency used.
Inactive
X
0
0
0
0
0
0
Advance LVDS data bits and
frame clock by one clock
cycle
lvds_advance
lvds_delay
Inactive
0
X
0
0x53
Delay LVDS data bits and
frame clock by one clock
cycle
Inactive
X
X
0
0
0
Controls the phase of the
LCLK output relative to data.
phase_ddr<1:0>
btc_mode
90 degrees
X
0x42
0x46
Binary two's complement
format for ADC output data.
Straight offset
binary
X
Serialized ADC output data
comes out with MSB first.
msb_first
LSB first
X
The HMCAD1512 uses an 8-bit serial LVDS output interface as shown in the Timing Diagrams section. The different
selection of number of channels uses the LVDS outputs as defined by table 14.
Table 14: Use of LVDS Outputs
Channel Set-Up
LVDS Outputs Used
D1A, D1B, D2A, D2B, D3A, D3B, D4A, D4B
D1A, D1B, D2A, D2B
Single channel
Dual channel, channel 1
Dual channel, channel 2
D3A, D3B, D4A, D4B
Maximum data output bit-rate for HMCAD1512 is 900 Mbps. The maximum sampling rate for the different configura-
tions is given by table 15. The sampling rate is set by the frequency of the input clock (FS). The frame-rate, i.e. the
frequency of the FCLK signal on the LVDS outputs, depends on the selected mode and the sampling frequency (FS)
as defined in table 16.
Table 15: Maximum Sampling Rate for Different
HMCAD1512 Configurations
Product
Single Channel (MSPS)
Dual Channel (MSPS)
HMCAD1512
900
450
Table 16: Output Data Frame Rate
Mode of Operation
Single channel
Dual channel
Frame-Rate (FCLK Frequency)
FS / 8
FS / 4
If the HMCAD1512 device is used at a low sampling rate the register bit low_clk_freq has to be set to ‘1’. See table 17
for when to use this register bit for the different modes of operation.
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Table 17: Use of Register Bit low_clk_freq
Mode of Operation
Limit When low_clk_freq Should Be Activated
Single channel
Dual channel
Quad channel
FS < 240 MHz
FS < 120 MHz
FS < 60 MHz
To ease timing in the receiver when using multiple HMCAD1512, the device has the option to adjust the timing of the
output data and the frame clock. The propagation delay with respect to the ADC input clock can be moved one LVDS
clock cycle forward or backward, by using lvds_delay and lvds_advance, respectively. See figure 10 for details. Note
that LCLK is not affected by lvds_delay or lvds_advance settings.
Input clock
TLVDS
LCLKP
LCLKN
TPROP
FCLKN
FCLKP
default:
D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
Dxxx
N-4 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2
N
N
N
N
N
N
N
TPROP
TLVDS
FCLKP
FCLKN
lvds_delay = '1':
D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5
Dxxx
N-4 N-4 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2
N
N
N
N
N
N
TLVDS
TPROP
FCLKP
FCLKN
lvds_advance = '1':
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2
Dxxx
N
N
N
N
N
N
N
N
Figure 9: LVDS output timing adjustment
The LVDS output interface of HMCAD1512 is a DDR interface. The default setting is with the LCLK rising and falling
edge transitions in the middle of alternate data windows. The phase for LCLK can be programmed relative to the
output frame clock and data bits using phase_ddr<1:0>. The LCLK phase modes are shown in figure 11. The default
timing is identical to setting phase_ddr<1:0>=’10’.
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HMCAD1512
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8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
PHASE_DDR<1:0>='01' (180 deg)
FCLKN
FCLKP
PHASE_DDR<1:0>='00' (270 deg)
FCLKN
FCLKP
LCLKP
LCLKN
LCLKN
LCLKP
Dxx<1:0>
Dxx<1:0>
PHASE_DDR<1:0>='10' (90 deg)
PHASE_DDR<1:0>='11' (0 deg)
FCLKN
FCLKP
FCLKN
FCLKP
LCLKN
LCLKP
LCLKP
LCLKN
Dxx<1:0>
Dxx<1:0>
Figure 10: Phase programmability modes for LCLK
The default data output format is offset binary. Two’s complement mode can be selected by setting the btc_mode bit
to ‘1’ which inverts the MSB.
The first bit of the frame (following the rising edge of FCLKP) is the LSB of the ADC output for default settings. Pro-
gramming the msb_first mode results in reverse bit order, and the MSB is output as the first bit following the FCLKP
rising edge.
LVDS Drive Strength Programmability
Hex
Address
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ilvds_lclk
<2:0>
LVDS current drive programmability
for LCLKP and LCLKN pins.
3.5 mA drive
3.5 mA drive
3.5 mA drive
X
X
X
ilvds_frame
<2:0>
LVDS current drive programmability
for FCLKP and FCLKN pins.
X
X
X
0x11
ilvds_dat
<2:0>
LVDS current drive programmability
for output data pins.
X
X
X
The current delivered by the LVDS output drivers can be configured as shown in table 18. The default current is
3.5mA, which is what the LVDS standard specifies.
To reduce power consumption in the HMCAD1512, Reduced Swing Data Signaling (RSDS), is recommended. The
output current drive setting should then be 1.5 mA.
Setting the ilvds_lclk<2:0> register controls the current drive strength of the LVDS clock output on the LCLKP and
LCLKN pins.
Setting the ilvds_frame<2:0> register controls the current drive strength of the frame clock output on the FCLKP and
FCLKN pins.
Setting the ilvds_dat<2:0> register controls the current drive strength of the data outputs on the D[8:1]P and D[8:1]N pins.
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Table 18: LVDS Output
Drive Strength for LCLK, FCLK & Data
ilvds_*<2:0>
LVDS Drive Strength
3.5 mA (default)
2.5 mA
000
001
101
1.5 mA (RSDS)
0.5 mA
011
100
7.5 mA
101
6.5 mA
110
5.5 mA
111
4.5 mA
Power Mode Control
Hex
Address
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
sleep2_ch
<2:1>
Channel-specific sleep mode for a
Dual Channel setup.
Inactive
Inactive
X
X
Channel-specific sleep mode for a
Single Channel setup.
sleep1_ch1
X
sleep
pd
Go to sleep-mode.
Go to power-down.
Inactive
Inactive
X
0x0F
X
PD pin configured
for power-down
mode
pd_pin_cfg
<1:0>
Configures the PD pin function.
X
X
lvds_pd_mode Controls LVDS power down mode
High z-mode
X
0x52
The HMCAD1512 device has several modes for power management, from sleep modes with short start up time to
full power down with extremely low power dissipation. There are two sleep modes, both with the LVDS clocks (FCLK,
LCLK) running, such that the synchronization with the receiver is maintained. The first is a light sleep mode (sleep*_
ch) with short start up time, and the second a deep sleep mode (sleep) with the same start up time as full power down.
Setting sleep2_ch<n> = ‘1’ sets channel <n> in a Dual Channel setup in sleep mode. Setting sleep1_ch1 = ‘1’ sets the
ADC channel in a Single Channel setup in sleep mode. This is a light sleep mode with short start up time.
Setting sleep = ‘1’, puts all channels to sleep, but keeps FCLK and LCLK running to maintain LVDS synchronization.
The start up time is the same as for complete power down. Power consumption is significantly lower than for setting
all channels to sleep by using the sleep*_ch register.
Setting pd = ‘1’ completely powers down the chip, including the band-gap reference circuit. Start-up time from this
mode is significantly longer than from the sleep*_ch mode. The synchronization with the LVDS receiver is lost since
LCLK and FCLK outputs are put in high-Z mode.
Setting pdn_pin_cfg<1:0> = ‘x1’ configures the circuit to enter sleep channel mode (all channels off) when the PD pin
is set high. This is equal to setting all channels to sleep by using sleep*_ch. The channels can not be powered down
separately using the PD pin. Setting pdn_pin_cfg<1:0> = ‘10’ configures the circuit to enter (deep) sleep mode when
the PD pin is set high (equal to setting sleep=’1’). When pdn_pin_cfg <1:0>= ‘00’, which is the default, the circuit enters
the power down mode when the PD pin is set high.
The lvds_pd_mode register configures whether the LVDS data output drivers are powered down or kept alive in sleep
and sleep channel modes. LCLK and FCLK drivers are not affected by this register, and are always on in sleep and
sleep channel modes. If lvds_pd_mode is set low (default), the LVDS output is put in high Z mode, and the driver is
completely powered down. If lvds_pd_mode is set high, the LVDS output is set to constant 0, and the driver is still on
during sleep and sleep channel modes.
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Programmable Gain
Hex
Address
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
x-gain
enabled
cgain_cfg
fine_gain_en
Configures the coarse gain setting
Enable use of fine gain.
X
0x33
Disabled
1x gain
X
Programmable coarse gain channel 1
in a Dual Channel setup.
cgain2_ch1 <3:0>
X
X
X
X
Programmable coarse gain channel 2
in a Dual Channel setup.
cgain2_ch2 <3:0>
cgain1_ch1 <3:0>
1x gain
1x gain
X
X
X
X
0x2B
Programmable coarse gain channel 1
in a 1 channel setup.
X
X
X
X
fgain_branch1<6:0> Programmable fine gain for branch1.
fgain_branch2<6:0> Programmable fine gain for branch 2.
fgain_branch3<6:0> Programmable fine gain for branch 3.
fgain_branch4<6:0> Programmable fine gain for branch 4.
fgain_branch5<6:0> Programmable fine gain for branch 5.
fgain_branch6<6:0> Programmable fine gain for branch 6.
fgain_branch7<6:0> Programmable fine gain for branch 7.
fgain_branch8<6:0> Programmable fine gain for branch 8.
0dB gain
0dB gain
0dB gain
0dB gain
0dB gain
0dB gain
0dB gain
0dB gain
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0x34
0x35
0x36
0x37
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
The device includes a digital programmable gain in addition to the Full-scale control. The programmable gain of each
channel can be individually set using a four bit code, indicated as cgain*<3:0>. The gain is configured by the register
cgain_cfg, when cgain_cfg equals ‘0’ a gain in dB steps is enabled as defined in table 20 otherwise if cgain_cfg equals
‘1’ the gain is defined by table 21. There will be no missing codes for gain settings lower than 32x (30dB), due to higher
than 8 bit resolution internally.
Table 19: Gain setting – dB Step
cgain_cfg
cgain*<3:0>
0000
0001
0010
0011
0100
0101
0110
Implemented Gain (dB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
0111
7
1000
1001
1010
1011
8
9
10
11
1100
12
1101
Not used
Not used
Not used
1110
1111
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Table 20: Gain Setting – x Step
Implemented Gain Factor
(x)
cgain_cfg
cgain*<3:0>
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
1.25
2
2.5
4
5
8
10
12.5
16
20
25
32
50
Not used
Not used
There is a digital fine gain implemented for each ADC to adjust the fine gain errors between the ADCs. The gain is
controlled by fgain_branch* as defined in table 22. There will be no missing codes when using digital fine gain, due
to higher resolution internally.
To enable the fine gain function the register bit fine_gain_en has to be activated, set to ‘1’.
Table 21: Fine Gain Setting
fgain_branchx<6:0>
Arithmetic Function
Implemented Gain (x)
Gain (dB)
0.0665
0.0655
0.0644
0.0634
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
OUT = (1 + 2-8 + 2-9 + 2-10 + 2-11 + 2-12 + 2-13) * IN
OUT = (1 + 2-8 + 2-9 + 2-10 + 2-11 + 2-12) * IN
OUT = (1 + 2-8 + 2-9 + 2-10 + 2-11 + 2-13) * IN
OUT = (1 + 2-8 + 2-9 + 2-10 + 2-11) * IN
1.0077
1.0076
1.0074
1.0073
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
OUT = (1 + 2-12 + 2-13) * IN
OUT = (1 + 2-12) * IN
OUT = (1 + 2-13) * IN
OUT = IN
1.0004
1.0002
1.0001
1.0000
1.0000
0.9999
0.9998
0.9996
0.0031
0.0021
0.001
0.0000
0.0000
-0.0011
-0.0021
-0.0032
OUT = IN
OUT = (1 - 2-13) * IN
OUT = (1 - 2-12) * IN
OUT = (1 - 2-12 - 2-13) * IN
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
OUT = (1 - 2-8 - 2-9 - 2-10 - 2-11) * IN
OUT = (1 - 2-8 - 2-9 - 2-10 - 2-11 - 2-13) * IN
OUT = (1 - 2-8 - 2-9 - 2-10 - 2-11 - 2-12) * IN
OUT = (1 - 2-8 - 2-9 - 2-10 - 2-11 - 2-12 - 2-13) * IN
0.9927
0.9926
0.9924
0.9923
-0.0639
-0.0649
-0.0660
-0.0670
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Analog Input Invert
Hex
Address
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
invert2_ch
<2:1>
Channel specific swapping of the analog
input signal for a Dual Channel setup.
IPx is positive
input
X
X
0x24
Channel specific swapping of the analog
input signal for a 1 channel setup.
IPx is positive
input
invert1_ch1
X
The IPx pin represents the positive analog input pin, and INx represents the negative (complementary) input. Setting
the bits marked invertx_ch<n:1> (individual control for each channel) causes the inputs to be swapped. INx would then
represent the positive input, and IPx the negative input.
LVDS Test Patterns
Hex
Address
Name
Description
Default
Inactive
Inactive
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Enables a repeating full-scale ramp
pattern on the outputs.
en_ramp
X
0
0
0
0
0x25
Enable the mode wherein the output
toggles between two defined codes.
custom_pat
X
Bits for the single custom pattern and
for the first code of the dual custom
pattern. <0> is the LSB.
bits_custom1
<7:0>
0x00
0x00
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0x26
0x27
bits_custom2
<7:0>
Bits for the second code of the dual
custom pattern.
To ease the LVDS synchronization setup of HMCAD1512, several test patterns can be set up on the outputs. Normal
ADC data are replaced by the test pattern in these modes. Setting en_ramp to ‘1’ sets up a repeating full-scale ramp
pattern on all data outputs. The ramp starts at code zero and is increased 1LSB every clock cycle. It returns to zero
code and starts the ramp again after reaching the full-scale code.
The device may also be made to alternate between two user-defined codes by programming custom_pat to ‘1’. The
two codes are the contents of bits_custom1<7:0> and bits_custom2<7:0>.
For normal operation, field <D6:D4> of register 0x25 should be set to 111b, which is the default value of this field
upon reset.
Note: Only one of the above patterns should be selected at the same time.
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Theory of Operation
Table 22: Dual Channel Mode
HMCAD1512 is a multi Mode high-speed, CMOS ADC,
consisting of 8 ADC branches, configured in different
channel modes, using interleaving to achieve high
speed sampling. For all practical purposes, the device
can be considered to contain 4 ADCs. Fine gain is
adjusted for each of the eight branches separately.
Sampling
Order
Fine Gain
Branch
Channel #
LVDS Output
1
2
3
4
1
2
3
4
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
1
3
2
4
5
7
6
8
1
HMCAD1512 utilizes a serial LVDS output, described
in ‘Register Description, Output Configuration and
Control’. The clocks needed (FCLK, LCLK) for the
LVDS interface are generated by an internal PLL.
2
The HMCAD1512 operate from one clock input, which
can be differential or single ended. The sampling
clocks for each of the four channels are generated
from the clock input using a carefully matched clock
buffer tree. Internal clock dividers are utilized to con-
trol the clock for each ADC during interleaving. The
clock tree is controlled by the Mode of operations.
Table 23: Single Channel Mode
Sampling
Fine Gain
Branch
Channel #
LVDS Output
Order
1
2
3
4
5
6
7
8
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
1
6
2
5
8
3
7
4
1
HMCAD1512 uses internally generated references.
The differential reference value is 1V. This results in
a differential input of −1V to correspond to the zero
code of the ADC, and a differential input of +1V to cor-
respond to the full-scale code (code 255).
The ADC employs a Pipeline converter architecture.
Each Pipeline Stage feeds its output data into the digi-
tal error correction logic, ensuring excellent differential
linearity and no missing codes.
HMCAD1512 operates from two sets of supplies and
grounds. The analog supply and ground set is identi-
fied as AVDD and AVSS, while the digital set is identi-
fied by DVDD and DVSS.
Interleaving Effects and Sampling Order
Interleaving ADCs will generate interleaving artifacts
caused by gain, offset and timing mismatch between
the ADC branches. The design of HMCAD1512 has
been optimized to minimize these effects. It is not
possible, though, to eliminate mismatch completely,
such that additional compensation may be needed,
especially when using high digital gain settings. The
internal digital fine gain control may be used to com-
pensate for gain errors between the ADC branches.
Due to the optimization of HMCAD1512 there is not
a one-to-one correspondence between the sampling
order, LVDS output order and the branch number.
Tables 23, 24 and 25 give an overview of the corre-
sponding branches, LVDS outputs and sampling order
for the different high speed modes.
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Recommended Usage
Analog Input
The analog input to HMCAD1512 ADC is a switched
capacitor track-and-hold amplifier optimized for differ-
ential operation.
Operation at common mode voltages at mid supply
is recommended even if performance will be good for
the ranges specified. The VCM pin provides a volt-
age suitable as common mode voltage reference. The
internal buffer for the VCM voltage can be switched
off, and driving capabilities can be changed program-
ming the ext_vcm_bc<1:0> register.
Figure 12: DC coupled input
The input amplifier could be inside a companion chip
or it could be a dedicated amplifier. Several suitable
single ended to differential driver amplifiers exist in the
market. The system designer should make sure the
specifications of the selected amplifier is adequate for
the total system, and that driving capabilities comply
with HMCAD1512 input specifications.
Detailed configuration and usage instructions must be
found in the documentation of the selected driver, and
the values given in figure 13 must be adjusted accord-
ing to the recommendations for the driver.
AC-Coupling
Figure 11: Input configuration
Figure 12 shows a simplified drawing of the input net-
work. The signal source must have sufficiently low
output impedance to charge the sampling capacitors
within one clock cycle. A small external resistor (e.g.
22 ohm) in series with each input is recommended
as it helps reducing transient currents and dampens
ringing behavior. A small differential shunt capacitor at
the chip side of the resistors may be used to provide
dynamic charging currents and may improve perfor-
mance. The resistors form a low pass filter with the
capacitor, and values must therefore be determined by
requirements for the application.
Figure 13: Transformer coupled input
A signal transformer or series capacitors can be used
to make an AC-coupled input network. Figure 14
shows a recommended configuration using a trans-
former. Make sure that a transformer with sufficient
linearity is selected, and that the bandwidth of the
transformer is appropriate. The bandwidth should
preferably exceed the sampling rate of the ADC sev-
eral times. It is also important to minimize phase mis-
match between the differential ADC inputs for good
HD2 performance. This type of transformer coupled
input is the preferred configuration for high frequency
signals as most differential amplifiers do not have ade-
quate performance at high frequencies. Magnetic cou-
pling between the transformers and PCB traces may
impact channel crosstalk, and must hence be taken
into account during PCB layout.
DC-Coupling
Figure 13 shows a recommended configuration for
DC-coupling. Note that the common mode input volt-
age must be controlled according to specified values.
Preferably, the CM_EXT output should be used as ref-
erence to set the common mode voltage.
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HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
If the input signal is traveling a long physical distance
The quality of the input clock is extremely important
for high-speed, high-resolution ADCs. The contribu-
tion to SNR from clock jitter with a full scale signal at a
given frequency is shown in equation 1.
from the signal source to the transformer (for example
a long cable), kick-backs from the ADC will also travel
along this distance. If these kick-backs are not termi-
nated properly at the source side, they are reflected
and will add to the input signal at the ADC input. This
could reduce the ADC performance. To avoid this
effect, the source must effectively terminate the ADC
kick-backs, or the traveling distance should be very
short.
SNRjitter = 20 · log (2 · π · ƒIN · єt)
(1)
where fIN is the signal frequency, and εt is the total
rms jitter measured in seconds. The rms jitter is the
total of all jitter sources including the clock generation
circuitry, clock distribution and internal ADC circuitry.
For applications where jitter may limit the obtainable
performance, it is of utmost importance to limit the
clock jitter. This can be obtained by using precise and
stable clock references (e.g. crystal oscillators with
good jitter specifications) and make sure the clock dis-
tribution is well controlled. It might be advantageous
to use analog power and ground planes to ensure
low noise on the supplies to all circuitry in the clock
distribution. It is of utmost importance to avoid cross-
talk between the ADC output bits and the clock and
between the analog input signal and the clock since
such crosstalk often results in harmonic distortion.
Figure 14: AC coupled input
Figure 15 shows AC-coupling using capacitors. Resis-
tors from the CM_EXT output, RCM, should be used
to bias the differential input signals to the correct volt-
age. The series capacitor, CI, form the high-pass pole
with these resistors, and the values must therefore be
determined based on the requirement to the high-pass
cut-off frequency.
The jitter performance is improved with reduced rise
and fall times of the input clock. Hence, optimum jitter
performance is obtained with LVDS or LVPECL clock
with fast edges. CMOS and sine wave clock inputs will
result in slightly degraded jitter performance.
Note that Start Up Time from Sleep Mode and Power
Down Mode will be affected by this filter as the time
required to charge the series capacitors is dependent
on the filter cut-off frequency.
If the clock is generated by other circuitry, it should
be re-timed with a low jitter master clock as the last
operation before it is applied to the ADC clock input.
Clock Input and Jitter Considerations
Application Usage Example
Typically high-speed ADCs use both clock edges to
generate internal timing signals. In HMCAD1512 only
the rising edge of the clock is used.
This section gives an overview on how HMCAD1512
can be used in an application utilizing all active modes
with a single clock source. The example assumes that
a 1 GHz clock source is applied. A differential clock
should be used, and can be generated from a single
ended crystal oscillator, using a transformer or balun
in conjunction with ac-coupling to convert from single
ended to differential signal.
The input clock can be supplied in a variety of for-
mats. The clock pins are AC-coupled internally, hence
a wide common mode voltage range is accepted.
Differential clock sources such as LVDS, LVPECL or
differential sine wave can be utilized. LVDS/LVPECL
clock signals must be appropriately terminated as
close to the ADC clock pins as possible. For CMOS
inputs, the CLKN pin should be connected to ground,
and the CMOS clock signal should be connected to
CLKP. CMOS input clock is not recommended above
200 MHz clock frequency. For differential sine wave
clock input the amplitude must be at least 0.8 Vpp.
No additional configuration is needed to set up the
clock source format.
Start-up Initialization
The start-up sequence will be as follows:
• Apply power
• Apply reset (RESETN low, then high, or SPI com-
mand 0x00 0x0001)
• Set power down (PD pin high or SPI command
0x0F 0x0200)
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
27
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
• Set LVDS bit clock phase (phase_ddr, regis-
ter 0x42)) if other than default must be used
(depends on the receiver).
• Select operating mode, for instance dual channel
mode, and clock divider factor (SPI command
0x31 0x0102).
Table 24: Overview of
Operating Modes and Setup Conditions
Sampling
Speed
(MSPS)
Clock
Divider
Factor
SPI command for
Mode Selection and
Clock Divider
Operating
Mode
• Set active mode (PD pin low or SPI command
0x0F 0x0000)
Single
channel
900
450
1
2
0x31 0x0001
0x31 0x0102
• Select analog inputs, for instance input 1 on
channel 1 and input 3 on channel 2 (SPI com-
mands 0x3A 0202 and 0x3B 0808)
Dual channel
Select Analog Input
Change Mode
When an operational mode is selected, the analog
inputs can be changed ‘on-the-fly’. To change analog
input one merely have to apply the dedicated SPI
commands. The change will occur instantaneously at
the end of each SPI command.
When changing operational mode, power down must
be activated due to internal synchronization routines.
A typical mode change will then be like this:
• Set power down (PD pin high or SPI command
0x0F 0x0200)
Table 25: Example of
Some Analog Input Selections
• Change mode to for example Single channel
mode (SPI command 0x31 0x0001)
Signal Input
Selection
Operating Mode
SPI Commands
• Set active mode (PD pin low or SPI command
0x0F 0x0000)
Single channel
IP2/IN2
0x3A 1010, 0x3B 1010
Ch1: IP1/IN1
Ch2: IP2/IN2
Dual channel
0x3A 0404, 0x3B 0808
• Select analog inputs, for instance Input 1 (SPI
commands 0x3A 0202 and 0x3B 0202)
Table 25 gives an overview of the operational modes
in this example and the SPI commands to apply for
each mode.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
28
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Outline Drawing
Table 26: 7x7 mm QFN 48 Pin (LP7) Dimensions
Millimeter
Inch
Typ
Symbol
Min
0.8
0
Typ
0.9
Max
1
Min
0.031
0
Max
0.039
0.002
A
A1
A2
b
0.035
0.02
0.05
0.0008
0.008
0.2
0.18
0.25
0.3
0.007
0.01
0.012
D
7.00 bsc
5.3
0.276 bsc
0.209
D2
L
5.15
0.3
5.4
0.5
0.203
0.012
0.213
0.02
0.4
0.016
e
0.50 bsc
0.020 bsc
F
0.2
0.008
Package Information
Part Number
Package Body Material
Lead Finish
MSL [1]
Level 2A
Package Marking [2]
HAD1511
XXXX
HMCAD1512
RoHS-compliant Low Stress Injection Molded Plastic
100% matte Sn
[1] MSL, Peak Temp: The moisture sensitivity level rating classified according to the JEDEC industry standard and to peak solder temperature.
[2] Proprietary marking XXXX, 4-Digit lot number XXXX
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
29
Application Support: Phone: 978-250-3343 or apps@hittite.com
HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
Notes:
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
30
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