T25S32CBIGT [HMSEMI]
3V 128M-BIT SERIAL NOR FLASH WITH DUAL AND QUAD SPI&QPI;
| 型号： | T25S32CBIGT |
| 厂家： | 
H&M Semiconductor |
| 描述： | 3V 128M-BIT SERIAL NOR FLASH WITH DUAL AND QUAD SPI&QPI |
| 文件： | 总74页 (文件大小：8655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM25Q128A
V1.1
3V 128M-BIT
SERIAL NOR FLASH WITH
DUAL AND QUAD SPI&QPI
1
HM25Q128A
Contents
FEATURES................................................................................................................................................................. 5
GENERAL DESCRIPTION.......................................................................................................................................5
1. ORDERING INFORMATION....................................................................................................................... 7
2. BLOCK DIAGRAM........................................................................................................................................ 8
3. CONNECTION DIAGRAMS........................................................................................................................ 9
4. SIGNAL DESCRIPTIONS..........................................................................................................................10
4.1. Serial Data Input (DI) / IO0.............................................................................................................10
4.2. Serial Data Output (DO) / IO1....................................................................................................... 10
4.3. Serial Clock (CLK)...........................................................................................................................10
4.4. Chip Select (CS#)............................................................................................................................10
4.5. Write Protect (WP#) / IO2...............................................................................................................11
4.6. HOLD (HOLD#) / IO3...................................................................................................................... 11
4.7. RESET (RESET#) / IO3..................................................................................................................11
5. MEMORY ORGANIZATION...................................................................................................................... 12
5.1. Flash Memory Array........................................................................................................................ 12
5.2. Security Registers............................................................................................................................12
5.2.1 Security Register 0................................................................................................................13
5.2.2 Serial Flash Discoverable Parameters (SFDP) Address Map.......................................13
5.2.3 SFDP Header Field Definitions...........................................................................................14
5.2.4 JEDEC SFDP Basic SPI Flash Parameter....................................................................... 15
6. FUNCTION DESCRIPTION...................................................................................................................... 20
6.1 SPI Operations..................................................................................................................................20
6.1.1 SPI Modes.............................................................................................................................. 20
6.1.2 Dual SPI Modes.....................................................................................................................20
6.1.3 Quad SPI Modes................................................................................................................... 20
6.1.4 QPI Function.......................................................................................................................... 21
6.1.5 Hold Function.........................................................................................................................21
6.1.6 Software Reset & Hardware RESET# pin.........................................................................21
6.2. Status Register.................................................................................................................................22
6.2.1 BUSY.......................................................................................................................................24
6.2.2 Write Enable Latch (WEL)................................................................................................... 24
6.2.3 Block Protect Bits (BP2, BP1, BP0)................................................................................... 24
6.2.4 Top / Bottom Block Protect (TB)..........................................................................................24
6.2.5 Sector / Block Protect (SEC)...............................................................................................25
6.2.6 Complement Protect (CMP)................................................................................................ 25
6.2.7 The Status Register Protect (SRP1, SRP0)..................................................................... 25
6.2.8 Erase / Program Suspend Status (SUS)...........................................................................25
6.2.9 Security Register Lock Bits (LB3, LB2, LB1)....................................................................25
6.2.10 Quad Enable (QE)...............................................................................................................26
6.2.11 HOLD# or RESET# Pin Function (HRSW)..................................................................... 26
6.2.12 Output Driver Strength (DRV1, DRV0)............................................................................26
6.2.13 High Frequency Enable Bit (HFQ)................................................................................... 26
6.2.14 Write Protect Selection (WPS)..........................................................................................26
6.2.15 Latency Control (LC)...........................................................................................................26
6.3. Write Protection................................................................................................................................27
6.3.1 Write Protect Features..........................................................................................................27
6.3.2 Block Protection Maps..........................................................................................................29
6.4. Page Program.................................................................................................................................. 32
6.5. Sector Erase, Block Erase and Chip Erase................................................................................ 32
6.6. Polling during a Write, Program or Erase Cycle.........................................................................32
6.7. Active Power, Stand-by Power and Deep Power-Down Modes.............................................. 32
7. INSTRUCTIONS..........................................................................................................................................33
7.1 Configuration and Status Commands........................................................................................... 39
7.1.1 Read Status Register (05h/35h/15h)................................................................................. 39
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HM25Q128A
7.1.2 Write Enable (06h)................................................................................................................ 39
7.1.3 Write Enable for Volatile Status Register (50h)................................................................40
7.1.4 Write Disable (04h)................................................................................................................40
7.1.5 Write Status Register (01h/31h/11h)..................................................................................40
7.2 Program and Erase Commands.....................................................................................................41
7.2.1 Page Program (PP) (02h).................................................................................................... 42
7.2.2 Quad Input Page Program (32h)........................................................................................ 42
7.2.3 Sector Erase (SE) (20h).......................................................................................................43
7.2.4 Block Erase (BE) (D8h) and Half Block Erase (52h).......................................................44
7.2.5 Chip Erase (CE) (C7h or 60h).............................................................................................44
7.2.6 Erase / Program Suspend (75h).........................................................................................45
7.2.7 Erase / Program Resume (7Ah)......................................................................................... 46
7.3 Read Commands..............................................................................................................................46
7.3.1 Read Data (03h).................................................................................................................... 46
7.3.2 Fast Read (0Bh).................................................................................................................... 47
7.3.3 Fast Read Dual Output (3Bh)..............................................................................................48
7.3.4 Fast Read Quad Output (6Bh)............................................................................................ 48
7.3.5 Fast Read Dual I/O (BBh)....................................................................................................49
7.3.6 Fast Read Quad I/O (EBh).................................................................................................. 49
7.3.7 Word Read Quad I/O (E7h)................................................................................................. 51
7.3.8 Octal Word Read Quad I/O (E3h).......................................................................................52
7.3.9 Set Burst with Wrap (77h)....................................................................................................53
7.4 Reset Commands............................................................................................................................. 54
7.4.1 Software Reset Enable (66h).............................................................................................. 54
7.4.2 Software Reset (99h)............................................................................................................55
7.5 ID and Security Commands............................................................................................................55
7.5.1 Deep Power-down (DP) (B9h)............................................................................................ 55
7.5.2 Release Power-down / Device ID (ABh)........................................................................... 55
7.5.3 Read Manufacturer / Device ID (90h)................................................................................56
7.5.4 Read Identification (RDID) (9Fh)........................................................................................57
7.5.5 Read SFDP Register (5Ah)................................................................................................. 57
7.5.6 Erase Security Registers (44h)...........................................................................................58
7.5.7 Program Security Registers (42h)......................................................................................58
7.5.8 Read Security Registers (48h)............................................................................................59
7.5.9 Individual Block/Sector Lock (36h).....................................................................................59
7.5.10 Individual Block/Sector Unlock (39h)...............................................................................60
7.5.11 Read Block/Sector Lock (3Dh)..........................................................................................61
7.5.12 Global Block/Sector Lock (7Eh)........................................................................................61
7.5.13 Global Block/Sector Unlock (98h).................................................................................... 62
7.5.14 Read Manufacturer / Device ID Dual I/O (92h)..............................................................62
7.5.15 Read Manufacturer / Device ID Quad I/O (94h)............................................................ 63
7.5.16 Read Unique ID Number (4Bh).........................................................................................63
7.5.17 Set Read Parameters (C0h)..............................................................................................63
7.5.18 Burst Read with Wrap (0Ch)............................................................................................. 64
7.5.19 Enter QPI Mode (38h)........................................................................................................ 65
7.5.20 Exit QPI Mode (FFh)...........................................................................................................65
8. ELECTRICAL CHARACTERISTIC.......................................................................................................... 66
8.1. Absolute Maximum Ratings........................................................................................................... 67
8.2. Recommended Operating Ranges...............................................................................................67
8.3. DC Characteristics...........................................................................................................................68
8.4. AC Measurement Conditions.........................................................................................................68
8.5. AC Electrical Characteristics..........................................................................................................69
9. PACKAGE MECHANICAL.........................................................................................................................71
9.1. 8-Pin SOIC 150-mil..........................................................................................................................71
9.2. 8-Pin SOIC 208-mil..........................................................................................................................71
9.3. 8-Contact WSON (6x5mm)............................................................................................................72
9.4. 8-Pin PDIP 300-mil..........................................................................................................................72
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HM25Q128A
9.5. FAB024 24-Ball BGA.......................................................................................................................73
9.6. FAC024 24-Ball BGA Package......................................................................................................73
REVISION LIST....................................................................................................................................................... 74
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HM25Q128A
FEATURES
Low power supply operation
- Single 2.3V-3.6V supply
Flexible Architecture with 4KB sectors
- Sector Erase (4K-bytes)
128 Mbit Serial Flash
- Block Erase (32K/64K-bytes)
- Page Program up to 256 bytes
- More than 100K erase/program cycles
- More than 20-year data retention
- 128 M-bit/16M-byte/65,536 pages
- 256 bytes per programmable page
- Uniform 4K-byte Sectors, 32K/64K-byte Blocks
New Family of SpiFlash Memories
- Standard SPI: CLK, CS#, DI, DO, WP#,
HOLD# / RESET#
Advanced Security Feature
- Software and Hardware Write-Protect
- Power Supply Lock-Down and OTP
protection
- Dual SPI: CLK, CS#, DI, DO, WP#, HOLD# /
RESET#
- Quad SPI: CLK, CS#, IO0, IO1, IO2, IO3
- QPI: CLK, CS#, IO0, IO1, IO2, IO3
- Software & Hardware Reset
- Auto-increment Read capability
- Top/Bottom, Complement array protection
- Individual Block/Sector array protection
- 64-Bit Unique ID for each device
- Discoverable parameters(SFDP) register
- 3X256-Bytes Security Registers with OTP
locks
Temperature Ranges
- Volatile & Non-volatile Status Register Bits
- Industrial (-40°C to +85°C)
High performance program/erase speed
- Page program time: 500us typical
- Sector erase time: 35ms typical
- Extended (-20°C to +85°C)
Low power consumption
- 9 mA typical active current
- 2 uA typical power down current
- Block erase time: 250ms typical
- Chip erase time: 50 Seconds typical
Package Options
Efficient “Continuous Read” and QPI Mode
- Continuous Read with 8/16/32/64-Byte Wrap
- As few as 8 clocks to address memory
- Quad Peripheral Interface(QPI) reduces
instruction overhead
- 8-pin SOIC 150/208-mil
- 8-pad WSON 6x5-mm
- 8-pin PDIP 300-mil
- All Pb-free packages are RoHS compliant
GENERAL DESCRIPTION
The HM25Q128A-PWof non-volatile flash memory device supports the standard Serial Peripheral Interface
(SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two
bit (Dual I/O or DIO) and four bit (quad I/O or QIO) serial protocols. This multiple width interface is called SPI
Multi-I/O or MIO.
The SPI protocols use only 4 to 6 signals:
Chip Select (CS#)
Serial Clock (CLK)
Serial Data
- IO0 (DI)
- IO1 (DO)
- IO2 (WP#)
- IO3 (HOLD# / RESET#)
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HM25Q128A
The HM25Q128A support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as
2-clocks instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0 (DI),
I/O1 (DO), I/O2 (WP#), and I/O3 (HOLD# / RESET#). SPI clock frequencies of up to 104MHz are supported
allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O
when using the Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can outperform standard
Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory
access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in
place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide
further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID and
SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers.
The HM25Q128A provides an ideal storage solution for systems with limited space, signal connections,
and power. These memories' flexibility and performance is better than ordinary serial flash devices. They are
ideal for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.
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HM25Q128A
1. ORDERING INFORMATION
The ordering part number is formed by a valid combination of the following:
Figure 1.1 Ordering Information
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HM25Q128A
2. BLOCK DIAGRAM
Figure 2 1 Block Diagram
8
HM25Q128A
3. CONNECTION DIAGRAMS
Figure 3.1 8-pin SOP (150/208mil)/ PDIP (300mil)
Figure 3.2 8-Contact 6 x 5 mm WSON
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HM25Q128A
4. SIGNAL DESCRIPTIONS
Table 4.1 Pin Descriptions
Symbol
Pin Name
CLK
Serial Clock Input
Serial Data Input(Data input output 0) (1)
Serial Data Output(Data input output 1) (1)
Chip Enable
DI(IO0)
DO(IO1)
CS#
WP#(IO2)(3)
HOLD# / RESET#(3)(IO3)
VCC
Write Protect (Data input output 2) (2)
Hold or Reset input(Data input output 3) (2)
Power Supply (2.3-3.6V)
GND
Ground
Notes:
(1)IO0 and IO1 are used for Standard and Dual SPI instructions.
(2)IO0—IO3 are used for QUAD SPI / QPI instructions.
(3)WP# and HOLD# / RESET# functions are only available for Standard and Dual SPI.
4.1. Serial Data Input (DI) / IO0
The SPI Serial Data Input (DI) pin is used to transfer data serially into the device. It receives instructions,
address and data to be programmed. Data is latched on the rising edge of the Serial Clock (CLK) input pin.
The DI pin becomes IO0 - an input and output during Dual and Quad commands for receiving instructions,
address, and data to be programmed (values latched on rising edge of serial CLK clock signal) as well as
shifting out data (on the falling edge of CLK).
4.2. Serial Data Output (DO) / IO1
The SPI Serial Data Output (DO) pin is used to transfer data serially out of the device. Data is shifted out
on the falling edge of the Serial Clock (CLK) input pin. DO becomes IO1 - an input and output during Dual and
Quad commands for receiving instructions, addresses, and data to be programmed (values latched on rising
edge of serial CLK clock signal) as well as shifting out data (on the falling edge of CLK).
4.3. Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Mode")
4.4. Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, CS# must transition from high to low before a new instruction will be accepted.
10
HM25Q128A
4.5. Write Protect (WP#) / IO2
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1 and BP2, TB, SEC, CMP) bits and Status
Register Protect (SRP0) bits, a portion or the entire memory array can be hardware protected.
The WP# function is not available when the Quad mode is enabled. The WP# function is replaced by IO2
for input and output during Quad mode for receiving addresses and data to be programmed (values are
latched on rising edge of the CLK signal) as well as shifting out data (on the falling edge of CLK).
4.6. HOLD (HOLD#) / IO3
The HOLD# pin allows the device to be paused while it is actively selected. When HRSW bit is ‘0’ (factory
default is ‘0’), the HOLD# pin is enabled. When HOLD# is brought low, while CS# is low, the DO pin will be at
high impedance and signals on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high,
device operation can resume. The HOLD# function can be useful when multiple devices are sharing the same
SPI signals. The HOLD# pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the
HOLD# pin function is not available since this pin is used for IO3.
4.7. RESET (RESET#) / IO3
The RESET# pin allows the device to be reset by the controller. When HRSW bit is ‘1’ (factory default is
‘0’), the RESET# pin is enabled. Drive RESET# low for a minimum period of ~1us (tRESET*) will interrupt any
on-going external/internal operations, regardless the status of other SPI signals (CS#, CLK, DI, DO, WP#
and/or HOLD#). The Hardware Reset function is only available for standard SPI and Dual SPI operation,
when QE=0, the IO3 pin can be configured either as a HOLD# pin or as a RESET# pin depending on Status
Register setting, when QE=1, this pin is the Serial Data IO (IO3) for Quad I/O operation.
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HM25Q128A
5. MEMORY ORGANIZATION
5.1. Flash Memory Array
The memory is organized as:
- 16,777,216bytes
- Uniform Sector Architecture 256 blocks of 64-Kbyte
- 4096 sectors of 4-Kbyte
- 65, 536 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
Table 5.1(1) Memory Organization
Block/ Security
Sector
Address range
Register/SFDP
Security Register 3
Security Register 2
Security Register 1
-
-
-
003000H
002000H
001000H
0030FFH
0020FFH
0010FFH
Security Register 0
(SFDP)
-
000000H
0000FFH
4095
......
4080
4079
......
4064
......
......
......
......
......
......
47
FFF000H
......
FFFFFFH
......
Block 255
Block 254
......
FF0000H
FEF000H
......
FF0FFFH
FEFFFFH
......
FE0000H
......
FE0FFFH
......
......
......
......
......
......
......
......
......
......
......
......
02F000H
......
02FFFFH
......
Block 2
Block 1
Block 0
......
32
020000H
01F000H
......
020FFFH
01FFFFH
......
31
......
16
010000H
00F000H
......
010FFFH
00FFFFH
......
15
......
0
000000H
000FFFH
Notes:
(1)These are condensed tables that use a couple of sectors as references. There are address ranges that are not explicitly
listed. All 4-kB sectors have the pattern XXX000h-XXXFFFh.
5.2. Security Registers
The HM25Q128A provides four 256-byte Security Registers. Each register can be used to store
information that can be permanently protected by programming One Time Programmable (OTP) lock bits in
Status Register-2.
Register 0 is used byFSRKto store and protect the Serial Flash Discoverable Parameters (SFDP)
information that is also accessed by the Read SFDP command. See Table 5.1.
The three additional Security Registers can be erased, programmed, and protected individually. These
12
HM25Q128A
registers may be used by system manufacturers to store and permanently protect security or other important
information separate from the main memory array.
5.2.1 Security Register 0
Serial Flash Discoverable Parameters (SFDP — JEDEC JESD216B):
This document defines the Serial Flash Discoverable Parameters (SFDP) revision B data structure for
HM25Q128A
family.
The Read SFDP (RSFDP) command (5Ah) reads information from a separate flash memory address
space for device identification, feature, and configuration information, in accord with the JEDEC JESD216B
standard for Serial Flash Discoverable Parameters.
The SFDP data structure consists of a header table that identifies the revision of the JESD216 header
format that is supported and provides a revision number and pointer for each of the SFDP parameter tables
that are provided. The parameter tables follow the SFDP header. However, the parameter tables may be
placed in any physical location and order within the SFDP address space. The tables are not necessarily
adjacent nor in the same order as their header table entries.
The SFDP header points to the following parameter tables:
Basic Flash
– This is the original SFDP table.
The physical order of the tables in the SFDP address space is: SFDP Header, and Basic Flash. The
SFDP address space is programmed byFSRKand read-only for the host system.
5.2.2 Serial Flash Discoverable Parameters (SFDP) Address Map
The SFDP address space has a header starting at address zero that identifies the SFDP data structure
and provides a pointer to each parameter. One Basic Flash parameter is mandated by the JEDEC JESD216B
standard.
Table 5.2 SFDP Overview Map — Security Register 0
Byte Address
0000h
Description
Location zero within JEDEC JESD216B SFDP space – start of SFDP header
Undefined space reserved for future SFDP header
Start of SFDP parameter
0010h
0030h
...
006Fh
Remainder of SFDP JEDEC parameter followed by undefined space
End of SFDP space
0070h to 00FFh
Reserved space
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HM25Q128A
5.2.3 SFDP Header Field Definitions
Table 5.3 SFDP Header
SFDP Byte SFDP Dword
Data
Description
Address
Name
This is the entry point for Read SFDP (5Ah) command i.e. location zero within
SFDP space
00h
53h
ASCII “S”
ASCII “F”
ASCII “D”
ASCII “P”
SFDP Header
1st DWORD
01h
02h
03h
46h
44h
50h
SFDP Minor Revision (06h = JEDEC JESD216 Revision B)
– This revision is backward compatible with all prior minor revisions. Minor
revisions are changes that define previously reserved fields, add fields to the
end, or that clarify definitions of existing fields. Increments of the minor revision
value indicate that previously reserved parameter fields may have been
assigned a new definition or entire Dwords may have been added to the
parameter table. However, the definition of previously existing fields is
unchanged and therefore remains backward compatible with earlier SFDP
parameter table revisions. Software can safely ignore increments of the minor
revision number, as long as only those parameters the software was designed
to support are used i.e. Previously reserved fields and additional Dwords must
be masked or ignored. Do not do a simple compare on the minor revision
number, looking only for a match with the revision number that the software is
designed to handle. There is no problem with using a higher number minor
revision.
04h
06h
SFDP Header
2nd DWORD
SFDP Major Revision
05h
01h
– This is the original major revision. This major revision is compatible with all
SFDP reading and parsing software.
06h
07h
08h
00h
FFh
00h
Number of Parameter Headers (zero based, 00h = 1 parameters
Unused
Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
Parameter Minor Revision (00h = JESD216)
–This older revision parameter header is provided for any legacy SFDP reading
and parsing software that requires seeing a minor revision 6 parameter header.
SFDP software designed to handle later minor revisions should continue
reading parameter headers looking for a higher numbered minor revision that
contains additional parameters for that software revision.
Parameter Major Revision (01h = The original major revision - all SFDP
software is compatible with this major revision.
Parameter Table Length (in double words = Dwords = 4-byte units) 10h = 16
Dwords
Parameter Table Pointer Byte 0 (Dword = 4-byte aligned) JEDEC Basic SPI
Flash parameter byte offset = 30h
09h
06h
Parameter Header
0 1st DWORD
0Ah
0Bh
0Ch
01h
10h
30h
Parameter Header
0 2nd DWORD
0Dh
0Eh
0Fh
00h
00h
FFh
Parameter Table Pointer Byte 1
Parameter Table Pointer Byte 2
Parameter ID MSB (FFh = JEDEC defined legacy Parameter ID)
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HM25Q128A
5.2.4 JEDEC SFDP Basic SPI Flash Parameter
Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Sheet 1 of 5)
SFDP
Parameter
Relative
Byte
SFDP Dword
Name
Data
Description
Address
Start of SFDP JEDEC parameter
Bits 7:5 = unused = 111b
Bit 4:3 = 05h is volatile status register write instruction and status register is
default non-volatile= 00b
Bit 2 = Program Buffer > 64 bytes = 1
Bits 1:0 = Uniform 4-kB erase is supported throughout the device = 01b
Bits 15:8 = Uniform 4-kB erase instruction = 20h
Bit 23 = Unused = 1b
30h
31h
E5h
20h
JEDEC
Basic Flash
Parameter
Dword-1
Bit 22 = Supports QOR Read (1-1-4), Yes = 1b
Bit 21 = Supports QIO Read (1-4-4),Yes =1b
Bit 20 = Supports DIO Read (1-2-2), Yes = 1b
Bit19 = Supports DDR, No= 0 b
Bit 18:17 = Number of Address Bytes 3 only = 00b
Bit 16 = Supports SIO and DIO Yes = 1b
Binary Field: 1-1-1-1-0-00-1
32h
F1h
Nibble Format: 1111_0001
Hex Format: F1
33h
34h
35h
36h
FFh
FFh
FFh
FFh
07h
Bits 31:24 = Unused = FFh
JEDEC
Density in bits, zero based,
32 Mb = 01FFFFFFh
64 Mb = 03FFFFFFh
128 Mb = 07FFFFFFh
Basic Flash
Parameter
Dword-2
37h
Bits 7:5 = number of QIO (1-4-4)Mode cycles = 010b
Bits 4:0 = number of Fast Read QIO Dummy cycles = 00100b for default
latency code
Fast Read QIO (1-4-4)instruction code
Bits 23:21 = number of Quad Out (1-1-4) Mode cycles = 000b
Bits 20:16 = number of Quad Out Dummy cycles = 01000b for default latency
code
38h
39h
3Ah
44h
EBh
08h
JEDEC
Basic Flash
Parameter
Dword-3
3Bh
3Ch
3Dh
6Bh
08h
3Bh
Quad Out (1-1-4)instruction code
Bits 7:5 = number of Dual Out (1-1-2)Mode cycles = 000b
Bits 4:0 = number of Dual Out Dummy cycles = 01000b for default latency code
Dual Out (1-1-2) instruction code
Bits 23:21 = number of Dual I/O Mode cycles = 100b
Bits 20:16 = number of Dual I/O Dummy cycles = 00000b for default latency
code
JEDEC
Basic Flash
Parameter
Dword-4
3Eh
3Fh
80h
BBh
Dual I/O instruction code
Bits 7:5 RFU = 111b
Bit 4 = QPI (4-4-4) fast read commands supported = 1b
Bits 3:1 RFU = 111b
Bit 0 = Dual All not supported = 0b
Bits 15:8 = RFU = FFh
Bits 23:16 = RFU = FFh
Bits 31:24 = RFU = FFh
Bits 7:0 = RFU = FFh
Bits 15:8 = RFU = FFh
40h
FEh
JEDEC
Basic Flash
Parameter
Dword-5
41h
42h
43h
44h
45h
FFh
FFh
FFh
FFh
FFh
JEDEC
Basic Flash
Parameter
Dword-6
Bits 23:21 = number of Dual All Mode cycles = 111b
Bits 20:16 = number of Dual All Dummy cycles = 11111b
Dual All instruction code
46h
47h
FFh
FFh
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HM25Q128A
Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Sheet 2 of 5)
SFDP
Parameter
Relative
Byte
SFDP Dword
Name
Data
Description
Address
48h
49h
FFh
FFh
Bits 7:0 = RFU = FFh
Bits 15:8 = RFU = FFh
Bits 23:21 = number of QPI Mode cycles = 010b
Bits 20:16 = number of QPI Dummy cycles = 00010b for default latency code
QPI instruction code
Erase Type 1 size 2N Bytes = 4 kB = 0Ch (for Uniform 4 kB)
Erase Type 1 instruction
Erase Type 2 size 2N Bytes = 32 kB = 0Fh (for Uniform 32 kB)
Erase Type 2 instruction
Erase Type 3 size 2N Bytes =64 kB = 10h(for Uniform 64 kB)
Erase Type 3 instruction
Erase Type 4 size 2N Bytes = not supported = 00h
Erase Type 4 instruction = not supported = FFh
JEDEC
Basic Flash
Parameter
Dword-7
4Ah
FFh
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
EBh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
JEDEC
Basic Flash
Parameter
Dword-8
JEDEC
Basic Flash
Parameter
Dword-9
JEDEC
Bits 31:30 = Erase Type 4 Erase, Typical time units (00b: 1 ms, 01b: 16 ms,
10b: 128 ms, 11b:1 s) = RFU = 11b
Bits 29:25 = Erase Type 4 Erase, Typical time count = RFU = 11111b (typ erase
time = (count+1) * units) = RFU =11111
Basic Flash
Parameter
Dword-4
54h
13h
Bits 24:23 = Erase Type 3 Erase, Typical time units (00b: 1 ms, 01b: 16 ms,
10b: 128 ms, 11b:1 s) = RFU = 01b
55h
56h
5Ah
BDh
Bits 22:18 = Erase Type 3 Erase, Typical time count = 01111b (typ erase time =
(count +1) *units) = 16*16 ms =250ms
Bits 17:16 = Erase Type 2 Erase, Typical time units (00b: 1 ms, 01b: 16 ms,
10b: 128 ms, 11b:1 s) = 16 ms = 01b
Bits 15:11 = Erase Type 2 Erase, Typical time count = 01011b (typ erase time =
(count +1) *units) = 12*16 ms = 180 ms
Bits 10:9 = Erase Type 1 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b:
128 ms, 11b: 1s) = 16ms = 01b
Bits 8:4 = Erase Type 1 Erase, Typical time count = 00001b (typ erase time =
(count +1) *units) = 2*16 ms = 35 ms
57h
FEh
Bits 3:0 = Count = (Max Erase time / (2 * Typical Erase time))- 1 = 0011b
Multiplier from typical erase time to maximum erase time = 8x multiplier
Max Erase time = 2*(Count +1)*Typ Erase time
Binary Fields: 1111111_0101111_0101011_0100001_0011
Nibble Format: 1111_1110_1011_1101_0101_1010_0001_0011
Hex Format: FE_BD_5A_13
16
HM25Q128A
Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Sheet 3 of 5)
SFDP
SFDP
Dword
Name
Parameter
Relative Byte
Address
58h
Data
Description
81h
67h
Bits 23 = Byte Program Typical time, additional byte units (0b:1 μs, 1b:8 μs) = 1 μs
= 0b
59h
Bits 22:19 = Byte Program Typical time, additional byte count, (count+1)*units,
count = 0010b,(typ Program time = (count +1) * units) = 3*1 μs =3 μs
Bits 18 = Byte Program Typical time, first byte units (0b:1 μs, 1b:8 μs) = 8 μs = 1b
Bits 17:14 = Byte Program Typical time, first byte count, (count+1)*units, count =
0001b, (typ Program time = (count +1) * units) = 2*8 μs = 16 μs
Bits 13 = Page Program Typical time units (0b:8 μs, 1b:64 μs) = 64 μs = 1b
Bits 12:8 = Page Program Typical time count, (count+1)*units, count = 00111b, (typ
Program time = (count +1) * units) = 8*64 μs = 500 μs
Bits 7:4 = N = 1000b, Page size= 2N = 256B page
JEDEC
Basic
Flash
5Ah
14h
Bits 3:0 = Count = 0001b = (Max Page Program time / (2 * Typ Page Program
time))- 1
Parameter
Dword-11
Multiplier from typical Page Program time to maximum Page Program time = 4x
multiplier
Max Page Program time = 2*(Count +1)*Typ Page Program time
Binary Fields: 0-0010-1-0001-1-00111-1000-0001
Nibble Format: 0001_0100_0110_0111_1000_0001
Hex Format: 14_67_81
128 Mb = 1100_1100b = CCh
Bit 31 Reserved = 1b
Bits 30:29 = Chip Erase, Typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b:
64 s) = 4s= 10b
5Bh
CCh
Bits 28:24 = Chip Erase, Typical time count, (count+1)*units, count = 01100b, (typ
Program time = (count +1) * units) = 13*4s = 50s
5Ch
5Dh
5Eh
EDh
63h
16h
Bit 31 = Suspend and Resume supported = 0b
Bits 30:29 = Suspend in-progress erase max latency units (00b: 128ns, 01b: 1us,
10b: 8 μs,11b: 64 μs) = 1 μs= 01b
Bits 28:24 = Suspend in-progress erase max latency count = 10011b, max erase
suspend latency = (count +1) * units = 20*1 μs = 20 μs
Bits 23:20 = Erase resume to suspend interval count = 0001b, interval = (count +1)
* 64 μs = 2* 64 μs = 128 μs
Bits 19:18 = Suspend in-progress program max latency units (00b: 128ns, 01b: 1us,
10b: 8 μs,11b: 64 μs) = 1 μs= 01b
Bits 17:13 = Suspend in-progress program max latency count = 10011b, max erase
suspend latency = (count +1) * units = 20*1 μs = 20 μs
Bits 12:9 = Program resume to suspend interval count = 0001b, interval = (count
+1) * 64 μs =2 * 64 μs = 128 μs
JEDEC
Basic
Flash
Parameter
Dword-12
Bit 8 = RFU = 1b
Bits 7:4 = Prohibited operations during erase suspend
= xxx0b: May not initiate a new erase anywhere (erase nesting not permitted)
+ xx1xb: May not initiate a page program in the erase suspended sector size
+ x1xxb: May not initiate a read in the erase suspended sector size
+ 1xxxb: The erase and program restrictions in bits 5:4 are sufficient
= 1110b
5Fh
33h
Bits 3:0 = Prohibited Operations During Program Suspend
= xxx1b: May not initiate a new erase in the program suspended page size
+ xx0xb: May not initiate a new page program anywhere (program nesting not
permitted)
+ x1xxb: May not initiate a read in the program suspended page size
+ 1xxxb: The erase and program restrictions in bits 1:0 are sufficient
= 1101b
Binary Fields: 0-01-10011-0001-01-10011-0001-1-1110-1101
Nibble Format: 0011_0011_0001_0110_0110_0011_1110_1101
Hex Format: 33_16_63_ED
17
HM25Q128A
Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Sheet 4 of 5)
SFDP
SFDP
Dword
Name
Parameter
Relative Byte
Address
60h
Data
Description
JEDEC
Basic
7Ah
75h
7Ah
Bits 31:24 = Erase Suspend Instruction = 75h
Bits 23:16 = Erase Resume Instruction = 7Ah
Bits 15:8 = Program Suspend Instruction = 75h
Bits 7:0 = Program Resume Instruction = 7Ah
61h
Flash
Parameter
Dword-13
62h
63h
75h
64h
65h
66h
F7h
A2h
D5h
Bit 31 = Deep Power-Down Supported = 0
Bits 30:23 = Enter Deep Power-Down Instruction = B9h
Bits 22:15 = Exit Deep Power-Down Instruction = ABh
Bits 14:13 = Exit Deep Power-Down to next operation delay units = (00b: 128 ns,
01b: 1 μs,
10b: 8 μs, 11b: 64 μs) = 1 μs = 01b
JEDEC
Basic
Flash
Bits 12:8 = Exit Deep Power-Down to next operation delay count = 00010b, Exit
Deep Power-Down to next operation delay = (count+1)*units = 3*1 μs=3 μs
Bits 7:4 = RFU = 1111b
Parameter
Dword-14
Bit 3:2 = Status Register Polling Device Busy
67h
5Ch
= 01b: Legacy status polling supported = Use legacy polling by reading the Status
Register with 05h instruction and checking WIP bit[0] (0=ready; 1=busy).
Bits 1:0 = RFU = 11b
Binary Fields: 0-10111001-10101011-01-00010-1111-01-11
Nibble Format: 0101_1100_1101_0101_1010_0010_1111_0111
Hex Format: 5C_D5_A2_F7
68h
69h
6Ah
19h
F6h
DDh
Bits 31:24 = RFU = FFh
Bit 23 = Hold and WP Disable = set QE(bit 1 of SR2) high = 1b
Bits 22:20 = Quad Enable Requirements
= 101b: QE is bit 1 of the status register 2. Status register 1 is read using Read
Status instruction 05h. Status register 2 is read using instruction 35h. QE is set via
Write Status instruction 01h with two data bytes where bit 1 of the second byte is
one. It is cleared via Write Status with two data bytes where bit 1 of the second byte
is zero.
Bits 19:16 0-4-4 Mode Entry Method
= xxx1b: Mode Bits[7:0] = A5h Note: QE must be set prior to using this mode
+ x1xxb: Mode Bits[7:0] = Axh
+ 1xxxb: RFU
= 1101b
JEDEC
Basic
Flash
Parameter
Dword-15
Bits 15:10 0-4-4 Mode Exit Method
= xx_xxx1b: Mode Bits[7:0] = 00h will terminate this mode at the end of the current
read operation
+ xx_1xxxb: Input Fh (mode bit reset) on DQ0-DQ3 for 8 clocks. This will terminate
the mode prior to the next read operation.
+ 11_x1xx: RFU
6Bh
FFh
= 111101b
Bit 9 = 0-4-4 mode supported = 1
Bits 8:4 = 4-4-4 mode enable sequences = 0_0001b: set QE per QER description
above, then issue instruction 38h
Bits 3:0 = 4-4-4 mode disable sequences
= xxx1b: issue FFh instruction
+ 1xxxb: issue the Soft Reset 66/99 sequence
= 1001b
Binary Fields: 11111111-1-101-1101-111101-1-00001-1001
Nibble Format: 1111_1111-1101-1101-1111_0110_0001-1001
Hex Format: FF_DD_F6_19
18
HM25Q128A
Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Sheet 5 of 5)
SFDP
SFDP
Dword
Name
Parameter
Relative Byte
Address
6Ch
Data
Description
E8h
30h
C0h
Bits 31:24 = Enter 4-Byte Addressing
= xxxx_xxx1b:issue instruction B7 (preceding write enable not required
+ xx1x_xxxxb: Supports dedicated 4-byte address instruction set. Consult vendor
data sheet
6Dh
6Eh
for the instruction set definition or look for 4-byte Address Parameter Table.
+ 1xxx_xxxxb: Reserved
= 10000000b not supported
Bits 23:14 = Exit 4-byte Addressing
= xx_xxxx_xxx1b:issue instruction E9h to exit 4-byte address mode (Write enable
instruction
06h is not required)
+ xx_xx1x_xxxxb: Hardware reset
+ xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD)
+ xx_1xxx_xxxxb: Power cycle
+ x1_xxxx_xxxxb: Reserved
+ 1x_xxxx_xxxxb: Reserved
= 11_0000_0000b not supported
JEDEC
Basic
Flash
Parameter
Dword-16
Bits 13:8 = Soft Reset and Rescue Sequence Support
= x1_xxxxb: issue reset enable instruction 66h, then issue reset instruction 99h.
The reset enable, reset sequence may be issued on 1,2, or 4 wires depending on
the device operating mode
+ 1x_xxxxb: exit 0-4-4 mode is required prior to other reset sequences above if the
device may be operating in this mode.
6Fh
80h
= 11_0000b
Bit 7 = RFU = 1
Bits 6:0 = Volatile or Non-Volatile Register and Write Enable Instruction for Status
Register 1
= xxx_1xxxb: Non-Volatile/Volatile status register 1 powers-up to last written value
in the nonvolatile status register, use instruction 06h to enable write to non-volatile
status register. Volatile status register may be activated after power-up to override
the non-volatile status register, use instruction 50h to enable write and activate the
volatile status register.
+ x1x_xxxxb: Reserved
+ 1xx_xxxxb: Reserved
= 1101000b
Binary Fields: 10000000-1100000000-110000-1-1101000
Nibble Format: 1000_0000_1100_0000_0011_0000_1110_1000
Hex Format: 80_C0_30_E8
19
HM25Q128A
6. FUNCTION DESCRIPTION
6.1 SPI Operations
6.1.1 SPI Modes
The HM25Q128A
can be driven by an embedded microcontroller (bus master) in either of the two
following clocking modes.
Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0
Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data is always latched in on the rising edge of the CLK signal and the output
data is always available on the falling edge of the CLK clock signal.
The difference between the two modes is the clock polarity when the bus master is in standby mode and
not transferring any data.
CLK will stay at logic low state with CPOL = 0, CPHA = 0
CLK will stay at logic high state with CPOL = 1, CPHA = 1
Figure 6.1 SPI Modes
Timing diagrams throughout the rest of the document are generally shown as both mode 0 and 3 by
showing CLK as both high and low at the fall of CS#. In some cases a timing diagram may show only mode 0
with CLK low at the fall of CS#. In such case, mode 3 timing simply means clock is high at the fall of CS# so
no CLK rising edge set up or hold time to the falling edge of CS# is needed for mode 3.
CLK cycles are measured (counted) from one falling edge of CLK to the next falling edge of CLK. In
mode 0 the beginning of the first CLK cycle in a command is measured from the falling edge of CS# to the first
falling edge of CLK because CLK is already low at the beginning of a command.
6.1.2 Dual SPI Modes
The HM25Q128A supports Dual SPI Operation when using the Fast Read Dual Output (3Bh) and Fast
Dual I/O (BBh) instruction. These features allow data to be transferred from the device at twice the rate
possible with the standard SPI. These instructions are ideal for quickly downloading code to RAM upon
Power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP). When
using Dual SPI commands, the DI and DO pins become bidirectional I/O pins: IO0 and IO1.
6.1.3 Quad SPI Modes
The HM25Q128A supports Quad SPI operation when using the Fast Read Quad Output (6Bh), Fast Read
Quad I/O (EBh) instruction, Word Read Quad I/O(E7h), and Octal Word Read Quad I/O(E3h). These
instructions allow data to be transferred to or from the device four times the rate of ordinary Serial Flash. The
Quad Read instructions offer a significant improvement in continuous and random access transfer rates
20
HM25Q128A
allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI
instructions, the DI and DO pins become bidirectional IO0 and IO1, and the WP# and HOLD# / RESET# pins
become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in
Status Register-2 to be set.
6.1.4 QPI Function
The HM25Q128A supports Quad Peripheral Interface (QPI) operations when the device is switched from
Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI protocol
requires that the byte-long instruction code being shifted into the device only via DI pin in eight serial clocks.
The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial clocks are required.
This can significantly reduce the SPI instruction overhead and improve system performance in an XIP
environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at
any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are used to switch between these two
modes. Upon power-up or after a software reset using “Reset (99h)” instruction, the default state of the device
is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit (QE) in Status
Register-2 is required to be set. When using QPI instructions, the DI and DO pins become bidirectional IO0
and IO1, and the WP# and HOLD# / RESET# pins become IO2 and IO3 respectively.
6.1.5 Hold Function
For Standard SPI and Dual SPI operations, the HOLD# / RESET# (IO3) signal allows the device interface
operation to be paused while it is actively selected (when CS# is low). The Hold function may be useful in
cases where the SPI data and clock signals are shared with other devices. For example, if the page buffer is
only partially written when a priority interrupt requires use of the SPI bus, the Hold function can save the state
of the interface and the data in the buffer so programming command can resume where it left off once the bus
is available again. The Hold function is only available for standard SPI and Dual SPI operation, not during
Quad SPI.
To initiate a Hold condition, the device must be selected with CS# low. A Hold condition will activate on
the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the Hold
condition will activate after the next falling edge of CLK. The Hold condition will terminate on the rising edge of
the HOLD# signal if the CLK signal is already low. If the CLK is not already low the Hold condition will
terminate after the next falling edge of CLK. During a Hold condition, the Serial Data Output, (DO) or IO0 and
IO1, are high impedance and Serial Data Input, (DI) or IO0 and IO1, and Serial Clock (CLK) are ignored. The
Chip Select (CS#) signal should be kept active (low) for the full duration of the Hold operation to avoid
resetting the internal logic state of the device.
6.1.6 Software Reset & Hardware RESET# pin
The HM25Q128A can be reset to the initial power-on state by a software Reset sequence, either in SPI
mode or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) & Reset
(99h). If the command sequence is successfully accepted, the device will take approximately 10us (tRST) to
reset. No command will be accepted during the reset period.
HM25Q128A
can also be configured to utilize a hardware RESET# pin. The HRSW bit in the Status
Register-3 is the configuration bit for HOLD# pin function or RESET# pin function. When HRSW=0 (factory
default), the pin acts as a HOLD# pin as described above; when HRSW =1, the pin acts as a RESET# pin.
Drive the RESET# pin low for a minimum period of ~1us (tRESET*) will reset the device to its initial power-on
state. Any on-going Program/Erase operation will be interrupted and data corruption may happen. While
RESET# is low, the device will not accept any command input.
If QE bit is set to 1, the HOLD# or RESET# function will be disabled, the pin will become one of the four
data I/O pins.
Hardware RESET# pin has the highest priority among all the input signals. Drive RESET# low for a
minimum period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the status
of other SPI signals (CS#, CLK, DI, DO, WP# and/or HOLD#).
Note:
21
HM25Q128A
1. While a faster RESET# pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is recommended to
ensure reliable operation.
6.2. Status Register
The Read and Write Status Registers commands can be used to provide status and control of the flash
memory device.
Status Register-1 (SR1) and Status Register-2 (SR2) can be used to provide status on the availability of
the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad
SPI setting, Security Register lock status, and Erase / Program Suspend status.
SR1 and SR2 contain non-volatile bits in locations SR1[7:2] and SR2[6:3], SR2[1] that control sector
protection, OTP Register Protection, Status Register Protection, and Quad mode. Bits located in SR2[7],
SR1[1], and SR1[0] are read only volatile bits for suspend, write enable, and busy status. These are updated
by the memory control logic. The SR1[1] write enable bit is set only by the Write Enable (06h) command and
cleared by the memory control logic when an embedded operation is completed.
Write access to the non-volatile Status Register bits is controlled by the state of the non-volatile Status
Register Protect bits SR1[7] and SR2[0] (SRP0, SRP1), the Write Enable command (06h) preceding a Write
Status Registers command, and while Quad mode is not enabled, the WP# pin.
A volatile version of bits SR2[6], SR2[1], and SR1[7:2] that control sector protection and Quad Mode is
used to control the behavior of these features after power up. During power up or software reset, these
volatile bits are loaded from the non-volatile version of the Status Register bits. The Write Enable for Volatile
Status Register (50h) command can be used to write these volatile bits when the command is followed by a
Write Status Registers (01h/31h/11h) command. This gives more flexibility to change the system configuration
and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting
the endurance of the Status Register non-volatile bits.
Write access to the volatile SR1, SR2 and SR3 Status Register bits is controlled by the state of the
non-volatile Status Register Protect bits SR1[7] and SR2[0] (SRP0, SRP1), the Write Enable for Volatile
Status Register command (50h) preceding a Write Status Registers command, and the WP# pin while Quad
mode is not enabled.
Status Register-3 (SR3) is used to configure and provide status on the variable HOLD# or RESET#
function, Output Driver Strength, High Frequency Enable Bit, Write Protect Selection and read latency.
Write access to the volatile SR3 Status Register bits is controlled by Write Enable for Volatile Status
Register command (50h) preceding a Write Status Register command.
22
HM25Q128A
Table 6.1 Status Register-1 (SR1)
Default
Bits
Field
Function
Type
State
Description
0 = WP# input has no effect or Power Supply
Lock Down mode
Status Register
Protect 0
7
SRP0
0
1
= WP# input can protect the Status
Register or OTP Lock Down.
Sector / Block
Protect
0 = BP2-BP0 protect 64-kB blocks
1 = BP2-BP0 protect 4-kB sectors
6
5
SEC
TB
0
0
Non-volatile
and Volatile
versions
Top / Bottom
protect
0 = BP2-BP0 protect from the Top down
1 = BP2-BP0 protect from the Bottom up
4
3
2
BP2
BP1
BP0
0
0
0
Block Protect
Bits
000b = No protection
0
= Not Write Enabled, no embedded
Write Enable
Latch
Volatile,
Read only
operation can start
1 = Write Enabled, embedded operation can
start
1
0
WEL
0
0
Embedded
Operation
Status
0 = Not Busy, no embedded operation in
progress
1 = Busy, embedded operation in progress
Volatile,
Read only
BUSY
Table 6.2 Status Register-2 (SR2)
Default
Bits
Field
Function
Type
State
Description
Volatile, Read
Only
0 = Erase / Program not suspended
1 = Erase / Program suspended
7
6
SUS
CMP
Suspend Status
0
0
Complement
Protect
Non-volatile and
Volatile versions
0 = Normal Protection Map
1 = Complementary Protection Map
5
4
3
LB3
LB2
LB1
0
0
0
OTP Lock Bits 3:0 for Security Registers
3:0
0 = Security Register not protected
1 = Security Register protected
Security Register
Lock Bits
OTP
Reserv
ed
2
0
0 = Quad Mode Not Enabled, the WP# pin
and HOLD# / RESET# are enabled
1
QE
Quad Enable
0
1 = Quad Mode Enabled, the IO2 and IO3
pins are enabled, and WP# and HOLD# /
RESET# functions are disabled
Non-volatile and
Volatile versions
0 = SRP1 selects whether WP# input has
effect on protection of the status register
1 = SRP1 selects Power Supply Lock Down
or OTP Lock Down mode
Status Register
Protect 1
0
SRP1
0
Note:
1. Reserved bit should be considered don't care for read.
23
HM25Q128A
Table 6.3 Status Register-3 (SR3)
Bits
Field
Function
HOLD# or
RESET#
function
Type
Default State
Description
When HRSW=0, the pin acts as HOLD#; when
HRSW=1, the pin acts as RESET#. HRSW
functions are only available when QE=0.
7
HRSW
0
6
5
DRV1
DRV0
0
0
The DRV1 & DRV0 bits are used to determine
the output driver strength for the Read
operations.
Non-volatile
and Volatile
versions
Output Driver
Strength
High
Frequency
Enable Bit
0= High Frequency Mode Disabled
1 = High Frequency Mode Enabled
4
3
HFQ
0
0
Reserve
When WPS=0, the device will use the
combination of CMP, SEC, TB, BP[2:0] bits to
protect a specific area of the memory array.
When WPS=1, the device will utilize the
Individual Block Locks to protect any individual
sector or blocks.
Non-volatile
and Volatile
versions
Write Protect
Selection
2
WPS
0
Latency
Control
(LC)
Variable SPI
Read Latency
Control
Defines the number of read latency cycles in
Fast Read, Dual Out, Quad Out, Dual IO, and
Quad IO commands. See details in Table 6.5.
1
0
0
0
Note:
1. LC[1:0] only controls SPI read latency and will be reset to default while switching from QPI to SPI. QPI read latency is set by C0
instruction.
6.2.1 BUSY
BUSY is a read only bit in the status register (SR1[0]) which is set to a “1” state when the device is
executing a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction.
During this time the device will ignore further instructions except for the Read Status Register instruction (see
tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status register instruction has
completed, the BUSY bit will be cleared to a “0” state indicating the device is ready for further instructions.
6.2.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (SR1[1]) which is set to a 1 after
executing a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is written disabled.
A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.
6.2.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read / write bits in the Status Register (SR1[4:2]) that
provide Write Protection control and status. Block Protect bits can be set using the Write Status Registers
Command (see tW in Section 8.5). All, none or a portion of the memory array can be protected from Program
and Erase commands (see Section 6.4.2, Block Protection Maps). The factory default setting for the Block
Protection Bits is 0 (none of the array is protected.)
6.2.4 Top / Bottom Block Protect (TB)
The non-volatile Top / Bottom bit (TB SR1[5]) controls whether the Block Protect Bits (BP2, BP1, BP0)
protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in Section 6.4.2, Block Protection
Maps. The factory default setting is TB=0. The TB bit can be set with the Write Status Registers Command
depending on the state of the SRP0, SRP1 and WEL bits.
24
HM25Q128A
6.2.5 Sector / Block Protect (SEC)
The non-volatile Sector / Block Protect bit (SEC SR1[6]) controls if the Block Protect Bits (BP2, BP1, BP0)
protect either 4-kB Sectors (SEC=1) or 64-kB Blocks (SEC=0) of the array as shown in Section 6.4.2, Block
Protection Maps. The default setting is SEC=0.
6.2.6 Complement Protect (CMP)
The Complement Protect bit (CMP SR2[6]) is a non-volatile read / write bit in the Status Register (SR2[6]).
It is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array
protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be
reversed. For instance, when CMP=0, a top 4-kB sector can be protected while the rest of the array is not;
when CMP=1, the top 4-kB sector will become unprotected while the rest of the array become read-only.
Refer to Section 6.3.2, Block Protection Maps for details. The default setting is CMP=0.
6.2.7 The Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read / write bits in the Status Register
(SR2[0] and SR1[7]). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down, or one time programmable (OTP) protection.
Table 6.4 Status Register Protect
SRP1
SRP0
WP#
Status Register
Description
WP# pin has no control. SR1 ,SR2 and SR3 can be written to
after a Write Enable command, WEL=1. [Factory Default]
0
0
X
Software Protection
When WP# pin is low the SR1, SR2 and SR3 are locked and
cannot be written.
0
1
1
0
1
0
1
Hardware Protected
Hardware
Unprotected
When WP# pin is high SR1 ,SR2 and SR3 are unlocked and
can be written to after a Write Enable command, WEL=1.
0
Power Supply Lock
Down
SR1 ,SR2 and SR3 are protected and cannot be written to again
until the next power-down, power-up cycle. (1)
1
1
X
X
SR1 ,SR2 and SR3 are permanently protected and cannot be
written.
One Time Program (2)
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up, or Software Reset cycle will change SRP1, SRP0 to (0, 0) state.
2. The One-Time Program feature is available upon special order. Contact Zbit for details.
3. Busy, WEL, and SUS (SR1[1:0] and SR2[7]) are volatile read only status bits that are never affected by the Write Status
Registers command.
4. The non-volatile version of CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR2[6,1,0] and SR1[6:2]) bits and the OTP
LB3-LB1 bits are not writable when protected by the SRP bits and WP# as shown in the table. The non-volatile version of
these Status Register bits is selected for writing when the Write Enable (06h) command precedes the Write Status Registers
(01h) command.
5. The volatile version of HRSW, DRV1, DRV0, HFQ, WPS, CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR3[7:4,2],
SR2[6,1,0] and SR1[6:2]) bits are not writable when protected by the SRP bits and WP# as shown in the table. The volatile
version of these Status Register bits is selected for writing when the Write Enable for volatile Status Register (50h)
command precedes the Write Status Registers (01h) command. There is no volatile version of the LB3-LB1 bits and these
bits are not affected by a volatile Write Status Registers command.
6.2.8 Erase / Program Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (SR2[7]) that is set to 1 after executing an
Erase / Program Suspend (75h) command. The SUS status bit is cleared to 0 by Erase / Program Resume
(7Ah) command as well as a power-down, power-up cycle.
6.2.9 Security Register Lock Bits (LB3, LB2, LB1)
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (SR2[5:3]) that provide the write protect control and status to the Security Registers. The default
state of LB[3:1] is 0, Security Registers 1 to 3 are unlocked. LB[3:1] can be set to 1 individually using the Write
25
HM25Q128A
Status Registers command. LB[3:1] are One Time Programmable (OTP), once it’s set to 1, the corresponding
256-byte Security Register will become read-only permanently.
6.2.10 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read / write bit in the Status Register (SR2[1]) that allows
Quad SPI operation. When the QE bit is set to a 0 state (factory default), the WP# pin and HOLD# / RESET#
are enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and WP# and HOLD# /
RESET# functions are disabled.
Note: If the WP# or HOLD# / RESET# pins are tied directly to the power supply or ground during standard SPI or Dual SPI operation, the
QE bit should never be set to a 1.
6.2.11 HOLD# or RESET# Pin Function (HRSW)
The HRSW bit is used to determine whether HOLD# or RESET# function should be implemented on the
hardware pin for 8-pin packages. When HRSW=0, the pin acts as #HOLD; when HRSW=1, the pin acts as
RESET#. However, HOLD# or RESET# functions are only available when QE=0. If QE is set to 1, the HOLD#
and RESET# functions are disabled, the pin acts as a dedicated data I/O pin.
6.2.12 Output Driver Strength (DRV1, DRV0)
The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0
Driver Strength
50%
25%
75%(default)
100%
0, 0
0, 1
1, 0
1, 1
6.2.13 High Frequency Enable Bit (HFQ)
The HFQ bit is used to determine whether the device is in Quad High Frequency Mode. When HFQ bit
sets to 1, it means the device is in Quad High Frequency Mode, when HFQ bit sets 0 (default), it means the
device is not in Quad High Frequency Mode. This Mode allows pre-charge of internal charge pump, so the
voltages required for accessing the flash memory array are readily available for Quad read. After the HFQ is
executed, the device will maintain a slightly higher standby current (ICC8) than standard SPI operation.
6.2.14 Write Protect Selection (WPS)
The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will
use the combination of CMP, SEC, TB, BP[2:0] bits to protect a specific area of the memory array. When
WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The default
value for all Individual Block Lock bits is 1 upon device power on or after reset.
6.2.15 Latency Control (LC)
Status Register-3 provides bits (SR3[1:0]) to select the number of read latency cycles used in each Fast
Read command(only in SPI mode). The Read Data command is not affected by the latency code. The binary
value of this field selects from 2,4,6 latency cycles. The default is 0 to provide backward compatibility to
legacy devices. The Latency Control bits may be set to select a number of read cycles optimized for the
frequency in use. If the number of latency cycles is not sufficient for the operating frequency, invalid data will
be read.
26
HM25Q128A
Table 6.5 Latency Cycles Versus Frequency for -40°C to 85°C/105°C at 2.3V to 3.6V
Read Command Maximum Frequency (MHz)
Latency Control
Dual
Output
Quad
Output
Word Read
Quad I/O
104
(2 mode, 2
dummy)
104
Fast Read
Dual I/O
Quad I/O
104
(4 mode, 0
dummy)
104
104
(2 mode, 4
dummy)
75
00
104
(8 dummy)
104
(8 dummy)
104
(8 dummy)
(legacy read latency)
01(2 dummy)
10(4 dummy)
11(6 dummy)
104
104
104
104
104
104
90
104
104
104
104
104
104
104
104
Notes:
1. The default dummy referred in this document is the dummy configuration when LC[1:0]=0.
2.Value guaranteed by design and/or characterization, not 100% tested in production.
6.3. Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the ZB25VQ128
provides the following data protection mechanisms:
6.3.1 Write Protect Features
Device resets when VCC is below threshold
Time delay write disable after Power-Up
Write enable / disable commands and automatic write disable after erase or program
Command length protection
- All commands that Write, Program or Erase must complete on a byte boundary (CS# driven high after
a full 8 bits have been clocked) otherwise the command will be ignored.
Software and Hardware write protection using Status Register control
- WP# input protection
- Lock Down write protection until next power-up or Software Reset
- One-Time Program (OTP) write protection
Additional Individual Block/Sector Locks for array protection
Write Protection using the Deep Power-Down command
Upon power-up or at power-down, the HM25Q128A will maintain a reset condition while VCC is below the
threshold value of VWI, (see Figure 8.1). While reset, all operations are disabled and no commands are
recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related
commands are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program,
Sector Erase, Block Erase, Chip Erase and the Write Status Registers commands. Note that the chip select
pin (CS#) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached.
If needed a pull-up resistor on CS# can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable command must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Registers command will be accepted. After completing a
program, erase or write command the Write Enable Latch (WEL) is automatically cleared to a write-disabled
state of 0.
Software controlled main flash array write protection is facilitated using the Write Status Registers
command to write the Status Register (SR1,SR2) and Block Protect (SEC, TB, BP2, BP1 and BP0) bits.
27
HM25Q128A
The BP method allows a portion as small as 4-kB sector or the entire memory array to be configured as
read only. Used in conjunction with the Write Protect (WP#) pin, changes to the Status Register can be
enabled or disabled under hardware control. See the Table 6.4 for further information.
The HM25Q128A
also provides another Write Protect method using the Individual Block Locks. Each
64KB block (except the top and bottom blocks, total of 126 blocks) and each 4KB sector within the top/bottom
blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is 0, the
corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or Program
commands issued to the corresponding sector or block will be ignored. When the device is powered on, all
Individual Block Lock bits will be 1, so the entire memory array is protected from Erase/Program. An
“Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector or block.
Additionally, the Deep Power-Down (DPD) command offers an alternative means of data protection as all
commands are ignored during the DPD state, except for the Release from Deep-Power-Down (RES ABh)
command. Thus, preventing any program or erase during the DPD state.
28
HM25Q128A
6.3.2 Block Protection Maps
Table 6.6 HM25Q128A Block Protection (WPS = 0,CMP = 0)
Status Register (1)
ZB25VQ128(128 Mbit) Block Protection (CMP=0) (2)
Protected
Density
Protected
Portion
SEC
X
0
TB
BP2
0
BP1
BP0
0
Protected Block(s)
None
Protected Addresses
None
X
0
0
0
0
0
0
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
None
256KB
512 kB
1 MB
2 MB
4 MB
8 MB
256 kB
512 kB
1 MB
2 MB
4 MB
8 MB
16 MB
4 kB
None
0
1
252 thru 255
248 thru 255
240 thru 255
224 thru 255
192 thru 255
128 thru 255
0 thru 3
0 thru 7
0 thru 15
0 thru 31
0 thru 63
0 thru 127
0 thru 255
255
FC0000h – FFFFFFh
F80000h – FFFFFFh
F00000h – FFFFFFh
E00000h – FFFFFFh
C00000h – FFFFFFh
800000h – FFFFFFh
000000h – 03FFFFh
000000h – 07FFFFh
000000h – 0FFFFFh
000000h – 1FFFFFh
000000h – 3FFFFFh
000000h – 7FFFFFh
000000h – FFFFFFh
FFF000h – FFFFFFh
FFE000h – FFFFFFh
FFC000h – FFFFFFh
FF8000h – FFFFFFh
000000h – 000FFFh
000000h – 001FFFh
000000h – 003FFFh
000000h – 007FFFh
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
All
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
X
1
1
1
Upper
1/4096
Upper
1/2048
Upper
1/1024
Upper
1/512
Lower
1/4096
Lower
1/2048
Lower
1/1024
Lower
1/512
0
1
1
0
0
255
8 kB
1
0
1
255
16 kB
32 kB
4 kB
1
1
X
1
255
1
0
0
1
0
0
0
8 kB
1
0
1
0
16 kB
32 kB
1
1
X
0
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
29
HM25Q128A
Table 6.7 HM25Q128A Block Protection (WPS = 0,CMP = 1)
Status Register (1)
ZB25VQ128(128 Mbit) Block Protection (CMP=1) (2)
Protected
Protected
Portion
SEC
X
0
TB
BP2
0
BP1
BP0
0
Protected Block(s)
Protected Addresses
000000h – FFFFFFh
000000h – FBFFFFh
000000h – F7FFFFh
000000h – EFFFFFh
000000h – DFFFFFh
000000h – BFFFFFh
000000h – 7FFFFFh
040000h – FFFFFFh
080000h – FFFFFFh
100000h – FFFFFFh
200000h – FFFFFFh
400000h – FFFFFFh
800000h – FFFFFFh
None
Density
X
0
0
0
0
0
0
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
0 thru 255
0 thru 251
0 thru 247
0 thru 239
0 thru 233
0 thru 191
0 thru 127
4 thru 255
8 thru 255
16 thru 255
32 thru 255
64 thru 255
128 thru 255
None
16 MB
All
Lower
63/64
Lower
31/32
Lower
15/16
0
1
16,128 kB
15,872 kB
15 MB
0
0
0
0
0
1
0
1
0
14 MB
Lower 7/8
Lower 3/4
Lower 1/2
0
1
1
12 MB
0
1
0
8 MB
Upper
63/64
Upper
31/32
Upper
15/16
0
0
1
16,128 kB
15,872 kB
15 MB
0
0
0
0
0
1
0
1
0
14 MB
Upper 7/8
Upper 3/4
Upper 1/2
None
0
1
1
12 MB
0
1
0
8 MB
X
1
1
1
None
Lower
4095/4096
Lower
2047/2048
Lower
1023/1024
Lower
511/512
0
1
0 thru 255
0 thru 255
0 thru 255
0 thru 255
0 thru 255
0 thru 255
0 thru 255
0 thru 255
000000h – FFEFFFh
000000h – FFDFFFh
000000h – FFBFFFh
000000h – FF7FFFh
001000h – 1FFFFFh
002000h – 1FFFFFh
004000h – 1FFFFFh
008000h – 1FFFFFh
16,380 KB
16,376 kB
16,368 kB
16,352 kB
16,380 KB
16,376 kB
16,368 kB
16,352 kB
1
0
0
1
0
1
1
1
X
1
Upper
4095/4096
Upper
2047/2048
Upper
1023/1024
Upper
1
0
1
0
0
1
0
1
1
1
X
511/512
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
30
HM25Q128A
6.3.3 Individual Block Memory Protection (WPS=1)
Figure 6.2 Individual Block/Sector Locks
Notes:
1. Individual Block/Sector protection is only valid when WPS=1.
2. All individual block/sector lock bits are set to 1 by default after power up, all memory array is protected.
31
HM25Q128A
6.4. Page Program
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a
Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program
cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to
be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the
same page of memory.
6.5. Sector Erase, Block Erase and Chip Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the
bytes of memory need to be erased to all 1s (FFh). This can be achieved a sector at a time, using the Sector
Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or throughout the entire
memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle (of duration tSE tBE or tCE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
6.6. Polling during a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE or
CE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBE or tCE). The Write In Progress (WIP)
bit is provided in the Status Register so that the application program can monitor its value, polling it to
establish when the previous Write cycle, Program cycle or Erase cycle is complete.
6.7. Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select
(CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have
completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The
device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode
(DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode
until another specific instruction (the Release from Deep Power-down Mode and Read Device ID (RDI)
instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as
an extra software protection mechanism, when the device is not in active use, to protect the device from
inadvertent Program or Erase instructions.
32
HM25Q128A
7. INSTRUCTIONS
The instruction set of the HM25Q128A consists of forty basic instructions that are fully controlled through
the SPI bus. Instructions are initiated with the falling edge of Chip Select (CS#). The first byte of data clocked
into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with
most significant bit (MSB) first.
The QPI instruction set of the HM25Q128A consists of 32 basic instructions that are fully controlled
through the SPI bus (see Instruction Set Table 7.5). Instructions are initiated with the falling edge of Chip
Select (CS#). The first byte of data clocked through IO[3:0] pins provides the instruction code. Data on all four
IO pins are sampled on the rising edge of clock with most significant bit (MSB) first. All QPI instructions,
addresses, data and dummy bytes are using all four IO pins to transfer every byte of data with every two serial
clocks (CLK).
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising
edge of edge CS#. Clock relative timing diagrams for each instruction are included in figures 7.1 through 7.47
All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or
Erase must complete on a byte boundary (CS driven high after a full 8-bits have been clocked) otherwise the
instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while
the memory is being programmed or erased, or when the Status Register is being written, all instructions
except for Read Status Register and Erase/Program Suspend will be ignored until the program or erase cycle
completes.
33
HM25Q128A
Table 7.1 Command Set (Configuration, Status, Erase, Program Instructions (1), SPI Mode)
BYTE 1
(Instruction)
Command Name
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
Read Status Register-1
Read Status Register-2
Read Status Register-3
Write Enable
05h
35h
SR1[7:0](2)
SR2[7:0](2)
SR3[7:0](2)
15h/33h
06h
Write Enable for Volatile
Status Register
50h
Write Disable
04h
01h
Write Status Registers-1
Write Status Registers-2
Write Status Registers-3
Set Burst with Wrap
Global Block Lock
Global Block Unlock
Read Block Lock
SR1[7:0](5)
SR2[7:0]
SR3[7:0]
xxh
31h
11h
77h
xxh
xxh
W[7:0](3)
L7—L0
7Eh
98h
3Dh
36h
A23—A16
A23—A16
A23—A16
A23—A16
A23—A16
A23—A16
A23—A16
A23—A16
A15—A8
A15—A8
A15—A8
A15—A8
A15—A8
A15—A8
A15—A8
A15—A8
A7—A0
A7—A0
A7—A0
A7—A0
A7—A0
A7—A0
A7—A0
A7—A0
Individual Block Lock
Individual Block Unlock
Page Program
39h
02h
D7—D0
Quad Page Program
Sector Erase (4 KB)
Block Erase (32 KB)
Block Erase (64 KB)
Chip Erase
32h
D7—D0(4)
20h
52h
D8h
C7h/60h
Erase/Program
Suspend
75h
Erase/Program Resume
Enter QPI Mode
Enable Reset
7Ah
38h
66h
99h
Reset Device
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data
being read from the device on the DO pin.
2. Status Register contents will repeat continuously until CS# terminates the command.
3. Set Burst with Wrap Input format.
IO0 = x, x, x, x, x, x, W4, x]
IO1 = x, x, x, x, x, x, W5, x]
IO2 = x, x, x, x, x, x, W6 x]
IO3 = x, x, x, x, x, x, x,x
4. Quad Page Program Input Data:
IO0 =(D4,D0,...)
IO1 = ( D5,D1,...)
IO2 = ( D6,D2,...)
IO3 =( D7,D3,...)
5. The 01h command could continuously write up to three bytes to registers SR1, SR2, SR3.
34
HM25Q128A
Table 7.2 Command Set (Read Instructions (1), SPI Mode)
BYTE 1
(Instruction)
Command Name
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
03h
0Bh
A23—A16
A23—A16
A15—A8
A15—A8
A7—A0
(D7—D0,…)
dummy
Read Data
Fast Read
A7—A0
A7—A0
(D7—D0,…)
Fast Read Dual
Output
3Bh
6Bh
A23—A16
A23—A16
A15—A8
A15—A8
dummy
dummy
(D7—D0,…)(1)
Fast Read Quad
Output
A7—A0
(D7—D0,…)(3)
A7—A0,M7
—M0(2)
Fast Read Dual I/O
BBh
EBh
E7H
E3h
A23—A8(2)
(D7—D0,…)(1)
Fast Read Quad
I/O
A23—A0,M7
—M0(4)
(x,x,x,x,D7—
D0,...)
(D7—D0,…)(3)
(D7—D0,…)(3)
(D7—D0,…)(3)
QUAD I/O WORD
FAST READ(5)
A23—A0,M7
—M0(4)
(x,x,D7—D0,
...)
Octal Word Read
Quad I/O(5)
A23—A0,M7
—M0(4)
(D7—D0,…)(
3)
Notes:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. For Word Read Quad I/O, the lowest address bit must be 0. (A0 = 0),and for Octal Word Read Quad I/O, the lowest four
address bits must be 0. (A3, A2, A1, A0 = 0)
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HM25Q128A
Table 7.3 Command Set (Read ID, OTP Instructions (1), SPI Mode)
Command
Name
BYTE 1
(Instruction)
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
Deep
Power-down
B9h
ABh
90h
92h
Release
Power down /
Device ID
dummy
dummy
dummy
dummy
dummy
00h
Device ID(1)
Manufacturer/
Device ID(2)
Manufacturer
Device ID
Manufacturer/
Device ID by
Dual I/O
A23—A8
A7—A0,M[7:0]
(MF[7:0],ID[7:0])
Manufacturer/
Device ID by
Quad I/O
94h
A23—A0,M[7:0] XXXX,(MF[7:0],ID[7:0]) (MF[7:0],ID[7:0]...)
9Fh
5Ah
Manufacturer
00h
Memory Type
00h
Capacity
A7—A0
JEDEC ID
Read SFDP
Register
dummy
dummy
(D7—D0,…)
(D7—D0,…)
Read
Security
Registers(3)
48h
44h
A23—A16
A23—A16
A15—A8
A15—A8
A7—A0
A7—A0
Erase
Security
Registers(3)
Program
Security
42h
4Bh
A23—A16
dummy
A15—A8
dummy
A7—A0
dummy
D7—D0,…
dummy
Registers(3)
Read Unique
ID
(ID63-ID0)
Notes:
1. The Device ID will repeat continuously until CS# terminates the command.
2. See Section 7.5.3, Legacy Device Identification Commands on page 56 for Device ID information. The 90h instruction is followed
by an address. Address = 0 selects Manufacturer ID as the first returned data as shown in the table. Address = 1 selects Device ID as
the first returned data followed by Manufacturer ID.
3. Security Register Address:
Security Register 0: A23-16 = 00h; A15-8 = 00h; A7-0 = byte address
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
Table 7.4(1) Manufacturer and Device Identification(SPI and QPI Mode)
OP Code
Data1
Data2
Data3
Device ID = 17h
-
ABh
-
Device ID = 17h
Memory Type =40h
Memory Type =60h
90h/92h/94h
9Fh(SPI)
9Fh(QPI)
Manufacturer ID = 5E
Manufacturer ID = 5E
Manufacturer ID = 5E
-
Capacity = 18h
Capacity = 18h
Notes:
(1)Please contact sales for more information
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HM25Q128A
Table 7.5 Command Set (QPI Instructions (1), QPI Mode)
BYTE 1
(Instruction)
Command Name
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
Clock Number
(0, 1)
06h
(2, 3)
(4, 5)
(6, 7)
(8, 9)
(10, 11)
Write Enable
Write Enable for Volatile
Status Register
50h
Write Disable
04h
05h
Read Status Register-1
Write Status Register-1(3)
Read Status Register-2
Write Status Register-2
Read Status Register-3
Write Status Register-3
Global Block Lock
Global Block Unlock
Read Block Lock
(S7-S0)(1)
(S7-S0)(3)
01h
35h
(S15-S8)(1)
(S15-S8)
31h
15h/33h
11h
(S23-S16)(1)
(S23-S16)
7Eh
98h
3Dh
36h
A23—A16
A23—A16
A23—A16
A15—A8
A15—A8
A15—A8
A7—A0
A7—A0
A7—A0
L7—L0
Individual Block Lock
Individual Block Unlock
Chip Erase
39h
C7h/60h
75h
Erase / Program Suspend
Erase / Program Resume
Deep Power-down
Set Read Parameters
Release Power down / ID
Manufacturer/Device ID
JEDEC ID
7Ah
B9h
C0h
ABh
90h
P7-P0
Dummy
Dummy
Dummy
Dummy
00h
(ID7-ID0)(1)
(MF7-MF0)
Dummy
(ID7-ID0)
9Fh
FFh
66h
(MF7-MF0)
(ID15-ID8)
(ID7-ID0)
Exit QPI Mode
Enable Reset
Reset Device
99h
Page Program
02h
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0(4)
D7-D0(2)
Sector Erase (4KB)
Block Erase (32KB)
Block Erase (64KB)
Fast Read
20h
52h
D8h
0Bh
0Ch
EBh
Dummy(5)
Dummy(5)
M7-M0(5)
D7-D0
D7-D0
D7-D0
Burst Read with Wrap(6)
Fast Read Quad I/O
Notes:
1. The Status Register contents and Device ID will repeat continuously until CS# terminates the instruction.
2. At least one byte of data input is required for Page Program, Quad Page Program and Program Security Registers, up to 256 bytes
of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and
overwrite previously sent data.
3. Write Status Register-1 (01h) can also be used to program Status Register-1&2&3, see section 7.1.5.
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HM25Q128A
4. Quad SPI data input/output format:
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
5. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read with Wrap is controlled by read
parameter P7 – P4.
6. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 – P0.
38
HM25Q128A
7.1 Configuration and Status Commands
7.1.1 Read Status Register (05h/35h/15h)
The Read Status Register commands allow the 8-bit Status Registers to be read. The command is
entered by driving CS# low and shifting the instruction code “05h” for Status Register-1, “35h” for Status
Register-2, “15h” for Status Register-3 into the DI pin on the rising edge of CLK. The Status Register bits are
then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 7.1. The Status Register bits are shown in Section 6.2, Status Registers.
The Read Status Register-1 (05h) command may be used at any time, even during a Program, Erase, or
Write Status Registers cycle. This allows the BUSY status bit to be checked to determine when the operation
is complete and if the device can accept another command.
Figure 7.1a Read Status Register Instruction(SPI Mode)
Figure 7.1b Read Status Register Instruction(QPI Mode)
7.1.2 Write Enable (06h)
The Write Enable instruction (Figure 7.2) sets the Write Enable Latch (WEL) bit in the Status Register to
a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write
Status Register instruction. The Write Enable instruction is entered by driving CS# low, shifting the instruction
code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving CS# high.
39
HM25Q128A
Figure 7.2 Write Enable Instruction(SPI or QPI Mode)
7.1.3 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 6.2 can also be written to as volatile bits. This
gives more flexibility to change the system configuration and memory protection schemes quickly without
waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register
non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status
Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable for
Volatile Status Register instruction (Figure 7.3) will not set the Write Enable Latch (WEL)bit, it is only valid for
the Write Status Register instruction to change the volatile Status Register bit values.
Figure 7.3 Write Enable for Volatile Status Register Instruction(SPI or QPI Mode)
7.1.4 Write Disable (04h)
The Write Disable instruction (Figure 7.4) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0. The Write Disable instruction is entered by driving CS# low, shifting the instruction code “04h” into the
DI pin and then driving CS# high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase
instructions.
Figure 7.4 Write Disable Instruction(SPI or QPI Mode)
7.1.5 Write Status Register (01h/31h/11h)
The Write Status Registers command allows the Status Registers to be written. Only non-volatile Status
Register bits SRP0, SEC, TB, BP2, BP1, BP0 (SR1[7:2]) CMP, LB3, LB2, LB1, QE, SRP1 (SR2[6:0]), and
HRSW, DRV1, DRV0, HFQ, WPS, LC[1:0] (SR3[7:4,2:0])can be written. All other Status Register bit locations
are read-only and will not be affected by the Write Status Registers command. LB[3:0] are non-volatile OTP
bits; once each is set to 1, it cannot be cleared to 0. The Status Register bits are shown in Section 6.2, Status
Registers. Any reserved bits should only be written to their default value.
To write non-volatile Status Register bits, a standard Write Enable (06h) command must previously have
40
HM25Q128A
been executed for the device to accept the Write Status Registers Command (Status Register bit WEL must
equal 1). Once write enabled, the command is entered by driving CS# low, sending the instruction code “01h”,
and then writing the Status Register data bytes as illustrated in Figure 7.5.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) command must
have been executed prior to the Write Status Registers command (Status Register bit WEL remains 0).
However, SRP1 and LB3, LB2, LB1 cannot be changed because of the OTP protection for these bits. Upon
power-off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will
be restored when power on again.
To complete the Write Status Registers command, the CS# pin must be driven high after the eighth bit of
a data value is clocked in (CS# must be driven high on an 8-bit boundary). If this is not done the Write Status
Registers command will not be executed.
The Write Status Register instruction allows the Status Register to be written. A Write Enable instruction
must previously have been executed for the device to accept the Write Status Register Instruction (Status
Register bit WEL must equal to 1). Once write enabled, the instruction is entered by driving CS# low, sending
the instruction code “01h”, and then writing the status register data byte as illustrated in Figure 7.5.
During non-volatile Status Register write operation (06h combined with 01h/31h), after CS# is driven high,
the self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics).
While the Write Status Register cycle is in progress, the Read Status Register instruction may still be
accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and
a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register
cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
During volatile Status Register write operation (50h combined with 01h/31h/11h), after CS# is driven high,
the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
If CS# is driven high after the eighth clock, the Write Status Register-1 (01h) instruction will only program
the Status Register-1, the Status Register-2 will not be affected.
gure 7.5a Write Status Register Instruction(SPI Mode)
Figure 7.5b Write Status Register Instruction(QPI Mode)
7.2 Program and Erase Commands
41
HM25Q128A
7.2.1 Page Program (PP) (02h)
The Page Program instruction allows up to 256 bytes of data to be programmed at previously erased to
all 1s (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the
Page Program Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the
CS# pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least one
data byte, into the DI pin. The CS# pin must be held low for the entire length of the instruction while data is
being sent to the device. The Page Program instruction sequence is shown in Figure 7.6.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page
length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial
page) can be programmed without having any effect on other bytes within the same page. One condition to
perform a partial page program is that the number of clocks cannot exceed the remaining page length. If more
than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite
previously sent data.
As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Page Program instruction will not be executed. After CS# is
driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still
be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and
becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the
Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The
Page Program instruction will not be executed if the addressed page is protected by the Block Protect (TB,
SEC, BP2, BP1, and BP0) bits (see Status Register Memory Protection table).
Figure 7.6a Page Program Instruction (SPI Mode)
Figure 7.6b Page Program Instruction(QPI Mode)
7.2.2 Quad Input Page Program (32h)
The Quad Input Page Program instruction allows up to 256 byte of data to be programmed at previously
erased (FFh) memory locations using four pins: IO0, IO1, IO2 and IO3. The Quad Input Page Program can
improved performance for PROM Programmer and applications that have slow clock speeds<5MHz. Systems
with faster clock speed will not realize much benefit for the Quad Input Page Program instruction since the
inherent page program time is much greater than the time it take to clock-in the data.
To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write Enable
42
HM25Q128A
instruction must be executed before the device will accept the Quad Page Program instruction (Status
Register-1, WEL=1). The instruction is initiated by driving the CS# pin low then shifting the instruction code
"32h" followed by a 24-bit address (A23-0) and at least one data byte, into the IO pins. The CS# pin must be
held low for entire length of the instruction while data is being sent to the device. All other functions of Quad
Page Program are identical to standard Page Program. The Quad Page Program instructions sequence is
shown in Figure 7.7.
Figure 7.7 Quad Page Program Instruction
7.2.3 Sector Erase (SE) (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and
shifting the instruction code “20h” followed a 24-bit sector address (A23-A0). The Sector Erase instruction
sequence is shown in Figure 7.8.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Sector Erase instruction will not be executed. After CS# is driven high, the self-timed Sector Erase
instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase cycle is
in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit.
The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device
is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the
addressed page is protected by the Block Protect (TB, SEC, BP2, BP1, and BP0) bits (see Status Register
Memory Protection table).
Figure 7.8a Sector Erase Instruction(SPI Mode)
43
HM25Q128A
Figure 7.8b Sector Erase Instruction(QPI Mode)
7.2.4 Block Erase (BE) (D8h) and Half Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) or half block (32K- bytes)
to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept
the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the
CS# pin low and shifting the instruction code “D8h” or “52h” followed a 24-bit block address (A23-A0). The
Block Erase instruction sequence is shown in Figure 7.9.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Block Erase instruction will not be executed. After CS# is driven high, the self-timed Block Erase
instruction will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit.
The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device
is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the
addressed page is protected by the Block Protect (TB, SEC, BP2, BP1, and BP0) bits (see Status Register
Memory Protection table).
Figure 7.9a Block Erase Instruction(SPI Mode)
Figure 7.9b Block Erase Instruction(QPI Mode)
7.2.5 Chip Erase (CE) (C7h or 60h)
44
HM25Q128A
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register
bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruction code
“C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 7.10.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After CS# is driven high, the self-timed Chip Erase instruction will commence
for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress, the Read Status
Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the
Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again.
After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0.
The Chip Erase instruction will not be executed if any page is protected by the Block Protect (SEC, TB, BP2,
BP1, and BP0) bits (see Status Register Memory Protection table).
Figure 7.10 Chip Erase Instruction(SPI or QPI Mode)
7.2.6 Erase / Program Suspend (75h)
The Erase / Program Suspend command allows the system to interrupt a Sector or Block Erase operation,
then read from or program data to any other sector. The Erase / Program Suspend command also allows the
system to interrupt a Page Program operation and then read from any other page or erase any other sector or
block. The Erase / Program Suspend command sequence is shown in Figure 7.11.
The Write Status Registers command (01h, 31h, 11h), and Erase commands (20h, 52h, D8h, C7h, 60h,
44h) are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase
operation. If written during the Chip Erase operation, the Erase Suspend command is ignored. The Write
Status Registers command (01h, 31h), and Program commands (02h, 32h, 42h) are not allowed during
Program Suspend. Program Suspend is valid during the Page Program or Quad Page Program operation.
The Erase / Program Suspend command 75h will be accepted by the device only if the SUS bit in the
Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program
operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend command will be
ignored by the device. Program or Erase command for the sector that is being suspended will be ignored.
A maximum of time of tSUS (Section 8.5, AC Electrical Characteristics) is required to suspend the erase or
program operation. The BUSY bit in the Status Register will be cleared from 1 to 0 within tSUS and the SUS bit
in the Status Register will be set from 0 to 1 immediately after Erase/Program Suspend. For a previously
resumed Erase/Program operation, it is also required that the Suspend command 75h is not issued earlier
than a minimum of time of tSUS following the preceding Resume command 7Ah.
Unexpected power off during the Erase / Program suspend state will reset the device and release the
suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that
was being suspended may become corrupted. It is recommended for the user to implement system design
techniques to prevent accidental power interruption, provide non-volatile tracking of in process program or
erase commands, and preserve data integrity by evaluating the non-volatile program or erase tracking
information during each system power up in order to identify and repair (re-erase and re-program) any
improperly terminated program or erase operations.
45
HM25Q128A
Figure 7.11a Erase / Program Suspend Instruction(SPI Mode)
Figure 7.11b Erase / Program Suspend Instruction(QPI Mode)
7.2.7 Erase / Program Resume (7Ah)
The Erase / Program Resume command “7Ah” must be written to resume the Sector or Block Erase
operation or the Page Program operation after an Erase / Program Suspend. The Resume command “7Ah”
will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to
0. After the Resume command is issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will
be set from 0 to 1 within 200 ns and the Sector or Block will complete the erase operation or the page will
complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume command
“7Ah” will be ignored by the device. The Erase / Program Resume command sequence is shown in Figure
7.12. It is required that a subsequent Erase / Program Suspend command not to be issued within a minimum
of time of “tSUS” following a Resume command.
Figure 7.12 Erase/Program Resume Instruction(SPI or QPI Mode)
7.3 Read Commands
7.3.1 Read Data (03h)
The Read Data instruction allows one more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the CS# pin low and then shifting the instruction code “03h” followed by a
46
HM25Q128A
24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the CLK
pin. After the address is received, the data byte of the addressed memory location will be shifted out on the
DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream
of data. This means that the entire memory can be accessed with a single instruction as long as the clock
continues. The instruction is completed by driving CS# high.
The Read Data instruction sequence is shown in Figure 7.13. If a Read Data instruction is issued while
an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fR (see
AC Electrical Characteristics).
Figure 7.13 Read Data Instruction
7.3.2 Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy”
clocks after the 24-bit address as shown in Figure 7.14. The dummy clocks allow the devices internal circuits
additional time for setting up the initial address. During the dummy clocks the data value on the DI pin is a
“don’t care”.
Figure 7.14a Fast Read Instruction (SPI Mode)
Fast Read (0Bh) in QPI Mode
The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the number of
dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide range of
applications with different needs for either maximum Fast Read frequency or minimum data access latency.
Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as
either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 2.
47
HM25Q128A
Figure 7.14b Fast Read Instruction (QPI Mode)
7.3.3 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins, DO and DI, instead of just DO. This allows data to be transferred from the
ZB25VQ128 at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for
quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to
RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy”
clocks after the 24-bit address as shown in Figure 7.15. The dummy clocks allow the device's internal circuits
additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”.
However, the DI pin should be high-impedance prior to the falling edge of the first data out clock.
Figure 7.15 Fast Read Dual Output Instruction Sequence Diagram
7.3.4 Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Dual Output (3Bh) instruction except
that data is output on four pins, IO0, IO1, IO2 and IO3. A Quad enable of status Register-2 must be executed
before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1).
The Fast Read Quad Output Instruction allows data to be transferred from HM25Q128A at four times the rate
of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). This is accomplished by adding "dummy" clocks after the 24-bit address as shown
in Figure 7.16. The input data during the dummy clocks is "don't care". However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.
48
HM25Q128A
Figure 7.16 Fast Read Quad Output Instruction
7.3.5 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Address bits (A23-0) two bits per dock. This reduced instruction overhead may allow for code execution
(XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with "Continuous Read Mode"
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
"Continuous Read Mode" bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.17. The upper
nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or
exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don't care ("X"). However,
the IO pins should be high-impedance prior to the falling edge of the first data out clock. It is recommended to
input FFFFh on IO0 for the next instruction (16 clocks), to ensure M4 = 1 and return the device to normal
operation.
Figure 7.17 Fast Read Dual I/O Instruction (Initial command or previous M5-4≠10)
Note:
1. Least significant 4 bits of Mode are don’t care and it is optional for the host to drive these bits. The host may turn off drive during these
cycles to increase bus turnaround time between Mode bits from host and returning data from the memory
Figure 7.18 Fast Read Dual I/O Instruction (Initial command or previous M5-4=10)
7.3.6 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) command is similar to the Fast Read Dual I/O (BBh) command except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and Dummy clock are
required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster
random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status
Register-2 must be set to enable the Fast Read Quad I/O Command.
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HM25Q128A
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O command can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.19, Fast Read
Quad I/O Command Sequence (Initial command or previous M5-4≠10). The upper nibble of the (M7-4)
controls the length of the next Fast Read Quad I/O command through the inclusion or exclusion of the first
byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“X”). However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O command (after CS#
is raised and then lowered) does not require the EBh instruction code, as shown in Figure 7.20, Fast Read
Quad I/O Command Sequence (Previous command set M5-4 = 10). This reduces the command sequence by
eight clocks and allows the Read address to be immediately entered after CS# is asserted low. If the
“Continuous Read Mode” bits M5-4 do not equal to (1, 0), the next command (after CS# is raised and then
lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to
input FFh on IO0 for the next instruction (8 clocks), to ensure M4=1 and return the device to normal operation.
Figure 7.19a Fast Read Quad I/O Instruction(Initial command or previous M5-4 ≠10)
Figure 7.20 Fast Read Quad I/O Instruction(Previous command set M5-4 = 10)
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Fast Read Quad I/O command can also be used to access a specific portion within a page by issuing
a “Set Burst with Wrap” command prior to EBh. The “Set Burst with Wrap” command can either enable or
disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the data
being accessed can be limited to 8/16/32/64-byte section of data. The output data starts at the initial address
specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will
wrap around to the beginning boundary automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and
then fill the cache afterwards within a fixed length (8/16/32/64-bytes) of data without issuing multiple read
commands.
The “Set Burst with Wrap” command allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 is used to specify the length of the wrap around
section within a page. See Section 7.3.9, Set Burst with Wrap (77h).
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HM25Q128A
Fast Read Quad I/O (EBh) in QPI Mode
The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 7.19b When QPI
mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction
to accommodate a wide range of applications with different needs for either maximum Fast Read frequency or
minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy
clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a
Reset instruction is 2. In QPI mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy
clocks. In the default setting, the data output will follow the Continuous Read Mode bits immediately.
“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction.
Please refer to the description on previous pages.
“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a
read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch)
instruction must be used. Please refer to 7.5.13 for details.
Figure 7.19b Fast Read Quad I/O Instruction(Initial command or previous M5-4 ≠10,QPI Mode)
7.3.7 Word Read Quad I/O (E7h)
The Word Read Quad I/O (E7h) instruction is similar to the Fast Quad I/O (EBh) instruction except that
the lowest Address bit (A0) must equal to 0 and only two Dummy clocks are required prior to the data output.
The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution
(XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the
Word Read Quad I/O instruction.
Word Read Quad I/O with "Continuous Read Mode"
The Word Read Quad I/O instruction can further reduce instruction overhead through setting the
"Continuous Read Mode" bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.21. The upper
nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or
exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don't care ("X"). However,
the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the "Continuous Read Mode" bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS#
is raised and then lowered) does not require the E7h instruction code, as shown in Figure 7.22. This reduces
the instruction sequence by eight clocks and allows the read address to be immediately entered after CS# is
asserted low. The "Continuous Read Mode Reset” instruction is also able to reset M7-0 before issuing normal
instructions.
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HM25Q128A
Figure 7.21 Word Read Quad I/O Instruction(Initial command or previous M5-4 ≠10)
Figure 7.22 Word Read Quad I/O Instruction(Initial command or previous M5-4 =10)
Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Word Read Quad I/O instruction can also be used to access a specific portion within a page by
issuing a “Set Burst with Wrap” (77h) command prior to E7h. The “Set Burst with Wrap” (77h) command can
either enable or disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is
enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page.
The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of
the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until CS# is
pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and
then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around
section within a page. See 7.3.9 for detail descriptions.
7.3.8 Octal Word Read Quad I/O (E3h)
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lower four Address bits (A0, A1 , A2, A3) must equal 0. As a result, the dummy clocks are not
required, which further reduces the instruction overhead allowing even faster random access for code
execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word Read
Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.23. The upper
nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through the inclusion
or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However,
the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is
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HM25Q128A
raised and then lowered) does not require the E3h instruction code, as shown in Figure 7.24. This reduces the
instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is
asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is
recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4= 1 and return the device to
normal operation.
Figure 7.23 Octal Word Read Quad I/O Instruction(Initial command or previous M5-4 ≠10)
Figure 7.24 Octal Word Read Quad I/O Instruction(Initial command or previous M5-4 =10)
7.3.9 Set Burst with Wrap (77h)
The Set Burst with Wrap (77h) command is used in conjunction with “Fast Read Quad I/O” commands to
access a fixed length and alignment of 8/16/32/64-bytes of data. Certain applications can benefit from this
feature and improve the overall system code execution performance. This command loads the W4,W5,W6
bits. Similar to a Quad I/O command, the Set Burst with Wrap command is initiated by driving the CS# pin low
and then shifting the instruction code “77h” followed by 24-dummy bits and 8 “Wrap Bits”, W7-0. The
command sequence is shown in Figure 7.25, Set Burst with Wrap Command Sequence. Wrap bit W7 and the
lower nibble W3-0 are not used.
W4=0
Wrap Around
W4=1(DEFAULT)
W6, W5
Wrap Length
8-byte
Wrap Around
Wrap Length
0,0
0,1
1,0
1,1
Yes
Yes
Yes
Yes
No
No
No
No
N/A
N/A
N/A
N/A
16-byte
32-byte
64-byte
Once W6-4 is set by a Set Burst with Wrap command, all the following “Fast Read Quad I/O” commands
will use the W6-4 setting to access the 8/16/32/64-byte section of data. Note, Status Register-2 QE bit
(SR2[1]) must be set to 1 in order to use the Fast Read Quad I/O and Set Burst with Wrap commands. To exit
the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap command
should be issued to set W4 = 1. The default value of W4 upon power on is 1.
In QPI mode, the “Burst Read with Wrap (0Ch)” instruction should be used to perform the Read operation
53
HM25Q128A
with “Wrap Around” feature. The Wrap Length set by W6-5 in Standard SPI mode is still valid in QPI mode and
can also be re-configured by “Set Read Parameters (C0h)” instruction. Refer to 7.5.12 and 7.5.13 for details.
Figure 7.25 Set Burst with Wrap Instruction
7.4 Reset Commands
Software controlled Reset commands restore the device to its initial power up state, by reloading volatile
registers from non-volatile default values. If a software reset is initiated during a Erase, Program or Writing
Register operation the data in that Sector, Page or Register is not stable, the operation that was interrupted
needs to be initiated again. Once the Reset instruction is accepted, any on-going internal operations will be
terminated and the device will return to its default power-on state and lose all the current volatile settings,
such as Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Read
parameter setting (P7-P0), Continuous Read Mode bit setting (M7-M0) and Wrap Bit setting (W6-W4).
When the device is in Deep Power-Down mode, the software reset command is ignored and has no
effect. To reset the device send the Release Power down command (ABh) and after time duration of tRES1 the
device will resume normal operation and the software reset command will be accepted.
A software reset is initiated by the Software Reset Enable command (66h) followed by Software Reset
command (99h) and then executed when CS# is brought high after tRCH time at the end of the Software Reset
instruction and requires tRST time before executing the next Instruction after the Software Reset. See Figure
8.7, Software Reset Input Timing. Note that CS# must be brought high after tRCH time, or the Software Reset
will not be executed.
Figure 7.26 Software Reset Instruction(SPI and QPI Mode)
7.4.1 Software Reset Enable (66h)
The Reset Enable (66h) command is required immediately before a software reset command (99h) such
that a software reset is a sequence of the two commands. Any command other than Reset (99h) following the
Reset Enable (66h) command, will clear the reset enable condition and prevent a later Reset (99h) command
from being recognized.
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HM25Q128A
7.4.2 Software Reset (99h)
The Reset (99h) command immediately following a Reset Enable (66h) command, initiates the software
reset process. Any command other than Reset (99h) following the Reset Enable (66h) command, will clear the
reset enable condition and prevent a later Reset (99h) command from being recognized.
7.5 ID and Security Commands
7.5.1 Deep Power-down (DP) (B9h)
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Power-down instruction. The lower power consumption makes the Power- down instruction
especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction
is initiated by driving the CS# pin low and shifting the instruction code “B9h” as shown in Figure 7.27.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done, the Power-
down instruction will not be executed. After CS# is driven high, the power-down state will enter within the time
duration of tDP (See AC Characteristics). While in the power-down state only the Release from Power-down /
Device ID instruction, which restores the device to normal operation, will be recognized. All other instructions
are ignored. This includes the Read Status Register instruction, which is always available during normal
operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing
maximum write protection. The device always powers-up in the normal operation with the standby current of
ICC1.
Figure 7.27 Deep Power-down Instruction(SPI and QPI Mode)
7.5.2 Release Power-down / Device ID (ABh)
The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the power-down state, obtain the devices electronic identification (ID) number or both.
To release the device from the power-down state, the instruction is issued by driving the CS# pin low,
shifting the instruction code “ABh” and driving CS# high as shown in Figure 7.28. After the time duration of
tRES1 (See AC Characteristics) the device will resume normal operation and other instructions will be accepted.
The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID during the non-power-down state, the instruction is initiated by
driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits
will then be shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.29.
The Device ID value for the HM25Q128A is listed in Manufacturer and Device Identification table. The Device
ID can be read continuously. The instruction is completed by driving CS# high.
When used to release the device from the power-down state and obtain the Device ID, the instruction is
the same as previously described, and shown in Figure 7.29, except that after CS# is driven high it must
remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will
resume normal operation and other instructions will be accepted. If the Release from Power-down / Device ID
instruction is issued within Erase, Program or Write cycle (when BUSY equals 1), the instruction is ignored
and will not have any effects on the current cycle.
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HM25Q128A
Figure 7.28 Release Power-down Instruction(SPI and QPI Mode)
Figure 7.29a Release Power-down / Device ID(SPI Mode)
Figure 7.29b Release Power-down / Device ID(QPI Mode)
7.5.3 Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down/Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID
instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code “90h”
followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID and the Device ID are
shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.30. If the 24-bit
address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID.
The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The command
is completed by driving CS# high.
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HM25Q128A
Figure 7.30a Read Manufacturer/Device ID(SPI Mode)
Figure 7.30b Read Manufacturer/Device ID(QPI Mode)
7.5.4 Read Identification (RDID) (9Fh)
For compatibility reasons, the HM25Q128A provides several instructions to electronically determine the
identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI
compatible serial memories that was adopted in 2003.
The instruction is initiated by driving the CS# pin low and shifting the instruction code “9Fh”. The JEDEC
assigned Manufacturer ID byte and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are
then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.31. For
memory type and capacity values, refer to Manufacturer and Device Identification table.
Figure 7.31a Read JEDEC ID(SPI Mode)
Figure 7.31b Read JEDEC ID(QPI Mode)
7.5.5 Read SFDP Register (5Ah)
The Read SFDP command is initiated by driving the CS# pin low and shifting the instruction code “5Ah”
followed by a 24-bit address (A23-A0) into the DI pin. Eight “dummy” clocks are also required before the
SFDP register contents are shifted out on the falling edge of the 40th CLK with most significant bit (MSB) first
as shown in Figure 7.32.
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HM25Q128A
Note: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-byte SFDP Register.
Figure 7.32 Read SFDP Register Instruction
7.5.6 Erase Security Registers (44h)
The HM25Q128A offers three 256-byte Security Registers which can be erased and programmed
individually. These registers may be used by system manufacturers to store security and other important
information separately from the main memory array.
The Erase Security Register command is similar to the Sector Erase command. A Write Enable
command must be executed before the device will accept the Erase Security Register Command (Status
Register bit WEL must equal to 1). The command is initiated by driving the CS# pin low and shifting the
instruction code “44h” followed by a 24-bit address (A23-A0) to erase one of the security registers.
Address
A23-16
00h
00h
A15-8
10h
20h
A7-0
xxh
xxh
xxh
Security Register-1
Security Register-2
Security Register-3
00h
30h
Note:
1. Addresses outside the ranges in the table have undefined results.
The Erase Security Register command sequence is shown in Figure 7.33. The CS# pin must be driven
high after the eighth bit of the last byte has been latched. If this is not done the command will not be executed.
After CS# is driven high, the self-timed Erase Security Register operation will commence for a time duration of
tSE (see Section 8.5, AC Electrical Characteristics). While the Erase Security Register cycle is in progress, the
Read Status Register command may still be accessed for checking the status of the BUSY bit. The BUSY bit
is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other commands again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit
in the Status Register is cleared to 0. The Security Register Lock Bits (LB[3:1]) in the Status Register-2 can be
used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will
be permanently locked, and an Erase Security Register command to that register will be ignored.
Figure 7.33 Erase Security Registers Instruction
7.5.7 Program Security Registers (42h)
The Program Security Register command is similar to the Page Program command. It allows from one
byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A
Write Enable command must be executed before the device will accept the Program Security Register
Command (Status Register bit WEL= 1). The command is initiated by driving the CS# pin low then shifting the
instruction code “42h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The
CS# pin must be held low for the entire length of the command while data is being sent to the device.
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HM25Q128A
Address
A23-16
00h
00h
A15-8
10h
20h
A7-0
Security Register-1
Security Register-2
Security Register-3
Byte Address
Byte Address
Byte Address
00h
30h
Note:
1. Addresses outside the ranges in the table have undefined results.
The Program Security Register command sequence is shown in Figure 7.34. The Security Register Lock
Bits (LB3:1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set
to 1, the corresponding security register will be permanently locked, and a Program Security Register
command to that register will be ignored.
Figure 7.34 Program Security Registers Instruction
7.5.8 Read Security Registers (48h)
The Read Security Register command is similar to the Fast Read command and allows one or more data
bytes to be sequentially read from one of the three security registers. The command is initiated by driving the
CS# pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight
“dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After
the address is received, and following the eight dummy cycles, the data byte of the addressed memory
location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first.
Locations with address bits A23-A16 not equal to zero, have undefined data. The byte address is
automatically incremented to the next byte address after each byte of data is shifted out. Once the byte
address reaches the last byte of the register (FFh), it will reset to the first byte of the register (00h) and
continue to increase. The command is completed by driving CS# high. The Read Security Register command
sequence is shown in Figure 7.35. If a Read Security Register command is issued while an Erase, Program,
or Write cycle is in process (BUSY=1), the command is ignored and will not have any effects on the current
cycle. The Read Security Register command allows clock rates from DC to a maximum of FR (see Section 8.5,
AC Electrical Characteristics).
Address
A23-16
00h
00h
A15-8
10h
20h
A7-0
Security Register-1
Security Register-2
Security Register-3
Byte Address
Byte Address
Byte Address
00h
30h
Note:
1. Addresses outside the ranges in the table have undefined results.
Figure 7.35 Read Security Registers Instruction
7.5.9 Individual Block/Sector Lock (36h)
The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse
Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be
set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2:0] bits in
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HM25Q128A
the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device
power up or after a Reset are 1, so the entire memory array is being protected.
To lock a specific block or sector as illustrated in Figure 6.2, an Individual Block/Sector Lock command
must be issued by driving CS# low, shifting the instruction code “36h” into the Data Input (DI) pin on the rising
edge of CLK, followed by a 24-bit address and then driving CS# high. A Write Enable instruction must be
executed before the device will accept the Individual Block/Sector Lock Instruction (Status Register bit WEL=
1).
Figure 7.36a Individual Block/Sector Lock Instruction(SPI Mode)
Figure 7.36b Individual Block/Sector Lock Instruction(QPI Mode)
7.5.10 Individual Block/Sector Unlock (39h)
The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse
Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be
set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2:0] bits in
the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device
power up or after a Reset are 1, so the entire memory array is being protected.
To unlock a specific block or sector as illustrated in Figure 6.2, an Individual Block/Sector Unlock
command must be issued by driving CS# low, shifting the instruction code “39h” into the Data Input (DI) pin on
the rising edge of CLK, followed by a 24-bit address and then driving CS# high. A Write Enable instruction
must be executed before the device will accept the Individual Block/Sector Unlock Instruction(Status Register
bit WEL= 1).
Figure 7.37a Individual Block/Sector Unlock Instruction(SPI Mode)
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HM25Q128A
Figure 7.37b Individual Block/Sector Unlock Instruction(QPI Mode)
7.5.11 Read Block/Sector Lock (3Dh)
The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse
Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be
set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2:0] bits in
the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device
power up or after a Reset are 1, so the entire memory array is being protected.
To read out the lock bit value of a specific block or sector as illustrated in Figure 6.2, a Read Block/Sector
Lock command must be issued by driving CS# low, shifting the instruction code “3Dh” into the Data Input (DI)
pin on the rising edge of CLK, followed by a 24-bit address. The Block/Sector Lock bit value will be shifted out
on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure7.38. If the
least significant bit (LSB) is 1, the corresponding block/sector is locked; if LSB=0, the corresponding
block/sector is unlocked, Erase/Program operation can be performed.
Figure 7.38a Read Block Lock Instruction(SPI Mode)
Figure 7.38b Read Block Lock Instruction(QPI Mode)
7.5.12 Global Block/Sector Lock (7Eh)
All Block/Sector Lock bits can be set to 1 by the Global Block/Sector Lock instruction. The command
must be issued by driving CS# low, shifting the instruction code “7Eh” into the Data Input (DI) pin on the rising
edge of CLK, and then driving CS# high. A Write Enable instruction must be executed before the device will
accept the Global Block/Sector Lock Instruction (Status Register bit WEL=1).
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HM25Q128A
Figure 7.39 Global Block Lock Instruction(SPI or QPI Mode)
7.5.13 Global Block/Sector Unlock (98h)
All Block/Sector Lock bits can be set to 0 by the Global Block/Sector Unlock instruction. The command
must be issued by driving CS# low, shifting the instruction code “98h” into the Data Input (DI) pin on the rising
edge of CLK, and then driving CS# high. A Write Enable instruction must be executed before the device will
accept the Global Block/Sector Unlock Instruction (Status Register bit WEL= 1).
Figure 7.40 Global Block Lock Instruction(SPI or QPI Mode)
7.5.14 Read Manufacturer / Device ID Dual I/O (92h)
The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x
speed.
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction.
The instruction is initiated by driving the CS# pin low and shifting the instruction code “92h” followed by a
24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits two bits per clock. After
which, the Manufacturer ID and the Device ID are shifted out 2 bits per clock on the falling edge of CLK with
most significant bits (MSB) first as shown in Figure 7.41. The Device ID values for the ZB25VQ128 are listed
in Manufacturer and Device Identification table. The Manufacturer and Device IDs can be read continuously,
alternating from one to the other. The instruction is completed by driving CS# high.
62
HM25Q128A
Figure 7.41 Read Manufacturer/Device ID Dual I/O Instruction
Note:
1. The "Continuous Read Mode" bits M7-0 must be set to Fxh to be compatible with Fast Read Dual I/O instruction.
7.5.15 Read Manufacturer / Device ID Quad I/O (94h)
The Read Manufacturer / Device ID Quad I/O instruction is an alternative to Read Manufacturer / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 4 x
speeds.
The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction.
The instruction is initiated by driving the CS# pin low and shifting the instruction code "94h" followed by a
24-bit address(A23-A0) of 000000h, 8-bit Continuous Read Mode Bits and then four clock dummy cycles, with
the capability to input the Address bits four bits per clock. After that, the Manufacturer ID and the Device ID
are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 7.42. The Device ID values for HM25Q128A are listed in Manufacturer and Device Identification table.
The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction
is completed by driving CS# high.
Figure 7.42 Read Manufacturer/Device ID Quad I/O Instruction
Note:
1. The "Continuous Read Mode" bits M7-0 must be set to Fxh to be compatible with Fast Read Quad I/O
instruction.
7.5.16 Read Unique ID Number (4Bh)
The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number which is unique
to each HM25Q128A device. The ID number can be used in conjunction with user software methods to help
prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the CS# pin low
and shifting the instruction code "4Bh" followed by four bytes dummy clocks. After that, the 64-bit ID is shifted
out on the falling edge of CLK as shown in Figure 7.43.
Figure 7.43 Read unique ID Number Instruction
7.5.17 Set Read Parameters (C0h)
In QPI mode, to accommodate a wide range of applications with different needs for either maximum read
frequency or minimum data access latency, “Set Read Parameters (C0h)” instruction can be used to configure
63
HM25Q128A
the number of dummy clocks for “Fast Read (0Bh)”, “Fast Read Quad I/O (EBh)” & “Burst Read with Wrap
(0Ch)” instructions, and to configure the number of bytes of “Wrap Length” for the “Burst Read with Wrap
(0Ch)” instruction.
In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy clocks
for various Fast Read instructions in Standard/Dual/Quad SPI mode are independently controlled by SR3[3:0],
see details in Table 6.5. The “Wrap Length” is set by W6-5 bit in the “Set Burst with Wrap (77h)” instruction.
This setting will remain unchanged when the device is switched between Standard SPI mode and QPI mode.
The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number of
dummy clocks is 2. The number of dummy clocks is only programmable for “Fast Read (0Bh)”, “Fast Read
Quad I/O (EBh)” & “Burst Read with Wrap (0Ch)” instructions in the QPI mode. Whenever the device is
switched from SPI mode to QPI mode, the number of dummy clocks should be set again, prior to any 0Bh,
EBh or 0Ch instructions.
DUMMY
CLOCKS
MAXIMUM
READ FREQ.
MAXIMUM READ
FREQ.(A[1:0]=0,0)
WRAP
LENGTH
P5-P4
P1-P0
00
01
10
11
2
4
6
8
50MHz
80MHz
104MHz
104MHz
50MHz
104MHz
104MHz
104MHz
00
01
10
11
8-byte
16-byte
32-byte
64-byte
Figure 7.44 Set Read Parameters Instruction (QPI Mode only)
7.5.18 Burst Read with Wrap (0Ch)
The “Burst Read with Wrap (0Ch)” instruction provides an alternative way to perform the read operation
with “Wrap Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh)” instruction in QPI mode,
except the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap
Length” once the ending boundary is reached. The “Wrap Length” and the number of dummy clocks can be
configured by the “Set Read Parameters(C0h)” instruction.
Figure 7.45 Burst Read with Wrap Instruction (QPI Mode only)
64
HM25Q128A
7.5.19 Enter QPI Mode (38h)
The HM25Q128A upport both Standard/Dual/Quad Serial Peripheral Interface (SPI) and Quad
Peripheral Interface (QPI). However, SPI mode and QPI mode cannot be used at the same time. “Enter QPI
(38h)” instruction is the only way to switch the device from SPI mode to QPI mode.
Upon power-up, the default state of the device upon is Standard/Dual/Quad SPI mode. This provides full
backward compatibility with earlier generations of ZBIT serial flash memories. See Instruction Set Table
7.1-7.4 for all supported SPI commands. In order to switch the device to QPI mode, the Quad Enable (QE) bit
in Status Register-2 must be set to 1 first, and an “Enter QPI (38h)” instruction must be issued. If the Quad
Enable (QE) bit is 0, the “Enter QPI (38h)” instruction will be ignored and the device will remain in SPI mode.
See Instruction Set Table 7.5 for all the commands supported in QPI mode. When the device is switched from
SPI mode to QPI mode, the existing Write Enable and Program/Erase Suspend status, and the Wrap Length
setting will remain unchanged.
Figure 7.46 Enter QPI Instruction (SPI Mode only)
7.5.20 Exit QPI Mode (FFh)
In order to exit the QPI mode and return to the Standard/Dual/Quad SPI mode, an “Exit QPI (FFh)”
instruction must be issued. When the device is switched from QPI mode to SPI mode, the existing Write
Enable Latch (WEL) and Program/Erase Suspend status, and the Wrap Length setting will remain
unchanged.
Figure 7.47 Exit QPI Instruction (QPI Mode only)
65
HM25Q128A
8. ELECTRICAL CHARACTERISTIC
Figure 8.1 Power-up Timing
Table 8.1 Power-up Timing
TYPE
PARAMETER
SYMBOL
UNIT
MIN
2.3
2.1
1.0
10
1
MAX
Vcc(min)
-
-
-
-
Vcc(minimum operation voltage)
V
V
Vcc(cut off)
Vcc(cut off where re-initialization is needed)
Vcc(low voltage for initialization to occur)
Vcc (min) to CS# Low
Vcc(low)
V
(1)
μs
ms
μs
V
tVSL
(1)
10
-
Time Delay Before Write Instruction
Vcc (low) time
tPUW
tPD
10
1
(1)
VWI
2
Write Inhibit Threshold Voltage
Notes:
(1)The parameters are characterized only.
(2)VCC (max.) is 3.6V and VCC (min.) is 2.3V.
Figure 8.2 Power-Down and Voltage Drop
66
HM25Q128A
8.1. Absolute Maximum Ratings
Stresses above the values mentioned as following may cause permanent damage to the device. These
values are for a stress rating only and do not imply that the device should be operated at conditions up to or
above these values.
Table 8.2(1) Absolute Maximum Rating
PARAMETERS(2)
Supply Voltage
SYMBOL
CONDITIONS
RANGE
-0.6 to +4.0
UNIT
V
VCC
Voltage applied on any pin
VIO
Relative to Ground
<20ns Transient Relative to
Ground
-0.6 to VCC+0.4
V
Transient Voltage on any Pin
VIOT
-2.0 to VCC+2.0
V
Storage Temperature
Lead Temperature
TSTG
TLEAD
VESD
-65 to +150
See Note(3)
℃
℃
V
Human Body Model(4)
Electrostatic Discharge Voltage
-2000 to +2000
Notes:
(1)Specification for HM25Q128A is preliminary. See preliminary designation at the end of this document.
(2)This device has been designed and tested for the specified operation ranges. Proper operation outside these levels is not
guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings
may cause permanent damage.
(3)Compatible to JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive
on restrictions on hazardous substances (RoHS) 2002/95/EU.
(4)JEDEC Std. JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).
8.2. Recommended Operating Ranges
Table 8.3 Recommended Operating Ranges
SPEC
PARAMETER
SYMBOL
CONDITIONS
UNIT
MIN
2.7
MAX
3.6
FR=104MHz,fR=80MHz
FR=80MHz,fR=50MHz
V
V
(1)
Supply Voltage
VCC
2.3
-40
2.7
Ambient Temperature,
Operating
℃
TA
Industrial
+85
Notes:
(1)Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
67
HM25Q128A
8.3. DC Characteristics
Table 8.4 DC Characteristics
SPEC
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
TYP
MAX
6
8
±2
±2
CIN(1)
COUT(1)
ILI
Input Capacitance
Output Capacitance
Input Leakage
VIN = 0V(2)
VOUT = 0V(2)
pF
pF
uA
uA
ILO
I/O Leakage
CS# = VCC, VIN=
GND or VCC
CS# = VCC, VIN=
GND or VCC
ICC1
ICC2
Standby Current
15
2
25
5
uA
uA
Power-down Current
Current Read Data /
Dual/Quad Output
Read 50MHz(2)
C = 0.1 VCC / 0.9
VCC DO = Open
ICC3
ICC3
ICC3
15
18
20
mA
mA
mA
Current Read Data /
Dual/Quad Output
Read 80MHz(2)
C = 0.1 VCC / 0.9
VCC DO = Open
Current Read Data /
Dual/Quad Output
Read 104MHz(2)
C = 0.1 VCC / 0.9
VCC DO = Open
Current Page
Program
Current Write Status
Register
20
20
25
25
ICC4
ICC5
CS# = VCC
CS# = VCC
mA
mA
Current Sector/Block
Erase
Current Chip Erase
High Performance
Current
CS# = VCC
CS# = VCC
20
20
25
25
ICC6
ICC7
mA
mA
ICC8
50
uA
VIL
VIH
VOL
VOH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-0.5
VCC×0.7
V
CC×0.3
V
V
V
V
IOL = 100 uA
IOH = －100 uA
0.2
V
CC－0.2
Notes:
(1)Tested on sample basis and specified through design and characterization data. TA=25° C, VCC=3V.
(2)Checker Board Pattern.
8.4. AC Measurement Conditions
Table 8.5 AC Measurement Conditions
Symbol
CL
PARAMETER
Load Capacitance
Min.
Max.
30
Unit
pF
ns
V
TR, TF
VIN
Input Rise and Fall Times
Input Pulse Voltages
5
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
0.5 VCC to 0.5 VCC
VtIN
Input Timing ReferenceVoltages
Output Timing ReferenceVoltages
V
VtON
V
Figure 8.3 AC Measurement I/O Waveform
68
HM25Q128A
8.5. AC Electrical Characteristics
Table 8.6 AC Electrical Characteristics
SPEC
SYMBOL
ALT
Parameter
UNIT
MIN
D.C.
TYP
MAX
Clock frequency for all QPI/Quad IO instructions with
HFQ, Vcc=2.7V-3.6V
Clock frequency for all SPI instructions (except 03h/EBh)
Vcc=2.7V-3.6V
Clock frequency for all SPI instructions (except 03h/EBh)
Vcc=2.3V-2.7V(1)
104
104
80
MHz
MHz
MHz
FR
FR
fC
fC
fC
D.C.
D.C.
FR
fR
Clock frequency for Read Data instruction (03h)
D.C.
4
60
MHz
ns
Clock High, Low Time for all instructions except Read
Data (03h)
(2)
tCLH, tCLL
(2)
Clock High, Low Time for Read Data (03h) instruction
tCRLH, tCRLL
6
0.1
0.1
ns
V/ns
V/ns
(3)
tCLCH
Clock Rise Time peak to peak
Clock Fall Time peak to peak
(3)
tCHCL
CS# Active Setup Time relative to CLK
CS# Not Active Hold Time relative to CLK
tSLCH
tCSS
5
ns
tCHSL
tDVCH
tCHDX
5
2
5
ns
ns
ns
tDSU
tDH
Data In Setup Time
Data In Hold Time
CS# Active Hold Time relative to CLK
tCHSH
5
ns
CS# Not Active Setup Time relative to CLK
tSHCH
tSHSL1
5
10
ns
ns
tCSH1
tCSH2
CS# Deselect Time SPI (Array ReadArray Read)
CS# Deselect Time for Erase/ProgramRead SR
Volatile Status Register Write Time
tSHSL2
50
ns
CS# Deselect Time for non Array Read→Array
Read(Dual IO, Quad IO and QPI Read)
Output Disable Time
tSHSL3
tCSH3
tDIS
tV
ns
ns
ns
100
(3)
tSHQZ
7
7
9
Clock Low to Output Valid 2.7V- 3.6V
tCLQV
Clock Low to Output Valid 2.3V- 2.7
Output Hold Time
V
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX
tHLQZ
tV
tHO
ns
ns
ns
ns
ns
ns
ns
ns
2
5
5
5
5
HOLD# Active Setup Time relative to CLK
HOLD# Active Hold Time relative to CLK
HOLD# Not Active Setup Time relative to CLK
HOLD# Not Active Hold Time relative to CLK
HOLD# to Output Low-Z
(3)
tLZ
7
12
(3)
tHZ
HOLD# to Output High-Z
(4)
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High to Power-down Mode
tWHSL
20
ns
ns
μs
(4)
tSHWL
100
(3)
3
8
tDP
CS# High to Standby Mode without Electronic Signature
Read
CS# High to Standby Mode with Electronic Signature
Read
CS# High to next Command after Suspend
Write Status Register Time
(3)
tRES1
μs
μs
(3)
tRES2
6
(3)
tsus
tW
20
100
μs
ms
10
Page Program Time
0.5
1.5
tPP
ms
Sector Erase Time (4KB)
35
200
tSE
tBE1
tBE2
tCE
ms
s
s
s
ns
μs
Block Erase Time (32KB)
Block Erase Time (64KB)
Chip Erase Time
End of Reset Instruction to CE# High
CE# High to next Instruction after Reset
0.8
2
200
0.15
0.25
50
(3)
tRCH
40
10
(3)(5)
tRST
Notes:
(1)With HFQ, the clock frequency of all SPI instructions(except 03h/EBh) can reach 104MHz.
(2)Clock high + Clock low must be less than or equal to 1/fC.
(3)Value guaranteed by design and/or characterization, not 100% tested in production.
(4)Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.4. For multiple
bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes
programmed.
(5)It’s possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to
ensure reliable operation.
69
HM25Q128A
Figure 8.4 Serial Output Timing
Figure 8.5 Input Timing
Figure 8.6 Hold Timing
Figure 8.7 Software Reset Input Timing
70
HM25Q128A
9. PACKAGE MECHANICAL
9.1. 8-Pin SOIC 150-mil
9.2. 8-Pin SOIC 208-mil
71
HM25Q128A
9.3. 8-Contact WSON (6x5mm)
9.4. 8-Pin PDIP 300-mil
72
HM25Q128A
9.5. FAB024 24-Ball BGA
9.6. FAC024 24-Ball BGA Package
73
HM25Q128A
REVISION LIST
Version No.
Description
Date
2017/11/01
A
Initial Release
74
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