HT24LC16(8SOP-A) [HOLTEK]
EEPROM, 2KX8, Serial, CMOS, PDSO8,;
| 型号： | HT24LC16(8SOP-A) |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | EEPROM, 2KX8, Serial, CMOS, PDSO8, 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总12页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT24LC16
CMOS 16K 2-Wire Serial EEPROM
Features
·
·
Operating voltage:
Partial page write allowed
2.2V~5.5V for temperature -40°C to +85°C
·
·
·
·
·
·
·
16-byte Page Write Mode
·
Low power consumption
Write operation with built-in timer
Hardware controlled write protection
40-year data retention
-
Operation: 5mA max.
-
Standby: 2mA max.
·
·
·
·
106 rewrite cycles per word
Internal organization: 2048´8
2-wire Serial Interface
Industrial temperature range (-40°C to +85°C)
8-pin DIP/SOP/TSSOP package
Write cycle time: 5ms max.
Automatic erase-before-write operation
General Description
The HT24LC16 is an 16K-bit serial read/write
non-volatile memory device using the CMOS floating
gate process. Its 16384 bits of memory are organized
into 2048 words and each word is 8 bits. The device is
optimized for use in many industrial and commercial ap-
plications where low power and low voltage operation
are essential. Up to only one HT24LC16 device may be
connected to the same 2-wire bus. The HT24LC16 is
guaranteed for 1M erase/write cycles and 40-year data
retention.
Block Diagram
Pin Assignment
I
/
O
A
A
A
0
1
2
V
W
S
S
C
C
1
2
3
4
8
7
6
5
S
C
L
H
V
P
u
m
p
C
o
n
t
r
o
l
P
S
D
A
L
o
g
i
c
C
D
L
A
X
D
E
C
V
S
S
E
E
P
R
O
M
A
r
r
a
y
H
T
2
4
L
C
1
6
M
e
m
o
r
y
8
D
I
P
-
A
/
S
O
P
-
A
/
T
S
C
o
n
t
r
o
l
W
P
L
o
g
i
c
P
a
g
e
B
u
f
Y
D
E
C
A
d
d
r
e
s
s
A
0
~
A
2
S
e
n
s
e
A
M
P
C
o
u
n
t
e
r
R
/
W
C
o
n
t
r
o
V
C
C
V
S
S
Pin Description
Pin Name
A0~A2
SDA
I/O
I
Description
Address input
Serial data
I/O
I
Serial clock input
Write protect
SCL
I
WP
Negative power supply, ground
Positive power supply
VSS
¾
¾
VCC
Rev. 1.60
1
June 25, 2010
HT24LC16
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+6.0V
Input Voltage .............................VSS-0.3V to VCC+0.3V
Storage Temperature............................-50°C to 125°C
Operating Temperature.........................-40°C to +85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Test Conditions
Symbol
Parameter
Operating Voltage
Min.
Typ.
Max.
Unit
VCC
¾
Conditions
-40°C to +85°C
Read at 100kHz
Write at 100kHz
¾
VCC
ICC1
ICC2
VIL
2.2
5.5
V
mA
mA
V
¾
¾
¾
¾
¾
¾
¾
¾
Operating Current
5V
5V
¾
2
¾
¾
Operating Current
5
0.3VCC
VCC+0.5
0.4
Input Low Voltage
-1
VIH
VOL
ILI
0.7VCC
Input High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
V
¾
¾
IOL=2.1mA
2.4V
5V
5V
V
¾
¾
¾
VIN=0 or VCC
1
mA
mA
ILO
VOUT=0 or VCC
1
2.2V~
5.5V
VIN=0 or VCC
ISTB
Standby Current
2
¾
¾
mA
CIN
Input Capacitance (See Note)
Output Capacitance (See Note)
6
8
pF
pF
¾
¾
f=1MHz 25°C
f=1MHz 25°C
¾
¾
¾
¾
COUT
Note: These parameters are periodically sampled but not 100% tested
A.C. Characteristics
Standard
Mode*
V
=3V±10%
V
=5V±10%
CC
CC
Symbol
Parameter
Remark
Unit
Min.
Max.
100
¾
Min.
¾
Max.
400
¾
Min.
¾
Max.
1000
¾
f
Clock Frequency
¾
¾
¾
¾
4000
4700
¾
kHz
ns
SK
t
t
t
t
Clock High Time
600
1200
¾
400
600
¾
HIGH
Clock Low Time
¾
¾
¾
ns
LOW
SDA and SCL Rise Time
SDA and SCL Fall Time
Note
Note
1000
300
300
300
300
100
ns
r
f
¾
¾
¾
ns
After this period the first
clock pulse is generated
t
t
START Condition Hold Time
START Condition Setup Time
4000
4000
¾
¾
600
600
¾
¾
250
250
¾
¾
ns
ns
HD:STA
SU:STA
Only relevant for repeated
START condition
t
t
t
t
Data Input Hold Time
¾
¾
¾
¾
0
¾
¾
0
¾
¾
¾
¾
¾
ns
ns
ns
ns
HD:DAT
SU:DAT
SU:STO
AA
Data Input Setup Time
STOP Condition Setup Time
Output Valid from Clock
200
4000
¾
100
600
¾
100
250
50
¾
¾
¾
3500
900
550
Rev. 1.60
2
June 25, 2010
HT24LC16
Standard
Mode*
V
=3V±10%
V
=5V±10%
CC
CC
Symbol
Parameter
Remark
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Time in which the bus must
t
Bus Free Time
be free before a new trans- 4700
mission can start
¾
1200
¾
500
¾
ns
BUF
Input Filter Time Constant
(SDA and SCL Pins)
t
t
Noise suppression time
¾
¾
100
5
¾
¾
50
5
¾
¾
50
5
ns
SP
Write Cycle Time
¾
ms
WR
Notes: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC= 2.2V to 5.5V at Ta= -40°C to +85°C
For relative timing, refer to timing diagrams
Functional Description
·
Serial clock (SCL)
·
·
Start condition
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
·
Serial data (SDA)
Stop condition
The SDA pin is bidirectional for serial data transfer.
The pin is open drain driven and may be wired-OR
with any number of other open drain or open collector
devices.
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (re-
fer to Start and Stop Definition Timing Diagram).
·
·
A0, A1, A2
·
Acknowledge
The HT24LC16 does not use the device address pins
which limits the number of devices on a single bus to
one. The A0, A1 and A2 pins have no connection.
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re-
ceived each word. This happens during the ninth clock
cycle.
Write protect (WP)
The HT24LC16 has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when the connection is
grounded. When the write protect pin is connected to
D
a
t
a
a
l
l
o
w
e
d
t
o
c
h
a
n
g
e
S
D
A
V
CC, the write protection feature is enabled and oper-
ates as shown in the following table.
WP Pin Status Protect Array
S
C
L
S
t
a
r
t
N
o
r
A
S
C
t
K
o
p
A
a
v
d
d
r
e
s
s
o
c
o
n
d
i
t
i
o
n
c
o
e
n
d
i
t
i
c
k
n
o
w
l
e
s
d
t
g
a
e
t
a
l
i
d
At VCC
At VSS
Full Array (16K)
Normal Read/Write Operations
Device Addressing
The 16K EEPROM devices require an 8-bit device ad-
dress word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
Memory Organization
Internally organized with 2048 8-bit words, the 16K re-
quires an 11-bit data word address for random word ad-
dressing.
Device Operations
·
Clock and data transition
The 16K does not use any device address bits but in-
stead the 3 bits are used for memory page addressing.
These page addressing bits on the 16K devices should
be considered the most significant bits of the data word
address which follows. The A0, A1 and A2 pins have no
connection.
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
Rev. 1.60
3
June 25, 2010
HT24LC16
·
Acknowledge polling
The 8th bit device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
To maximize bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write com-
mand have been sent. If the device is still busy imple-
menting its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
1
0
1
0
A
2
A
1
R
A
/
0
W
S
e
n
d
W
r
i
t
e
C
o
m
D
e
v
i
c
e
A
d
d
r
e
s
s
S
e
n
d
S
t
o
p
C
o
n
d
Write Operations
t
o
I
n
i
t
i
a
t
e
W
r
i
·
Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledg-
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de-
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
nonvolatile memory. All inputs are disabled during this
write cycle and EEPROM will not respond until write is
complete (refer to Byte write timing).
S
e
n
d
S
t
a
r
t
S
e
n
d
C
o
n
t
r
o
l
B
w
i
t
h
R
/
W
=
0
N
o
(
A
C
K
=
0
)
?
Y
e
s
N
e
x
t
O
p
e
r
a
t
i
o
Acknowledge Polling Flow
Write protect
·
Page write
The 16K EEPROM is capable of a 16-byte page write.
A page write is initiated in the same way as a byte
write, but the microcontroller does not send a stop con-
dition after the first data word is clocked in. Instead, af-
ter the EEPROM acknowledges the receipt of the first
data word, the microcontroller can transmit up to 15
more data words. The EEPROM will respond with a
zero after each data word received. The
microcontroller must terminate the page write sequence
with a stop condition (refer to Page write timing).
The data word address lower four bits are internally in-
cremented following the receipt of each data word.
The higher data word address bits are not incre-
mented, retaining the memory page row location.
·
The HT24LC16 has a write-protect function and pro-
gramming will then be inhibited when the WP pin is
connected to VCC. Under this mode, the HT24LC16 is
used as a serial ROM.
·
Read operations
The HT24LC16 supports three read operations,
namely, current address read, random address read
and sequential read. During read operation execution,
the read/write select bit should be set to ²1².
D
e
v
i
c
e
a
d
d
r
W
e
s
o
s
r
d
a
d
d
r
e
s
s
D
A
T
A
S
D
A
S
A
2
A
1
A
0
P
R
/
W
S
t
a
r
t
A
C
K
A
C
K
A
C
K
S
t
o
p
Byte Write Timing
D
e
v
i
c
e
a
d
d
r
e
s
s
D
W
A
o
T
r
A
d
n
a
D
d
d
A
r
T
e
A
s
s
n
+
1
D
A
T
A
n
+
x
S
A
P
S
D
A
C
K
S
t
a
r
t
A
C
K
A
C
K
A
C
K
S
t
o
Page Write Timing
Rev. 1.60
4
June 25, 2010
HT24LC16
·
·
Sequential read
Current address read
The internal data word address counter maintains the
last address accessed during the last read or write op-
eration, incremented by one. This address stays valid
between operations as long as the chip power is main-
tained. The address roll over during read from the last
byte of the last memory page to the first byte of the first
page. The address roll over during write from the last
byte of the current page to the first byte of the same
page. Once the device address with the read/write se-
lect bit set to one is clocked in and acknowledged by
the EEPROM, the current address data word is seri-
ally clocked out. The microcontroller should respond
with a ²no ACK² signal (high) followed by a stop condi-
tion (refer to Current read timing).
Sequential reads are initiated by either a current ad-
dress read or a random address read. After the
microcontroller receives a data word, it responds with
an acknowledgment. As long as the EEPROM re-
ceives an acknowledgment, it will continue to incre-
ment the data word address and serially clock out
sequential data words. When the memory address
limit is reached, the data word address will roll over
and the sequential read continues. The sequential
read operation is terminated when the microcontroller
responds with a ²no ACK² signal (high) followed by a
stop condition.
·
Random read
Arandom read requires a dummy byte write sequence
to load in the data word address which is then clocked
in and acknowledged by the EEPROM. The
microcontroller must then generate another start con-
dition. The microcontroller now initiates a current ad-
dress read by sending a device address with the
read/write select bit high. The EEPROM acknowl-
edges the device address and serially clocks out the
data word. The microcontroller should respond with a
²no ACK² signal (high) followed by a stop condition
(refer to Random read timing).
D
e
v
i
c
e
a
d
d
r
e
s
D
s
A
T
A
S
t
o
p
S
D
A
S
A
2
A
1
A
0
P
S
t
a
r
t
A
C
K
N
o
A
C
K
Current Read Timing
D
e
v
i
c
e
a
d
d
r
e
s
s
D
W
e
v
o
i
r
c
d
e
a
a
d
d
d
D
d
r
A
r
e
e
T
s
s
A
s
s
S
t
o
p
A
2
A
1
A
0
S
A
S
P
S
D
A
C
K
A
C
K
A
C
K
N
o
A
C
K
S
t
a
r
t
S
t
a
r
t
Random Read Timing
D
e
v
i
c
e
a
d
d
r
e
s
s
D
A
D
T
A
A
T
n
A
+
1
n
D
A
T
A
n
+
x
S
t
o
p
S
A
P
S
D
S
t
a
r
t
A
C
K
A
C
K
N
o
A
C
K
Sequential Read Timing
Rev. 1.60
5
June 25, 2010
HT24LC16
Timing Diagrams
t
H
I
G
H
t
F
t
R
t
t
L
H
O
W
S
C
L
t
S
U
:
S
T
A
D
:
S
T
A
t
S
U
:
D
A
T
t
S
U
:
S
T
O
t
H
D
:
D
A
T
S
D
D
A
A
t
S
P
t
B
U
F
t
A
A
S
V
a
l
i
d
V
a
l
i
d
O
U
T
S
C
L
S
D
A
8
t
h
b
i
t
A
C
K
W
o
r
d
n
t
W
R
S
t
o
p
S
t
a
r
t
C
o
n
d
i
t
i
o
n
C
o
n
d
i
t
i
o
n
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start con-
dition of sequential command.
Rev. 1.60
6
June 25, 2010
HT24LC16
Package Information
8-pin DIP (300mil) Outline Dimensions
A
8
5
B
1
4
H
C
D
I
G
E
F
Dimensions in inch
Nom.
Symbol
Min.
0.355
0.240
0.125
0.125
0.016
0.050
¾
Max.
0.375
0.260
0.135
0.145
0.020
0.070
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
¾
0.100
¾
0.295
¾
0.315
¾
0.375
Dimensions in mm
Nom.
Symbol
Min.
9.02
6.10
3.18
3.18
0.41
1.27
¾
Max.
9.53
6.60
3.43
3.68
0.51
1.78
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
¾
2.54
¾
7.49
¾
8.00
¾
9.53
Rev. 1.60
7
June 25, 2010
HT24LC16
8-pin SOP (150mil) Outline Dimensions
8
5
A
B
1
4
C
C
'
G
H
D
a
E
F
·
MS-012
Dimensions in inch
Nom.
Symbol
Min.
0.228
0.150
0.012
0.188
¾
Max.
0.244
0.157
0.020
0.197
0.069
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
¾
0.050
¾
¾
0.004
0.016
0.007
0°
0.010
0.050
0.010
8°
G
H
a
¾
¾
¾
Dimensions in mm
Nom.
Symbol
Min.
5.79
3.81
0.30
4.78
¾
Max.
6.20
3.99
0.51
5.00
1.75
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
¾
1.27
¾
¾
0.10
0.41
0.18
0°
0.25
1.27
0.25
8°
G
H
a
¾
¾
¾
Rev. 1.60
8
June 25, 2010
HT24LC16
8-pin TSSOP Outline Dimensions
8
5
E
1
1
4
E
D
L
A
A
2
C
q
e
A
1
B
L
1
R
0
.
1
0
y
(
4
C
O
R
N
E
R
S
)
Dimensions in inch
Nom.
Symbol
Min.
Max.
0.047
0.006
0.041
¾
A
A1
A2
B
0.041
0.002
0.031
¾
¾
¾
¾
0.010
¾
C
0.004
0.114
0.244
0.169
¾
0.006
0.122
0.260
0.177
¾
D
¾
E
¾
E1
e
¾
0.026
¾
L
0.020
0.035
¾
0.028
0.043
0.004
8°
L1
y
¾
¾
q
0°
¾
Dimensions in mm
Nom.
Symbol
Min.
1.05
0.05
0.80
¾
Max.
1.20
0.15
1.05
¾
A
A1
A2
B
¾
¾
¾
0.25
¾
C
0.11
2.90
6.20
4.30
¾
0.15
3.10
6.60
4.50
¾
D
¾
E
¾
E1
e
¾
0.65
¾
L
0.50
0.90
¾
0.70
1.10
0.10
8°
L1
y
¾
¾
q
0°
¾
Rev. 1.60
9
June 25, 2010
HT24LC16
Product Tape and Reel Specifications
Reel Dimensions
D
T
2
C
A
B
T
1
SOP 8N, TSSOP 8L
Symbol
Description
Dimensions in mm
A
B
Reel Outer Diameter
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
330.0±1.0
100.0±1.5
13.0+0.5/-0.2
C
D
2.0±0.5
12.8+0.3/-0.2
T1
T2
Space Between Flange
Reel Thickness
18.2±0.2
Rev. 1.60
10
June 25, 2010
HT24LC16
Carrier Tape Dimensions
P
0
P
1
t
D
E
F
W
B
0
C
D
1
P
K
0
A
0
R
e
e
l
H
o
l
e
I
C
p
a
c
k
a
g
e
p
i
n
1
a
n
d
t
h
a
r
e
l
o
c
a
t
e
d
o
n
t
h
e
s
a
m
e
SOP 8N
Symbol
Description
Dimensions in mm
12.0+0.3/-0.1
W
P
Carrier Tape Width
Cavity Pitch
8.0±0.1
1.75±0.1
5.5±0.1
E
Perforation Position
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
D
1.55±0.10
1.50+0.25
4.0±0.1
D1
P0
P1
A0
B0
K0
t
Cavity to Perforation (Length Direction)
Cavity Length
2.0±0.1
6.4±0.1
Cavity Width
5.2±0.1
Cavity Depth
2.1±0.1
Carrier Tape Thickness
Cover Tape Width
0.30±0.05
9.3±0.1
C
TSSOP 8L
Symbol
Description
Carrier Tape Width
Dimensions in mm
12.0+0.3/-0.1
W
P
Cavity Pitch
8.0±0.1
1.75±0.10
5.5±0.5
E
Perforation Position
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
F
D
1.5+0.1/-0.0
1.5+0.1/-0.0
4.0±0.1
D1
P0
P1
A0
B0
K0
t
Cavity to Perforation (Length Direction)
Cavity Length
2.0±0.1
7.0±0.1
Cavity Width
3.6±0.1
Cavity Depth
1.6±0.1
Carrier Tape Thickness
Cover Tape Width
0.300±0.013
9.3±0.1
C
Rev. 1.60
11
June 25, 2010
HT24LC16
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
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46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.60
12
June 25, 2010
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