HT27C010(32SOP) [HOLTEK]
Memory IC;
| 型号： | HT27C010(32SOP) |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | Memory IC |
| 文件： | 总14页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT27C010
CMOS 128K´8-Bit OTP EPROM
Features
·
·
Operating voltage: +5.0V
128K´8-bit organization
·
·
Programming voltage
Fast read access time: 70ns
-
·
VPP=12.5V±0.2V
Fast programming algorithm
-
VCC=6.0V±0.2V
·
Programming time 75ms typ.
·
High-reliability CMOS technology
·
Two line controls (OE and CE)
·
Latch-up immunity to 100mA from -1.0V to
CC+1.0V
·
·
·
Standard product identification code
Commercial temperature range (0°C to +70°C)
32-pin DIP/SOP/PLCC package
V
·
·
CMOS and TTL compatible I/O
Low power consumption
-
Active: 30mA max.
-
Standby: 1mA typ.
General Description
The HT27C010 chip family is a low-power, 1024K
(1,048,576) bit, +5V electrically one-time programmable
(OTP) read-only memories (EPROM). Organized into
128K words with 8 bits per word, it features a fast single
address location programming, typically at 75ms per
byte. Any byte can be accessed in less than 70ns with
respect to Spec. This eliminates the need for WAIT
states in high-performance microprocessor systems.
The HT27C010 has separate Output Enable (OE) and
Chip Enable (CE) controls which eliminate bus conten-
tion issues.
Block Diagram
R
o
w
X
-
D
e
c
o
d
e
r
C
e
l
l
A
r
r
a
y
A
d
d
r
e
s
s
V
C
C
C
o
l
u
m
n
V
V
S
P
S
P
Y
-
D
e
c
o
d
e
r
Y
-
G
a
t
i
n
g
A
d
d
r
e
s
s
C
E
E
C
E
&
O
E
&
S
A
C
K
T
P
G
M
&
T
E
S
T
O
&
D
Q
0
~
D
Q
7
C
o
n
t
r
o
l
L
o
g
i
c
O
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t
p
u
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B
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f
f
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r
P
G
M
Rev. 1.20
1
December 5, 2003
HT27C010
Pin Assignment
V
P
P
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
2
2
2
2
2
1
1
1
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
V
P
N
A
A
A
A
A
O
A
C
D
D
D
D
D
C
G
C
A
A
A
1
1
1
6
M
5
C
2
7
6
5
4
3
2
1
0
0
1
2
1
1
8
9
1
4
3
A
A
A
A
A
A
A
A
2
2
2
2
2
2
2
2
2
9
8
7
6
5
4
3
2
1
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
0
5
A
1
4
6
7
8
9
A
1
3
A
A
A
8
9
1
1
H
T
2
7
C
0
1
0
1
0
E
3
2
P
L
C
C
-
A
1
1
1
1
0
1
2
3
O
A
C
D
E
0
1
2
3
4
5
6
1
0
1
E
Q
Q
Q
Q
Q
E
D
Q
Q
7
7
6
5
4
3
D
D
D
Q
Q
Q
S
V
S
H
T
2
7
C
0
1
0
3
2
D
I
P
-
A
/
S
O
P
-
A
Pin Description
Pin Name
A0~A16
DQ0~DQ7
CE
I/O/C/P
Description
I
I/O
C
C
C
¾
P
I
Address inputs
Data inputs/outputs
Chip enable
OE
Output enable
PGM
Program strobe
No connection
NC
VPP
Program voltage supply
Positive power supply
VCC
VSS
I
Negative power supply, ground
Rev. 1.20
2
December 5, 2003
HT27C010
Absolute Maximum Rating
Operation Temperature Commercial..........................................................................................................0°C to +70°C
Storage Temperature.............................................................................................................................-65°C to 125 °C
Applied VCC Voltage with Respect to VSS ................................................................................................-0.6V to 7.0V
Applied Voltage on Input Pin with Respect to VSS..................................................................................... -0.6V to 7.0V
Applied Voltage on Output Pin with Respect to VSS ..........................................................................-0.6V to VCC+0.5V
Applied Voltage on A9 Pin with Respect to VSS.......................................................................................-0.6V to 13.5V
Applied VPP Voltage with Respect to VSS...............................................................................................-0.6V to 13.5V
Applied READ Voltage (Functionality is guaranteed between these limits) ..............................................+4.5V to +5.5V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Conditions
Read operation
VOH
VOL
VIH
VIL
Output High Level
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
2.4
¾
V
V
IOH=-0.4mA
IOL=2.1mA
¾
¾
¾
¾
¾
¾
¾
1.0
¾
¾
¾
0.45
VCC+0.5
0.8
Output Low Level
Input High Level
2.0
-0.3
-5
V
¾
¾
Input Low Level
V
ILI
VIN=0 to 5.5V
Input Leakage Current
Output Leakage Current
VCC Active Current
Standby Current (CMOS)
Standby Current (TTL)
VPP Read/Standby Current
5
mA
mA
mA
mA
mA
mA
ILO
VOUT=0 to 5.5V
CE=VIL, f=5MHz, IOUT=0mA
CE=VCC±0.3V
10
-10
¾
ICC
ISB1
ISB2
IPP
30
10
¾
CE=VIH
1.0
¾
CE=OE=VIL, VPP=VCC
100
¾
Programming operation
VOH
VOL
VIH
VIL
ILI
Output High Level
Output Low Level
Input High Level
6V
6V
6V
6V
6V
6V
6V
6V
2.4
V
V
IOH=-0.4mA
¾
¾
¾
¾
¾
¾
¾
¾
¾
IOL=2.1mA
0.45
¾
0.7VCC
V
CC+0.5
V
¾
¾
Input Low Level
0.8
V
-0.5
¾
VIN=VIL, VIH
Input Load Current
A9 Product ID Voltage
VCC Supply Current
VPP Supply Current
5.0
mA
V
VH
11.5
¾
12.5
40
¾
ICC
IPP
Capacitance
mA
mA
¾
CE=VIL
10
¾
CIN
VIN=0V
Input Capacitance
Output Capacitance
VPP Capacitance
5V
5V
5V
8
8
12
12
25
pF
pF
pF
¾
¾
¾
COUT
CVPP
VOUT=0V
VPP=0V
18
Rev. 1.20
3
December 5, 2003
HT27C010
A.C. Characteristics
Ta=+25°C±5°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Conditions
Read Operation
tACC
tCE
CE=OE=VIL
OE=VIL
Address to Output Delay
5V
5V
5V
70
70
30
ns
ns
ns
¾
¾
¾
Chip Enable to Output Delay
Output Enable to Output Delay
tOE
CE=VIL
CE or OE High to Output Float, Whichever
Occurred First
tDF
5V
5V
25
ns
ns
¾
¾
¾
Output Hold from Address, CE or OE,
Whichever Occurred First
tOH
0
¾
Programming Operation
tAS
Address Setup Time
OE Setup Time
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
2
2
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
75
¾
¾
¾
¾
¾
¾
ms
ms
ms
ms
ms
ns
ms
ms
ms
ms
ns
ms
tOES
tDS
Data Setup Time
2
¾
tAH
Address Hold Time
0
¾
tDH
Data Hold Time
2
¾
tDFP
tVPS
tPW
tVCS
tCES
tOE
Output Enable to Output Float Delay
VPP Setup Time
0
130
¾
2
PGM Program Pulse Width
VCC Setup Time
30
2
105
¾
CE Setup Time
2
¾
Data Valid from OE
150
¾
¾
2
tPRT
VPP Pulse Rise Time During Programming
Test waveforms and Measurements
Output Test Load
2
.
4
V
V
D D
2
.
0
V
A
M
L
C
1
.
3
V
A
C
D
r
i
v
i
n
g
e
a
s
u
r
e
m
e
n
t
L
e
v
e
l
s
e
v
e
l
0
.
8
V
(
1
N
9
1
4
)
0
.
4
5
V
3
.
3
k
tR, tF< 20ns (10% to 90%)
O
u
t
p
u
t
P
i
n
C
L
Note: CL=100pF including jig capacitance, except for
the -45 devices, where CL=30pF.
Rev. 1.20
4
December 5, 2003
HT27C010
Functional Description
Programming of the HT27C010
To activate this mode, the programming equipment
must force 12.0±0.5V on the address line A9 of the
HT27C010. Two identifier bytes may then be se-
quenced from the device outputs by toggling address
line A0 from VIL to VIH, when A1=VIH. All other address
lines must be held at VIH during Auto Product Identification
mode.
When the HT27C010 is delivered, the chip has all
1024K bits in the ²ONE², or HIGH state. ²ZEROs² are
loaded into the HT27C010 through programming.
The programming mode is entered when 12.5±0.2V is ap-
plied to the VPP pin, OE is at VIH, and CE and PGM are
VIL. For programming, the data to be programmed is ap-
plied with 8 bits in parallel to the data pins.
Byte 0 (A0=VIL) represents the manufacturer code, and
byte 1 (A0=VIH), the device code. For HT27C010, these
two identifier bytes are given in the Operation mode truth
table. All identifiers for the manufacturer and device codes
will possess odd parity, with the MSB (DQ7) defined as the
parity bit. When A1=VIL, the HT27C010 will read out the bi-
nary code of 7F, continuation code, to signify the unavail-
ability of manufacturer ID codes.
The programming flowchart in Figure 3 shows the fast
interactive programming algorithm. The interactive al-
gorithm reduces programming time by using 30ms to
105ms programming pulses and giving each address
only as many pulses as is necessary in order to reliably
program the data. After each pulse is applied to a given
address, the data in that address is verified. If the data
is not verified, additional pulses are given until it is veri-
fied or until the maximum number of pulses is reached
while sequencing through each address of the
HT27C010. This process is repeated while sequencing
through each address of the HT27C010. This part of
the programming algorithm is done at VCC=6.0V to as-
sure that each EPROM bit is programmed to a suffi-
ciently high threshold voltage. This ensures that all bits
have sufficient margin. After the final address is com-
pleted, the entire EPROM memory is read at
Read Mode
The HT27C010 has two control functions, both of which
must be logically satisfied in order to obtain data at out-
puts. Chip Enable (CE) is the power control and should
be used for device selection. Output Enable (OE) is the
output control and should be used to gate data to the
output pins, independent of device selection. Assuming
that addresses are stable, address access time (tACC) is
equal to the delay from CE to output (tCE). Data is avail-
able at the outputs (tOE) after the falling edge of OE, as-
suming the CE has been LOW and addresses have
VCC=VPP=5.25±0.25V to verify the entire memory.
been stable for at least tACC-tOE
.
Program Inhibit Mode
Standby Mode
Programming of multiple HT27C010 in parallel with dif-
ferent data is also easily accomplished by using the Pro-
gram Inhibit Mode. Except for CE, all like inputs of the
parallel HT27C010 may be common. A TTL low-level
program pulse applied to an HT27C010 CE input with
The HT27C010 has CMOS standby mode which re-
duces the maximum VCC current to 10mA. It is placed in
CMOS standby when CE is at VCC±0.3V. The
HT27C010 also has a TTL-standby mode which re-
duces the maximum VCC current to 1.0mA. It is placed
in TTL-standby when CE is at VIH. When in standby
mode, the outputs are in a high-impedance state, inde-
pendent of the OE input.
VPP=12.5±0.2V, PGM LOW, and OE HIGH will program
that HT27C010. A high-level CE input inhibits the
HT27C010 from being programmed.
Program Verify Mode
Verification should be performed on the programmed
bits to determine whether they were correctly pro-
grammed. The verification should be performed with OE
and CE at VIL, PGM at VIH, and VPP at its programming
voltage.
Two-line Output Control Function
To accommodate multiple memory connections, a
two-line control function is provided to allow for:
·
Low memory power dissipation
·
Assurance that output bus contention will not occur
Auto Product Identification
It is recommended that CE be decoded and used as the
primary device-selection function, while OE be made a
common connection to the READ line from the system
control bus. This assures that all deselected memory
devices are in their low-power standby mode and that
the output pins are only active when data is desired from
a particular memory device.
The Auto Product Identification mode allows the reading
out of a binary code from an EPROM that will identify its
manufacturer and the type. This mode is intended for
programming to automatically match the device to be
programmed with its corresponding programming algo-
rithm. This mode is functional in the 25°C±5°C ambient
temperature range that is required when programming
the HT27C010.
Rev. 1.20
5
December 5, 2003
HT27C010
System Considerations
VCC and VPP to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM ar-
rays, a 4.7mF bulk electrolytic capacitor should be used
between VCC and VPP for each eight devices. The lo-
cation of the capacitor should be close to where the
power supply is connected to the array.
During the switch between active and standby condi-
tions, transient current peaks are produced on the rising
and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1mF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
Operation Mode Truth Table
All the operation modes are shown in the table following.
Mode
CE
VIL
OE
VIL
VIH
X
PGM
X (2)
X
A0
X
A1
X
A9
VPP
VCC
VCC
VCC
VCC
VPP
VPP
VPP
VCC
VCC
Output
Dout
Read
X
Output Disable
Standby (TTL)
VIL
X
X
X
High Z
High Z
High Z
DIN
VIH
X
X
X
X
X
Standby (CMOS)
Program
VCC± 0.3V
VIL
X
X
X
X
VIH
VIL
X
VIL
VIH
X
X
X
X
Program Verify
Product Inhibit
VIL
X
X
X
DOUT
High Z
1C
VIH
X
X
X
Manufacturer Code (3)
Device Type Code (3)
VIL
VIL
VIL
X
VIL
VIH
VIH
VIH
VH (1)
VH (1)
VIL
X
01
Note:
(1) VH=12.0V ± 0.5V
(2) X=Either VIH or VIL
(3) For Manufacturer Code and Device Code, A1=VIH, When A1=VIL, both codes will read 7F
Product Identification Code
Pins
Hex
Data
Code
A0
0
A1
1
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Manufacturer
Device Type
0
0
0
0
0
0
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
0
0
1
1
0
1
1
1
1C
01
7F
7F
1
1
0
0
Continuation
1
0
A
d
d
r
e
s
s
V
a
l
i
d
A
d
d
r
e
s
s
t
C E
C
E
t
D <
t
O E
O
E
t
A C C
t
O H
O
u
t
p
u
t
V
a
l
i
d
O
u
t
p
u
t
H
I
G
H
Z
Figure 1. A.C. Waveforms for Read Operation
Rev. 1.20
6
December 5, 2003
HT27C010
R
e
a
d
P
r
o
g
r
a
m
(
V
e
r
i
f
y
)
V
I
H
A
d
d
r
e
s
s
S
t
a
b
l
e
A
d
d
r
e
s
s
V
I
L
t
A
S
t
O
E
t
A H
V
I
H
D
a
t
a
O
u
t
D
a
t
a
I
n
D
a
t
a
V
a
l
i
d
V
I
L
t
D
S
t
D H
6
5
.
.
0
0
V
V
V
C
C
t
D < P
t
V C S
1
2
5
.
.
5
0
V
t
V P S
V
P
P
V
t
P R T
V
I
H
C
E
V
I
L
t
C E S
V
I
H
P
G
M
V
I
L
t
O E S
t
P W
V
I
H
O
E
V
I
L
Figure 2. Programming Waveforms
S
T
A
R
T
A
d
d
r
e
s
s
=
<
i
r
s
t
L
o
c
a
t
i
o
n
V
C
C
V
P
P
=
1
2
.
5
V
X
=
0
P
r
o
g
r
a
m
o
n
e
7
5
m
s
P
u
l
s
e
I
n
t
e
r
a
c
t
i
v
e
S
e
c
t
i
o
n
I
n
c
r
e
m
e
n
t
X
Y
e
s
X
=
2
5
?
N
o
<
a
i
l
V
e
r
i
f
y
B
y
t
e
?
P
a
s
s
N
o
L
a
s
t
<
a
i
l
I
n
c
r
e
m
e
n
t
A
d
d
r
e
s
s
A
d
d
r
e
s
s
Y
e
s
V
C
C
=
V
P
P
=
5
.
2
5
V
V
e
r
i
f
y
S
e
c
t
i
o
n
<
a
i
l
V
e
r
i
f
y
a
l
l
D
e
v
i
c
e
<
a
i
l
e
d
B
y
t
e
s
?
P
a
s
s
D
e
v
i
c
e
P
a
s
s
e
d
N
m
m
Figure 3. Fast Programming Flowchart
Rev. 1.20
7
December 5, 2003
HT27C010
Package Information
32-pin DIP (600mil) Outline Dimensions
A
3
2
1
7
B
1
1
6
H
C
D
I
a
E
<
G
Dimensions in mil
Nom.
Symbol
Min.
1635
535
145
125
16
Max.
1665
555
155
145
20
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
50
70
¾
100
¾
¾
¾
595
635
0°
615
670
15°
¾
a
¾
Rev. 1.20
8
December 5, 2003
HT27C010
32-pin SOP (450mil) Outline Dimensions
3
2
1
7
A
B
1
1
6
C
C
'
G
H
D
a
E
<
Dimensions in mil
Nom.
Symbol
Min.
543
440
14
¾
Max.
557
450
20
A
B
C
C¢
D
E
F
¾
¾
¾
¾
¾
50
¾
¾
¾
¾
817
112
¾
100
¾
4
¾
G
H
a
32
4
38
12
0°
10°
Rev. 1.20
9
December 5, 2003
HT27C010
32-pin PLCC Outline Dimensions
A
B
4
1
3
2
3
0
5
2
9
D
C
1
3
2
1
1
4
2
0
K
E
<
J
G
H
I
Dimensions in mil
Nom.
Symbol
Min.
485
445
585
545
105
¾
Max.
495
455
595
555
115
140
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
¾
¾
50
¾
¾
¾
¾
15
¾
¾
16
22
J
24
32
K
a
8
12
0°
10°
Rev. 1.20
10
December 5, 2003
HT27C010
Product Tape and Reel Specifications
Reel Dimensions
D
T
2
C
A
B
T
1
SOP 32W
Symbol
Description
Dimensions in mm
A
B
Reel Outer Diameter
Reel Inner Diameter
330±1.0
100±0.1
13.0+0.5
-0.2
C
D
Spindle Hole Diameter
Key Slit Width
2.0±0.5
32.8+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
38.2+0.2
PLCC 32
Symbol
Description
Dimensions in mm
330±1.0
A
B
Reel Outer Diameter
Reel Inner Diameter
62±1.5
13.0+0.5
-0.2
C
D
Spindle Hole Diameter
Key Slit Width
2.0±0.5
24.8+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
30.2±0.2
Rev. 1.20
11
December 5, 2003
HT27C010
Carrier Tape Dimensions
P
0
P
1
t
D
E
<
B
0
W
C
K
1
D
1
P
K
2
A
0
SOP 32W
Symbol
Description
Dimensions in mm
32.0+0.3
-0.1
W
Carrier Tape Width
P
E
Cavity Pitch
16.0±0.1
1.75±0.1
14.2±0.1
1.55+0.1
2.0+0.25
4.0±0.1
2.0±0.1
14.7±0.1
20.9±0.1
3.0±0.1
3.4±0.1
0.35±0.05
25.5
Perforation Position
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
D
D1
P0
P1
A0
B0
K1
K2
t
Cavity to Perforation (Length Direction)
Cavity Length
Cavity Width
Cavity Depth
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
Rev. 1.20
12
December 5, 2003
HT27C010
P
0
P
1
t
D
E
<
W
B
0
C
D
1
P
K
0
A
0
PLCC 32
Symbol
Description
Dimensions in mm
24.0±0.3
W
P
E
F
Carrier Tape Width
Cavity Pitch
18.0±0.1
Perforation Position
1.75±0.1
Cavity to Perforation (Width Direction)
Perforation Diameter
11.5±0.1
D
1.5+0.1
1.55+1.0
D1
Cavity Hole Diameter
-0.05
P0
P1
A0
B0
K0
t
Perforation Pitch
4.0±0.1
2.0±0.1
13.1±0.1
15.5±0.1
3.9±0.1
0.30±0.05
21.3
Cavity to Perforation (Length Direction)
Cavity Length
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
Rev. 1.20
13
December 5, 2003
HT27C010
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (Shanghai) Inc.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor (Hong Kong) Ltd.
Block A, 3/F, Tin On Industrial Building, 777-779 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Holmate Semiconductor, Inc.
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2003 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
14
December 5, 2003
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