HT27LC010(32TSOP-A) [HOLTEK]
Memory IC;
| 型号： | HT27LC010(32TSOP-A) |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | Memory IC LTE |
| 文件： | 总9页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT27LC010
CMOS 128K´8-Bit OTP EPROM
Features
·
·
Operating voltage: +3.3V
128K´8-bit organization
·
·
Programming voltage
Fast read access time 90ns
-
VPP=12.5V±0.2V
·
Fast programming algorithm
-
VCC=6.0V±0.2V
·
Programming time 75ms typ.
·
High-reliability CMOS technology
·
Commercial and industrial temperature range
·
Latch-up immunity to 100mA from -1.0V to
CC+1.0V
·
·
·
·
Two line controls (OE and CE)
V
Standard product identification code
Commercial temperature ranges (0°C to +70°C)
32-pin DIP/SOP/TSOP/PLCC Package
·
·
CMOS and TTL compatible I/O
Low power consumption
-
Active: 15mA max.
-
Standby: 1mA typ.
General Description
The HT27LC010 chip family is a low-power, 1024K
(1,048,576) bit, +3.3V electrically one-time programma-
ble (OTP) read-only memories (EPROM). Organized
into 128K words with 8 bits per word, it features a fast
single address location programming, typically at 75ms
per byte. Any byte can be accessed in less than 90ns
with respect to Spec. This eliminates the need for WAIT
states in high-performance microprocessor systems.
The HT27LC010 has separate Output Enable (OE) and
Chip Enable (CE) controls which eliminate bus conten-
tion issues.
Block Diagram
R
o
w
X
-
D
e
c
o
d
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C
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l
A
r
r
a
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A
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V
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C
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C
C
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N
D
Y
-
D
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-
G
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A
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C
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&
O
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&
S
A
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T
&
D
Q
0
~
D
Q
7
O
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Rev. 1.10
1
May 6, 2002
HT27LC010
Pin Assignment
V
P
P
1
2
3
3
2
1
V
P
C
G
C
A
1
6
M
A
A
1
1
5
2
7
6
3
4
5
6
3
2
2
2
0
9
8
7
N
C
A
1
4
3
3
3
3
2
2
2
2
2
2
2
2
2
2
1
1
1
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
A
1
1
O
A
C
D
D
D
D
D
G
D
D
D
A
A
A
A
E
1
1
0
A
A
9
8
2
3
4
5
6
A
A
A
A
1
8
2
9
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
5
E
Q
Q
Q
Q
Q
A
A
1
1
4
3
A
A
1
1
3
4
7
6
5
4
3
D
2
1
0
2
8
6
7
8
9
A
A
5
4
7
8
2
2
6
5
A
A
9
1
2
2
2
2
2
2
2
7
6
5
4
3
2
1
A
8
N
C
P
G
M
7
8
1
A
9
H
T
2
7
L
C
0
1
0
V
C
C
H
T
2
7
L
C
0
1
0
A
1
1
0
A
A
A
A
3
2
1
0
9
1
1
1
2
2
2
2
4
3
2
1
O
E
V
P
P
N
9
3
2
P
L
C
C
-
A
1
1
1
1
0
1
2
3
3
2
T
S
O
P
-
A
O
A
E
A
A
1
1
6
5
Q
Q
Q
1
0
0
1
2
A
1
0
1
1
1
A
1
2
1
2
C
D
E
Q
C
D
E
A
A
A
A
7
6
5
4
0
1
2
3
1
3
7
D
Q
0
Q
7
1
4
1
5
D
D
Q
Q
0
1
1
1
3
4
2
1
0
9
D
D
Q
Q
6
5
1
6
D
Q
2
1
1
5
6
1
1
8
7
D
D
Q
Q
4
3
G
N
D
H
T
2
7
L
C
0
1
0
3
2
D
I
P
-
A
/
S
O
P
-
A
Pin Description
Pin Name
VPP
I/O/C/P
Description
P
I
Program voltage supply
Address inputs
A0~A16
DQ0~DQ7
CE
I/O
C
Data inputs/outputs
Chip enable
OE
C
Output enable
PGM
C
Program strobe
No connection
NC
¾
¾
VCC
Positive power supply
Absolute Maximum Rating
Operation Temperature Commercial..........................................................................................................0°C to +70°C
Storage Temperature.............................................................................................................................-65°C to 125 °C
Applied VCC Voltage with Respect to GND............................................................................................... -0.6V to 7.0V
Applied Voltage on Input Pin with Respect to GND.................................................................................... -0.6V to 7.0V
Applied Voltage on Output Pin with Respect to GND......................................................................... -0.6V to VCC+0.5V
Applied Voltage on A9 Pin with Respect to GND ..................................................................................... -0.6V to 13.5V
Applied VPP Voltage with Respect to GND..............................................................................................-0.6V to 13.5V
Applied READ Voltage (Functionality is guaranteed between these limits) ..............................................+3.0V to +3.6V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Rev. 1.10
2
May 6, 2002
HT27LC010
D.C. Characteristics
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Read operation
VOH
VOL
VIH
VIL
ILI
Output High Level
Output Low Level
Input High Level
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
2.4
¾
V
V
IOH=-0.4mA
¾
¾
¾
¾
¾
¾
¾
0.45
VCC+0.5
0.8
IOL=2.0mA
2.0
-0.3
-5
V
¾
¾
Input Low Level
V
VIN=0 to 3.6V
VOUT=0 to 3.6V
CE=VIL, f=5MHz,
Input Leakage Current
Output Leakage Current
5
mA
mA
ILO
10
-10
ICC
VCC Active Current
3.3V
15
mA
¾
¾
I
OUT=0mA
ISB1
ISB2
IPP
Standby Current (CMOS)
Standby Current (TTL)
3.3V
3.3V
3.3V
10
0.6
100
CE=VCC±0.3V
CE=VIH
¾
¾
¾
¾
¾
¾
mA
mA
mA
VPP Read/Standby Current
CE=OE=VIL, VPP=VCC
Programming operation
VOH
VOL
VIH
VIL
ILI
Output High Level
Output Low Level
Input High Level
6V
6V
6V
6V
6V
6V
6V
6V
2.4
V
V
IOH=-0.4mA
¾
¾
¾
¾
¾
¾
¾
¾
¾
IOL=2.0mA
0.45
¾
0.7VCC
V
CC+0.5
0.8
V
¾
¾
Input Low Level
V
-0.5
¾
VIN=VIL, VIH
Input Load Current
A9 Product ID Voltage
VCC Supply Current
VPP Supply Current
5.0
mA
V
VH
11.5
¾
12.5
40
¾
¾
ICC
IPP
Capacitance
mA
mA
CE=VIL
10
¾
CIN
VIN=0V
Input Capacitance
Output Capacitance
VPP Capacitance
3.3V
3.3V
3.3V
8
8
12
12
25
pF
pF
pF
¾
¾
¾
COUT
CVPP
VOUT=0V
VPP=0V
18
A.C. Characteristics
Ta=+25°C±5°C
Test Conditions
Symbol
Parameter
Min.
Max.
Typ.
Unit
VCC
Conditions
Read operation
tACC
tCE
CE=OE=VIL
OE=VIL
Address to Output Delay
3.3V
3.3V
3.3V
90
90
45
ns
ns
ns
¾
¾
¾
¾
¾
¾
Chip Enable to Output Delay
Output Enable to Output Delay
tOE
CE=VIL
CE or OE High to Output Float, Whichever
Occurred First
tDF
3.3V
3.3V
40
ns
ns
¾
¾
¾
¾
¾
Output Hold from Address, CE or OE,
Whichever Occurred First
tOH
0
¾
Rev. 1.10
3
May 6, 2002
HT27LC010
Test Conditions
Symbol
Parameter
Min.
Max.
Typ.
Unit
VCC
Conditions
Programming operation
tAS
Address Setup Time
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
2
2
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
75
¾
¾
¾
¾
¾
¾
ms
ms
ms
ms
ms
ns
ms
ms
ms
ns
ms
ms
tOES
tDS
OE Setup Time
Data Setup Time
2
¾
tAH
Address Hold Time
Data Hold Time
0
¾
tDH
2
¾
tDFP
tVPS
tPW
tVCS
tCES
tOE
Output Enable to Output Float Delay
VPP Setup Time
0
130
¾
2
PGM Program Pulse Width
VCC Setup Time
30
2
105
¾
CE Setup Time
2
¾
Data Valid from OE
150
¾
¾
2
tPRT
VPP Pulse Rise Time During Progromming 6V
Test waveforms and measurements
2
.
4
V
2
.
0
V
A
M
L
C
A
C
D
r
i
v
i
n
g
e
a
s
u
r
e
m
e
n
t
L
e
v
e
l
s
e
v
e
l
0
.
8
V
0
.
4
5
V
tR, tF< 20ns (10% to 90%)
Output test load
V
D
D
1
.
3
V
(
1
N
9
1
4
)
3
.
3
k
O
u
t
p
u
t
P
i
n
C
L
Note: CL=100pF including jig capacitance.
Product Identification Code
Pins
Hex
Data
Code
A0
0
A1
1
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Manufacturer
Device Type
0
0
0
0
0
0
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
0
0
1
1
0
1
1
1
1C
01
7F
7F
1
1
0
0
Continuation
1
0
Rev. 1.10
4
May 6, 2002
HT27LC010
Functional Description
Operation mode
All the operation modes are shown in the table following.
Mode
CE
VIL
OE
VIL
VIH
X
PGM
X (2)
X
A0
X
A1
X
A9
VPP
Output
Dout
Read
X
VCC
VCC
VCC
VCC
VPP
VPP
VPP
VCC
VCC
Output Disable
Standby (TTL)
Standby (CMOS)
Program
VIL
X
X
X
High Z
High Z
High Z
DIN
VIH
X
X
X
X
X
X
X
X
X
V
CC± 0.3V
VIL
VIH
VIL
X
VIL
VIH
X
X
X
X
Program Verify
Product Inhibit
Manufacturer Code (3)
Device Code (3)
VIL
X
X
X
DOUT
High Z
1C
VIH
X
X
X
VIL
VIL
VIL
X
VIL
VIH
VIH
VIH
VH (1)
VH (1)
VIL
X
01
Notes:
(1) ²VH² 12.0V ± 0.5V
(2) ²X² Either VIH or VIL
(3) For Manufacturer Code and Device Code, A1=VIH, When A1=VIL, both codes will read 7F
Programming of the HT27LC010
program pulse applied to an HT27LC010 CE input with
Vpp=12.5±0.2V, PGM LOW, and OE HIGH will program
that HT27LC010. A high-level CE input inhibits the
HT27LC010 from being programmed.
When the HT27LC010 is delivered, the chip has all
1024K bits in the ²ONE², or HIGH state. ²ZEROs² are
loaded into the HT27LC010 through programming.
The programming mode is entered when 12.5±0.2V is
applied to the VPP pin, OE is at VIH, and CE and PGM are
VIL. For programming, the data to be programmed is ap-
plied with 8 bits in parallel to the data pins.
Program verify mode
Verification should be performed on the programmed
bits to determine whether they were correctly pro-
grammed. The verification should be performed with OE
and CE at VIL, PGM at VIH, and VPP at its programming
voltage.
The programming flowchart in Figure 3 shows the fast
interactive programming algorithm. The interactive al-
gorithm reduces programming time by using 30ms to
105ms programming pulses and giving each address
only as many pulses as is necessary in order to reliably
program the data. After each pulse is applied to a given
address, the data in that address is verified. If the data is
not verified, additional pulses are given until it is verified
or until the maximum number of pulses is reached while
sequencing through each address of the HT27LC010.
This process is repeated while sequencing through
each address of the HT27LC010. This part of the pro-
gramming algorithm is done at VCC=6.0V to assure that
each EPROM bit is programmed to a sufficiently high
threshold voltage. This ensures that all bits have suffi-
cient margin. After the final address is completed, the
entire EPROM memory is read at VCC=VPP=3.3±0.3V to
verify the entire memory.
Auto product identification
The Auto Product Identification mode allows the reading
out of a binary code from an EPROM that will identify its
manufacturer and the type. This mode is intended for
programming to automatically match the device to be
programmed with its corresponding programming algo-
rithm. This mode is functional in the 25°C±5°C ambient
temperature range that is required when programming
the HT27LC010.
To activate this mode, the programming equipment must
force 12.0±0.5V on the address line A9 of the
HT27LC010. Two identifier bytes may then be se-
quenced from the device outputs by toggling address
line A0 from VIL to VIH, when A1=VIH. All other address
lines must be held at VIH during Auto Product Identifica-
tion mode.
Program inhibit mode
Byte 0 (A0=VIL) represents the manufacturer code, and
byte 1 (A0=VIH), the device code. For HT27LC010,
these two identifier bytes are given in the Mode Select
Table. All identifiers for the manufacturer and device
Programming of multiple HT27LC010 in parallel with dif-
ferent data is also easily accomplished by using the Pro-
gram Inhibit Mode. Except for CE, all like inputs of the
parallel HT27LC010 may be common. A TTL low-level
Rev. 1.10
5
May 6, 2002
HT27LC010
codes will possess odd parity, with the MSB (DQ7) de-
fined as the parity bit. When A1=VIL, the HT27LC010 will
read out the binary code of 7F, continuation code, to sig-
nify the unavailability of manufacturer ID codes.
Two-line output control function
To accommodate multiple memory connections, a
two-linecontrolfunctionisprovidedtoallowfor:
·
Low memory power dissipation
·
Assurance that output bus contention will not occur
Read mode
It is recommended that CE be decoded and used as the
primary device-selection function, while OE be made a
common connection to the READ line from the system
control bus. This assures that all deselected memory
devices are in their low-power standby mode and that
the output pins are only active when data is desired from
a particular memory device.
The HT27LC010 has two control functions, both of which
must be logically satisfied in order to obtain data at out-
puts.ChipEnable(CE)isthepowercontrolandshouldbe
used for device selection. Output Enable (OE) is the out-
put control and should be used to gate data to the output
pins, independent of device selection. Assuming that ad-
dressesarestable, addressaccesstime(tACC)isequalto
the delay from CE to output (tCE). Data is available at the
outputs(tOE)afterthefallingedgeofOE,assumingtheCE
has been LOW and addresses have been stable for at
System considerations
During the switch between active and standby condi-
tions, transient current peaks are produced on the rising
and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1mF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VPP to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM ar-
rays, a 4.7mF bulk electrolytic capacitor should be used
between VCC and VPP for each eight devices. The lo-
cation of the capacitor should be close to where the
power supply is connected to the array.
leasttACC-tOE
.
Standby mode
The HT27LC010 has CMOS standby mode which re-
duces the maximum VCC current to 10mA. It is placed in
CMOS standby when CE is at VCC±0.3V. The
HT27LC010 also has a TTL-standby mode which re-
duces the maximum VCC current to 0.6mA. It is placed
in TTL-standby when CE is at VIH. When in standby
mode, the outputs are in a high-impedance state, inde-
pendent of the OE input.
A
d
d
r
e
s
s
A
d
d
r
e
s
s
V
a
l
i
d
t
C E
C
E
t
D <
t
O
E
O
E
t
A C C
t
O H
O
u
t
p
u
t
V
a
l
i
d
O
u
t
p
u
t
H
I
G
H
Z
Figure 1. A.C. waveforms for read operation
Rev. 1.10
6
May 6, 2002
HT27LC010
R
e
a
d
P
r
o
g
r
a
m
(
V
e
r
i
f
y
)
V
I
H
A
d
d
r
e
s
s
A
d
d
r
e
s
s
S
t
a
b
l
e
V
I
L
t
A
S
t
O
E
t
A H
V
I
H
D
a
t
a
O
u
t
D
a
t
a
I
n
D
a
t
a
V
a
l
i
d
V
I
L
t
D
S
t
D H
6
5
.
.
0
0
V
V
V
C
C
t
D < P
t
V C S
1
2
5
.
.
5
0
V
t
V P S
V
P
P
V
t
P R T
V
I
H
C
E
V
I
L
t
C E S
V
I
H
P
G
M
V
I
L
t
O E S
t
P W
V
I
H
O
E
V
I
L
Figure 2. Programming waveforms
Rev. 1.10
7
May 6, 2002
HT27LC010
S
T
A
R
T
A
d
d
r
e
s
s
=
<
i
r
s
t
L
o
c
a
t
i
o
n
V
C
C
V
P
P
=
1
2
.
5
V
X
=
0
P
r
o
g
r
a
m
m
o n e 7 5 s P u l s e
I
n
t
e
r
a
c
t
i
v
e
S
e
c
t
i
o
n
I
n
c
r
e
m
e
n
t
X
Y
e
s
X
=
2
5
?
N
o
<
a
i
l
V
e
r
i
f
y
B
y
t
e
?
P
a
s
s
L
a
s
t
<
a
i
l
N
o
I
n
c
r
e
m
e
n
t
A
d
d
r
e
s
s
A
d
d
r
e
s
s
Y
e
s
V
C
C
=
V
P
P
= 3 . 3 V
V
e
r
i
f
y
S
e
c
t
i
o
n
<
a
i
l
V
e
r
i
f
y
a
l
l
D
e
v
i
c
e
<
a
i
l
e
d
B
y
t
e
s
?
P
a
s
s
D
e
v
i
c
e
P
a
s
s
e
d
N
m
m
Figure 3. Fast programming flowchart
Rev. 1.10
8
May 6, 2002
HT27LC010
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Sales Office)
11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Holtek Semiconductor (Shanghai) Inc.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holmate Technology Corp.
48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most
up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
9
May 6, 2002
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